xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Garpu 0
Kode Masalah Tarik Permintaan Actions Packages Projects Rilis Wiki Kegiatan

MIPS: Netlogic: Fix frequency calculation register

Telusuri Sumber 
Change the PIC frequency calculation to use the register that has the
current configuration. The existing code used the register that is
written to change frequency, which can have an invalid value if the
firmware did not set it up correctly.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8885/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ganesan Ramalingam
2015-01-07 16:58:27 +05:30
committed by Ralf Baechle
orang tua 72e0605b43
melakukan a3613be442
2 mengubah file dengan 7 tambahan dan 4 penghapusan
Download Patch File Download Diff File Expand all files Collapse all files

8
arch/mips/netlogic/xlp/nlm_hal.c
Melihat File

@@ -332,7 +332,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
/* Find the clock source PLL device for PIC */
if (cpu_xlp9xx) {
reg_select = nlm_read_sys_reg(clockbase,
SYS_9XX_CLK_DEV_SEL) & 0x3;
SYS_9XX_CLK_DEV_SEL_REG) & 0x3;
switch (reg_select) {
case 0:
ctrl_val0 = nlm_read_sys_reg(clockbase,
@@ -361,7 +361,7 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
}
} else {
reg_select = (nlm_read_sys_reg(sysbase,
SYS_CLK_DEV_SEL) >> 22) & 0x3;
SYS_CLK_DEV_SEL_REG) >> 22) & 0x3;
switch (reg_select) {
case 0:
ctrl_val0 = nlm_read_sys_reg(sysbase,
@@ -425,10 +425,10 @@ static unsigned int nlm_xlp2_get_pic_frequency(int node)
/* PIC post divider, which happens after PLL */
if (cpu_xlp9xx)
pic_div = nlm_read_sys_reg(clockbase,
SYS_9XX_CLK_DEV_DIV) & 0x3;
SYS_9XX_CLK_DEV_DIV_REG) & 0x3;
else
pic_div = (nlm_read_sys_reg(sysbase,
SYS_CLK_DEV_DIV) >> 22) & 0x3;
SYS_CLK_DEV_DIV_REG) >> 22) & 0x3;
do_div(pll_out_freq_num, 1 << pic_div);
return pll_out_freq_num;