Merge tag 'irqchip-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier - Core pseudo-NMI handling code - Allow the default irq domain to be retrieved - A new interrupt controller for the Loongson LS1X platform - Affinity support for the SiFive PLIC - Better support for the iMX irqsteer driver - NUMA aware memory allocations for GICv3 - A handful of other fixes (i8259, GICv3, PLIC)
This commit is contained in:
Thomas Gleixner
@@ -406,6 +406,15 @@ config IMX_IRQSTEER
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help
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Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
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config LS1X_IRQ
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bool "Loongson-1 Interrupt Controller"
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depends on MACH_LOONGSON32
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default y
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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help
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Support for the Loongson-1 platform Interrupt Controller.
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endmenu
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config SIFIVE_PLIC
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@@ -94,3 +94,4 @@ obj-$(CONFIG_CSKY_APB_INTC) += irq-csky-apb-intc.o
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obj-$(CONFIG_SIFIVE_PLIC) += irq-sifive-plic.o
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obj-$(CONFIG_IMX_IRQSTEER) += irq-imx-irqsteer.o
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obj-$(CONFIG_MADERA_IRQ) += irq-madera.o
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obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o
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@@ -129,8 +129,9 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct brcmstb_l2_intc_data *b = gc->private;
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unsigned long flags;
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irq_gc_lock(gc);
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irq_gc_lock_irqsave(gc, flags);
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/* Save the current mask */
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b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
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@@ -139,7 +140,7 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d)
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irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
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irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
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}
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irq_gc_unlock(gc);
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irq_gc_unlock_irqrestore(gc, flags);
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}
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static void brcmstb_l2_intc_resume(struct irq_data *d)
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@@ -147,8 +148,9 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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struct brcmstb_l2_intc_data *b = gc->private;
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unsigned long flags;
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irq_gc_lock(gc);
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irq_gc_lock_irqsave(gc, flags);
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if (ct->chip.irq_ack) {
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/* Clear unmasked non-wakeup interrupts */
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irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
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@@ -158,7 +160,7 @@ static void brcmstb_l2_intc_resume(struct irq_data *d)
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/* Restore the saved mask */
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irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
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irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
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irq_gc_unlock(gc);
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irq_gc_unlock_irqrestore(gc, flags);
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}
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static int __init brcmstb_l2_intc_of_init(struct device_node *np,
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@@ -1737,6 +1737,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
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u64 type = GITS_BASER_TYPE(val);
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u64 baser_phys, tmp;
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u32 alloc_pages;
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struct page *page;
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void *base;
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retry_alloc_baser:
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@@ -1749,10 +1750,11 @@ retry_alloc_baser:
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order = get_order(GITS_BASER_PAGES_MAX * psz);
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}
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base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
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if (!base)
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page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
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if (!page)
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return -ENOMEM;
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base = (void *)page_address(page);
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baser_phys = virt_to_phys(base);
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/* Check if the physical address of the memory is above 48bits */
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@@ -1946,6 +1948,8 @@ static int its_alloc_tables(struct its_node *its)
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indirect = its_parse_indirect_baser(its, baser,
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psz, &order,
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its->device_ids);
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break;
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case GITS_BASER_TYPE_VCPU:
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indirect = its_parse_indirect_baser(its, baser,
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psz, &order,
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@@ -2236,7 +2240,8 @@ static struct its_baser *its_get_baser(struct its_node *its, u32 type)
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return NULL;
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}
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static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
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static bool its_alloc_table_entry(struct its_node *its,
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struct its_baser *baser, u32 id)
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{
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struct page *page;
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u32 esz, idx;
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@@ -2256,7 +2261,8 @@ static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
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/* Allocate memory for 2nd level table */
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if (!table[idx]) {
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page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz));
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page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
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get_order(baser->psz));
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if (!page)
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return false;
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@@ -2287,7 +2293,7 @@ static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
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if (!baser)
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return (ilog2(dev_id) < its->device_ids);
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return its_alloc_table_entry(baser, dev_id);
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return its_alloc_table_entry(its, baser, dev_id);
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}
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static bool its_alloc_vpe_table(u32 vpe_id)
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@@ -2311,7 +2317,7 @@ static bool its_alloc_vpe_table(u32 vpe_id)
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if (!baser)
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return false;
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if (!its_alloc_table_entry(baser, vpe_id))
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if (!its_alloc_table_entry(its, baser, vpe_id))
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return false;
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}
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@@ -2345,7 +2351,7 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
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nr_ites = max(2, nvecs);
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sz = nr_ites * its->ite_size;
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sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
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itt = kzalloc(sz, GFP_KERNEL);
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itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
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if (alloc_lpis) {
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lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
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if (lpi_map)
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@@ -3487,6 +3493,7 @@ static int __init its_probe_one(struct resource *res,
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void __iomem *its_base;
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u32 val, ctlr;
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u64 baser, tmp, typer;
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struct page *page;
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int err;
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its_base = ioremap(res->start, resource_size(res));
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@@ -3542,12 +3549,13 @@ static int __init its_probe_one(struct resource *res,
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its->numa_node = numa_node;
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its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
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get_order(ITS_CMD_QUEUE_SZ));
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if (!its->cmd_base) {
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page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
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get_order(ITS_CMD_QUEUE_SZ));
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if (!page) {
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err = -ENOMEM;
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goto out_free_its;
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}
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its->cmd_base = (void *)page_address(page);
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its->cmd_write = its->cmd_base;
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its->fwnode_handle = handle;
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its->get_msi_base = its_irq_get_msi_base;
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@@ -225,14 +225,6 @@ static struct syscore_ops i8259_syscore_ops = {
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.shutdown = i8259A_shutdown,
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};
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static int __init i8259A_init_sysfs(void)
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{
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register_syscore_ops(&i8259_syscore_ops);
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return 0;
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}
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device_initcall(i8259A_init_sysfs);
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static void init_8259A(int auto_eoi)
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{
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unsigned long flags;
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@@ -332,6 +324,7 @@ struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
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panic("Failed to add i8259 IRQ domain");
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setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
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register_syscore_ops(&i8259_syscore_ops);
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return domain;
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}
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@@ -10,10 +10,11 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/spinlock.h>
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#define CTRL_STRIDE_OFF(_t, _r) (_t * 8 * _r)
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#define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r)
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#define CHANCTRL 0x0
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#define CHANMASK(n, t) (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
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#define CHANSET(n, t) (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
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@@ -21,12 +22,15 @@
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#define CHAN_MINTDIS(t) (CTRL_STRIDE_OFF(t, 3) + 0x4)
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#define CHAN_MASTRSTAT(t) (CTRL_STRIDE_OFF(t, 3) + 0x8)
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#define CHAN_MAX_OUTPUT_INT 0x8
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struct irqsteer_data {
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void __iomem *regs;
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struct clk *ipg_clk;
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int irq;
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int irq[CHAN_MAX_OUTPUT_INT];
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int irq_count;
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raw_spinlock_t lock;
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int irq_groups;
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int reg_num;
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int channel;
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struct irq_domain *domain;
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u32 *saved_reg;
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@@ -35,7 +39,7 @@ struct irqsteer_data {
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static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
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unsigned long irqnum)
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{
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return (data->irq_groups * 2 - irqnum / 32 - 1);
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return (data->reg_num - irqnum / 32 - 1);
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}
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static void imx_irqsteer_irq_unmask(struct irq_data *d)
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@@ -46,9 +50,9 @@ static void imx_irqsteer_irq_unmask(struct irq_data *d)
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u32 val;
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raw_spin_lock_irqsave(&data->lock, flags);
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val = readl_relaxed(data->regs + CHANMASK(idx, data->irq_groups));
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val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
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val |= BIT(d->hwirq % 32);
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writel_relaxed(val, data->regs + CHANMASK(idx, data->irq_groups));
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writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
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raw_spin_unlock_irqrestore(&data->lock, flags);
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}
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@@ -60,9 +64,9 @@ static void imx_irqsteer_irq_mask(struct irq_data *d)
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u32 val;
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raw_spin_lock_irqsave(&data->lock, flags);
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val = readl_relaxed(data->regs + CHANMASK(idx, data->irq_groups));
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val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
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val &= ~BIT(d->hwirq % 32);
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writel_relaxed(val, data->regs + CHANMASK(idx, data->irq_groups));
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writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
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raw_spin_unlock_irqrestore(&data->lock, flags);
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}
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@@ -87,23 +91,47 @@ static const struct irq_domain_ops imx_irqsteer_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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};
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static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
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{
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int i;
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for (i = 0; i < data->irq_count; i++) {
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if (data->irq[i] == irq)
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return i * 64;
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}
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return -EINVAL;
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}
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static void imx_irqsteer_irq_handler(struct irq_desc *desc)
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{
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struct irqsteer_data *data = irq_desc_get_handler_data(desc);
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int i;
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int hwirq;
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int irq, i;
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chained_irq_enter(irq_desc_get_chip(desc), desc);
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for (i = 0; i < data->irq_groups * 64; i += 32) {
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int idx = imx_irqsteer_get_reg_index(data, i);
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irq = irq_desc_get_irq(desc);
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hwirq = imx_irqsteer_get_hwirq_base(data, irq);
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if (hwirq < 0) {
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pr_warn("%s: unable to get hwirq base for irq %d\n",
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__func__, irq);
|
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return;
|
||||
}
|
||||
|
||||
for (i = 0; i < 2; i++, hwirq += 32) {
|
||||
int idx = imx_irqsteer_get_reg_index(data, hwirq);
|
||||
unsigned long irqmap;
|
||||
int pos, virq;
|
||||
|
||||
if (hwirq >= data->reg_num * 32)
|
||||
break;
|
||||
|
||||
irqmap = readl_relaxed(data->regs +
|
||||
CHANSTATUS(idx, data->irq_groups));
|
||||
CHANSTATUS(idx, data->reg_num));
|
||||
|
||||
for_each_set_bit(pos, &irqmap, 32) {
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virq = irq_find_mapping(data->domain, pos + i);
|
||||
virq = irq_find_mapping(data->domain, pos + hwirq);
|
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if (virq)
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generic_handle_irq(virq);
|
||||
}
|
||||
@@ -117,7 +145,8 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
||||
struct device_node *np = pdev->dev.of_node;
|
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struct irqsteer_data *data;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
u32 irqs_num;
|
||||
int i, ret;
|
||||
|
||||
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
@@ -130,12 +159,6 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
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return PTR_ERR(data->regs);
|
||||
}
|
||||
|
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data->irq = platform_get_irq(pdev, 0);
|
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if (data->irq <= 0) {
|
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dev_err(&pdev->dev, "failed to get irq\n");
|
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return -ENODEV;
|
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}
|
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|
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data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
|
||||
if (IS_ERR(data->ipg_clk)) {
|
||||
ret = PTR_ERR(data->ipg_clk);
|
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@@ -146,12 +169,19 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
||||
|
||||
raw_spin_lock_init(&data->lock);
|
||||
|
||||
of_property_read_u32(np, "fsl,irq-groups", &data->irq_groups);
|
||||
of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
|
||||
of_property_read_u32(np, "fsl,channel", &data->channel);
|
||||
|
||||
/*
|
||||
* There is one output irq for each group of 64 inputs.
|
||||
* One register bit map can represent 32 input interrupts.
|
||||
*/
|
||||
data->irq_count = DIV_ROUND_UP(irqs_num, 64);
|
||||
data->reg_num = irqs_num / 32;
|
||||
|
||||
if (IS_ENABLED(CONFIG_PM_SLEEP)) {
|
||||
data->saved_reg = devm_kzalloc(&pdev->dev,
|
||||
sizeof(u32) * data->irq_groups * 2,
|
||||
sizeof(u32) * data->reg_num,
|
||||
GFP_KERNEL);
|
||||
if (!data->saved_reg)
|
||||
return -ENOMEM;
|
||||
@@ -166,27 +196,48 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
|
||||
/* steer all IRQs into configured channel */
|
||||
writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
|
||||
|
||||
data->domain = irq_domain_add_linear(np, data->irq_groups * 64,
|
||||
data->domain = irq_domain_add_linear(np, data->reg_num * 32,
|
||||
&imx_irqsteer_domain_ops, data);
|
||||
if (!data->domain) {
|
||||
dev_err(&pdev->dev, "failed to create IRQ domain\n");
|
||||
clk_disable_unprepare(data->ipg_clk);
|
||||
return -ENOMEM;
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(data->irq, imx_irqsteer_irq_handler,
|
||||
data);
|
||||
if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
for (i = 0; i < data->irq_count; i++) {
|
||||
data->irq[i] = irq_of_parse_and_map(np, i);
|
||||
if (!data->irq[i]) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
irq_set_chained_handler_and_data(data->irq[i],
|
||||
imx_irqsteer_irq_handler,
|
||||
data);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
clk_disable_unprepare(data->ipg_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int imx_irqsteer_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < irqsteer_data->irq_count; i++)
|
||||
irq_set_chained_handler_and_data(irqsteer_data->irq[i],
|
||||
NULL, NULL);
|
||||
|
||||
irq_set_chained_handler_and_data(irqsteer_data->irq, NULL, NULL);
|
||||
irq_domain_remove(irqsteer_data->domain);
|
||||
|
||||
clk_disable_unprepare(irqsteer_data->ipg_clk);
|
||||
@@ -199,9 +250,9 @@ static void imx_irqsteer_save_regs(struct irqsteer_data *data)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < data->irq_groups * 2; i++)
|
||||
for (i = 0; i < data->reg_num; i++)
|
||||
data->saved_reg[i] = readl_relaxed(data->regs +
|
||||
CHANMASK(i, data->irq_groups));
|
||||
CHANMASK(i, data->reg_num));
|
||||
}
|
||||
|
||||
static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
|
||||
@@ -209,9 +260,9 @@ static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
|
||||
int i;
|
||||
|
||||
writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
|
||||
for (i = 0; i < data->irq_groups * 2; i++)
|
||||
for (i = 0; i < data->reg_num; i++)
|
||||
writel_relaxed(data->saved_reg[i],
|
||||
data->regs + CHANMASK(i, data->irq_groups));
|
||||
data->regs + CHANMASK(i, data->reg_num));
|
||||
}
|
||||
|
||||
static int imx_irqsteer_suspend(struct device *dev)
|
||||
|
||||
192
drivers/irqchip/irq-ls1x.c
Normal file
192
drivers/irqchip/irq-ls1x.c
Normal file
@@ -0,0 +1,192 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2019, Jiaxun Yang <jiaxun.yang@flygoat.com>
|
||||
* Loongson-1 platform IRQ support
|
||||
*/
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
|
||||
#define LS_REG_INTC_STATUS 0x00
|
||||
#define LS_REG_INTC_EN 0x04
|
||||
#define LS_REG_INTC_SET 0x08
|
||||
#define LS_REG_INTC_CLR 0x0c
|
||||
#define LS_REG_INTC_POL 0x10
|
||||
#define LS_REG_INTC_EDGE 0x14
|
||||
|
||||
/**
|
||||
* struct ls1x_intc_priv - private ls1x-intc data.
|
||||
* @domain: IRQ domain.
|
||||
* @intc_base: IO Base of intc registers.
|
||||
*/
|
||||
|
||||
struct ls1x_intc_priv {
|
||||
struct irq_domain *domain;
|
||||
void __iomem *intc_base;
|
||||
};
|
||||
|
||||
|
||||
static void ls1x_chained_handle_irq(struct irq_desc *desc)
|
||||
{
|
||||
struct ls1x_intc_priv *priv = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
u32 pending;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
pending = readl(priv->intc_base + LS_REG_INTC_STATUS) &
|
||||
readl(priv->intc_base + LS_REG_INTC_EN);
|
||||
|
||||
if (!pending)
|
||||
spurious_interrupt();
|
||||
|
||||
while (pending) {
|
||||
int bit = __ffs(pending);
|
||||
|
||||
generic_handle_irq(irq_find_mapping(priv->domain, bit));
|
||||
pending &= ~BIT(bit);
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static void ls_intc_set_bit(struct irq_chip_generic *gc,
|
||||
unsigned int offset,
|
||||
u32 mask, bool set)
|
||||
{
|
||||
if (set)
|
||||
writel(readl(gc->reg_base + offset) | mask,
|
||||
gc->reg_base + offset);
|
||||
else
|
||||
writel(readl(gc->reg_base + offset) & ~mask,
|
||||
gc->reg_base + offset);
|
||||
}
|
||||
|
||||
static int ls_intc_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
|
||||
u32 mask = data->mask;
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
|
||||
ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
irqd_set_trigger_type(data, type);
|
||||
return irq_setup_alt_chip(data, type);
|
||||
}
|
||||
|
||||
|
||||
static int __init ls1x_intc_of_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_chip_type *ct;
|
||||
struct ls1x_intc_priv *priv;
|
||||
int parent_irq, err = 0;
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->intc_base = of_iomap(node, 0);
|
||||
if (!priv->intc_base) {
|
||||
err = -ENODEV;
|
||||
goto out_free_priv;
|
||||
}
|
||||
|
||||
parent_irq = irq_of_parse_and_map(node, 0);
|
||||
if (!parent_irq) {
|
||||
pr_err("ls1x-irq: unable to get parent irq\n");
|
||||
err = -ENODEV;
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
/* Set up an IRQ domain */
|
||||
priv->domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
|
||||
NULL);
|
||||
if (!priv->domain) {
|
||||
pr_err("ls1x-irq: cannot add IRQ domain\n");
|
||||
goto out_iounmap;
|
||||
}
|
||||
|
||||
err = irq_alloc_domain_generic_chips(priv->domain, 32, 2,
|
||||
node->full_name, handle_level_irq,
|
||||
IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0,
|
||||
IRQ_GC_INIT_MASK_CACHE);
|
||||
if (err) {
|
||||
pr_err("ls1x-irq: unable to register IRQ domain\n");
|
||||
goto out_free_domain;
|
||||
}
|
||||
|
||||
/* Mask all irqs */
|
||||
writel(0x0, priv->intc_base + LS_REG_INTC_EN);
|
||||
|
||||
/* Ack all irqs */
|
||||
writel(0xffffffff, priv->intc_base + LS_REG_INTC_CLR);
|
||||
|
||||
/* Set all irqs to high level triggered */
|
||||
writel(0xffffffff, priv->intc_base + LS_REG_INTC_POL);
|
||||
|
||||
gc = irq_get_domain_generic_chip(priv->domain, 0);
|
||||
|
||||
gc->reg_base = priv->intc_base;
|
||||
|
||||
ct = gc->chip_types;
|
||||
ct[0].type = IRQ_TYPE_LEVEL_MASK;
|
||||
ct[0].regs.mask = LS_REG_INTC_EN;
|
||||
ct[0].regs.ack = LS_REG_INTC_CLR;
|
||||
ct[0].chip.irq_unmask = irq_gc_mask_set_bit;
|
||||
ct[0].chip.irq_mask = irq_gc_mask_clr_bit;
|
||||
ct[0].chip.irq_ack = irq_gc_ack_set_bit;
|
||||
ct[0].chip.irq_set_type = ls_intc_set_type;
|
||||
ct[0].handler = handle_level_irq;
|
||||
|
||||
ct[1].type = IRQ_TYPE_EDGE_BOTH;
|
||||
ct[1].regs.mask = LS_REG_INTC_EN;
|
||||
ct[1].regs.ack = LS_REG_INTC_CLR;
|
||||
ct[1].chip.irq_unmask = irq_gc_mask_set_bit;
|
||||
ct[1].chip.irq_mask = irq_gc_mask_clr_bit;
|
||||
ct[1].chip.irq_ack = irq_gc_ack_set_bit;
|
||||
ct[1].chip.irq_set_type = ls_intc_set_type;
|
||||
ct[1].handler = handle_edge_irq;
|
||||
|
||||
irq_set_chained_handler_and_data(parent_irq,
|
||||
ls1x_chained_handle_irq, priv);
|
||||
|
||||
return 0;
|
||||
|
||||
out_free_domain:
|
||||
irq_domain_remove(priv->domain);
|
||||
out_iounmap:
|
||||
iounmap(priv->intc_base);
|
||||
out_free_priv:
|
||||
kfree(priv);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(ls1x_intc, "loongson,ls1x-intc", ls1x_intc_of_init);
|
||||
@@ -59,62 +59,83 @@ static void __iomem *plic_regs;
|
||||
|
||||
struct plic_handler {
|
||||
bool present;
|
||||
int ctxid;
|
||||
void __iomem *hart_base;
|
||||
/*
|
||||
* Protect mask operations on the registers given that we can't
|
||||
* assume atomic memory operations work on them.
|
||||
*/
|
||||
raw_spinlock_t enable_lock;
|
||||
void __iomem *enable_base;
|
||||
};
|
||||
static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
|
||||
|
||||
static inline void __iomem *plic_hart_offset(int ctxid)
|
||||
static inline void plic_toggle(struct plic_handler *handler,
|
||||
int hwirq, int enable)
|
||||
{
|
||||
return plic_regs + CONTEXT_BASE + ctxid * CONTEXT_PER_HART;
|
||||
}
|
||||
|
||||
static inline u32 __iomem *plic_enable_base(int ctxid)
|
||||
{
|
||||
return plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART;
|
||||
}
|
||||
|
||||
/*
|
||||
* Protect mask operations on the registers given that we can't assume that
|
||||
* atomic memory operations work on them.
|
||||
*/
|
||||
static DEFINE_RAW_SPINLOCK(plic_toggle_lock);
|
||||
|
||||
static inline void plic_toggle(int ctxid, int hwirq, int enable)
|
||||
{
|
||||
u32 __iomem *reg = plic_enable_base(ctxid) + (hwirq / 32);
|
||||
u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32);
|
||||
u32 hwirq_mask = 1 << (hwirq % 32);
|
||||
|
||||
raw_spin_lock(&plic_toggle_lock);
|
||||
raw_spin_lock(&handler->enable_lock);
|
||||
if (enable)
|
||||
writel(readl(reg) | hwirq_mask, reg);
|
||||
else
|
||||
writel(readl(reg) & ~hwirq_mask, reg);
|
||||
raw_spin_unlock(&plic_toggle_lock);
|
||||
raw_spin_unlock(&handler->enable_lock);
|
||||
}
|
||||
|
||||
static inline void plic_irq_toggle(struct irq_data *d, int enable)
|
||||
static inline void plic_irq_toggle(const struct cpumask *mask,
|
||||
int hwirq, int enable)
|
||||
{
|
||||
int cpu;
|
||||
|
||||
writel(enable, plic_regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
|
||||
for_each_cpu(cpu, irq_data_get_affinity_mask(d)) {
|
||||
writel(enable, plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID);
|
||||
for_each_cpu(cpu, mask) {
|
||||
struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
|
||||
|
||||
if (handler->present)
|
||||
plic_toggle(handler->ctxid, d->hwirq, enable);
|
||||
plic_toggle(handler, hwirq, enable);
|
||||
}
|
||||
}
|
||||
|
||||
static void plic_irq_enable(struct irq_data *d)
|
||||
{
|
||||
plic_irq_toggle(d, 1);
|
||||
unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
|
||||
cpu_online_mask);
|
||||
if (WARN_ON_ONCE(cpu >= nr_cpu_ids))
|
||||
return;
|
||||
plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
|
||||
}
|
||||
|
||||
static void plic_irq_disable(struct irq_data *d)
|
||||
{
|
||||
plic_irq_toggle(d, 0);
|
||||
plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static int plic_set_affinity(struct irq_data *d,
|
||||
const struct cpumask *mask_val, bool force)
|
||||
{
|
||||
unsigned int cpu;
|
||||
|
||||
if (force)
|
||||
cpu = cpumask_first(mask_val);
|
||||
else
|
||||
cpu = cpumask_any_and(mask_val, cpu_online_mask);
|
||||
|
||||
if (cpu >= nr_cpu_ids)
|
||||
return -EINVAL;
|
||||
|
||||
if (!irqd_irq_disabled(d)) {
|
||||
plic_irq_toggle(cpu_possible_mask, d->hwirq, 0);
|
||||
plic_irq_toggle(cpumask_of(cpu), d->hwirq, 1);
|
||||
}
|
||||
|
||||
irq_data_update_effective_affinity(d, cpumask_of(cpu));
|
||||
|
||||
return IRQ_SET_MASK_OK_DONE;
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct irq_chip plic_chip = {
|
||||
.name = "SiFive PLIC",
|
||||
/*
|
||||
@@ -123,6 +144,9 @@ static struct irq_chip plic_chip = {
|
||||
*/
|
||||
.irq_enable = plic_irq_enable,
|
||||
.irq_disable = plic_irq_disable,
|
||||
#ifdef CONFIG_SMP
|
||||
.irq_set_affinity = plic_set_affinity,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
|
||||
@@ -150,7 +174,7 @@ static struct irq_domain *plic_irqdomain;
|
||||
static void plic_handle_irq(struct pt_regs *regs)
|
||||
{
|
||||
struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
|
||||
void __iomem *claim = plic_hart_offset(handler->ctxid) + CONTEXT_CLAIM;
|
||||
void __iomem *claim = handler->hart_base + CONTEXT_CLAIM;
|
||||
irq_hw_number_t hwirq;
|
||||
|
||||
WARN_ON_ONCE(!handler->present);
|
||||
@@ -186,7 +210,7 @@ static int plic_find_hart_id(struct device_node *node)
|
||||
static int __init plic_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
int error = 0, nr_handlers, nr_mapped = 0, i;
|
||||
int error = 0, nr_contexts, nr_handlers = 0, i;
|
||||
u32 nr_irqs;
|
||||
|
||||
if (plic_regs) {
|
||||
@@ -203,10 +227,10 @@ static int __init plic_init(struct device_node *node,
|
||||
if (WARN_ON(!nr_irqs))
|
||||
goto out_iounmap;
|
||||
|
||||
nr_handlers = of_irq_count(node);
|
||||
if (WARN_ON(!nr_handlers))
|
||||
nr_contexts = of_irq_count(node);
|
||||
if (WARN_ON(!nr_contexts))
|
||||
goto out_iounmap;
|
||||
if (WARN_ON(nr_handlers < num_possible_cpus()))
|
||||
if (WARN_ON(nr_contexts < num_possible_cpus()))
|
||||
goto out_iounmap;
|
||||
|
||||
error = -ENOMEM;
|
||||
@@ -215,7 +239,7 @@ static int __init plic_init(struct device_node *node,
|
||||
if (WARN_ON(!plic_irqdomain))
|
||||
goto out_iounmap;
|
||||
|
||||
for (i = 0; i < nr_handlers; i++) {
|
||||
for (i = 0; i < nr_contexts; i++) {
|
||||
struct of_phandle_args parent;
|
||||
struct plic_handler *handler;
|
||||
irq_hw_number_t hwirq;
|
||||
@@ -237,19 +261,33 @@ static int __init plic_init(struct device_node *node,
|
||||
}
|
||||
|
||||
cpu = riscv_hartid_to_cpuid(hartid);
|
||||
if (cpu < 0) {
|
||||
pr_warn("Invalid cpuid for context %d\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
handler = per_cpu_ptr(&plic_handlers, cpu);
|
||||
if (handler->present) {
|
||||
pr_warn("handler already present for context %d.\n", i);
|
||||
continue;
|
||||
}
|
||||
|
||||
handler->present = true;
|
||||
handler->ctxid = i;
|
||||
handler->hart_base =
|
||||
plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART;
|
||||
raw_spin_lock_init(&handler->enable_lock);
|
||||
handler->enable_base =
|
||||
plic_regs + ENABLE_BASE + i * ENABLE_PER_HART;
|
||||
|
||||
/* priority must be > threshold to trigger an interrupt */
|
||||
writel(0, plic_hart_offset(i) + CONTEXT_THRESHOLD);
|
||||
writel(0, handler->hart_base + CONTEXT_THRESHOLD);
|
||||
for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
|
||||
plic_toggle(i, hwirq, 0);
|
||||
nr_mapped++;
|
||||
plic_toggle(handler, hwirq, 0);
|
||||
nr_handlers++;
|
||||
}
|
||||
|
||||
pr_info("mapped %d interrupts to %d (out of %d) handlers.\n",
|
||||
nr_irqs, nr_mapped, nr_handlers);
|
||||
pr_info("mapped %d interrupts with %d handlers for %d contexts.\n",
|
||||
nr_irqs, nr_handlers, nr_contexts);
|
||||
set_handle_irq(plic_handle_irq);
|
||||
return 0;
|
||||
|
||||
|
||||
Reference in New Issue
Block a user