Merge tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "This has two exciting community drivers for ARM Mali accelerators. Since ARM has never been open source friendly on the GPU side of the house, the community has had to create open source drivers for the Mali GPUs. Lima covers the older t4xx and panfrost the newer 6xx/7xx series. Well done to all involved and hopefully this will help ARM head in the right direction. There is also now the ability if you don't have any of the legacy drivers enabled (pre-KMS) to remove all the pre-KMS support code from the core drm, this saves 10% or so in codesize on my machine. i915 also enable Icelake/Elkhart Lake Gen11 GPUs by default, vboxvideo moves out of staging. There are also some rcar-du patches which crossover with media tree but all should be acked by Mauro. Summary: uapi changes: - Colorspace connector property - fourcc - new YUV formts - timeline sync objects initially merged - expose FB_DAMAGE_CLIPS to atomic userspace new drivers: - vboxvideo: moved out of staging - aspeed: ASPEED SoC BMC chip display support - lima: ARM Mali4xx GPU acceleration driver support - panfrost: ARM Mali6xx/7xx Midgard/Bitfrost acceleration driver support core: - component helper docs - unplugging fixes - devm device init - MIPI/DSI rate control - shmem backed gem objects - connector, display_info, edid_quirks cleanups - dma_buf fence chain support - 64-bit dma-fence seqno comparison fixes - move initial fb config code to core - gem fence array helpers for Lima - ability to remove legacy support code if no drivers requires it (removes 10% of drm.ko size) - lease fixes ttm: - unified DRM_FILE_PAGE_OFFSET handling - Account for kernel allocations in kernel zone only panel: - OSD070T1718-19TS panel support - panel-tpo-td028ttec1 backlight support - Ronbo RB070D30 MIPI/DSI - Feiyang FY07024DI26A30-D MIPI-DSI panel - Rocktech jh057n00900 MIPI-DSI panel i915: - Comet Lake (Gen9) PCI IDs - Updated Icelake PCI IDs - Elkhartlake (Gen11) support - DP MST property addtions - plane and watermark fixes - Icelake port sync and VEBOX disable fixes - struct_mutex usage reduction - Icelake gamma fix - GuC reset fixes - make mmap more asynchronous - sound display power well race fixes - DDI/MIPI-DSI clocks for Icelake - Icelake RPS frequency changing support - Icelake workarounds amdgpu: - Use HMM for userptr - vega20 experimental smu11 support - RAS support for vega20 - BACO support for vega12 + fixes for vega20 - reworked IH interrupt handling - amdkfd RAS support - Freesync improvements - initial timeline sync object support - DC Z ordering fixes - NV12 planes support - colorspace properties for planes= - eDP opts if eDP already initialized nouveau: - misc fixes etnaviv: - misc fixes msm: - GPU zap shader support expansion - robustness ABI addition exynos: - Logging cleanups tegra: - Shared reset fix - CPU cache maintenance fix cirrus: - driver rewritten using simple helpers meson: - G12A support vmwgfx: - Resource dirtying management improvements - Userspace logging improvements virtio: - PRIME fixes rockchip: - rk3066 hdmi support sun4i: - DSI burst mode support vc4: - load tracker to detect underflow v3d: - v3d v4.2 support malidp: - initial Mali D71 support in komeda driver tfp410: - omap related improvement omapdrm: - drm bridge/panel support - drop some omap specific panels rcar-du: - Display writeback support" * tag 'drm-next-2019-05-09' of git://anongit.freedesktop.org/drm/drm: (1507 commits) drm/msm/a6xx: No zap shader is not an error drm/cma-helper: Fix drm_gem_cma_free_object() drm: Fix timestamp docs for variable refresh properties. drm/komeda: Mark the local functions as static drm/komeda: Fixed warning: Function parameter or member not described drm/komeda: Expose bus_width to Komeda-CORE drm/komeda: Add sysfs attribute: core_id and config_id drm: add non-desktop quirk for Valve HMDs drm/panfrost: Show stored feature registers drm/panfrost: Don't scream about deferred probe drm/panfrost: Disable PM on probe failure drm/panfrost: Set DMA masks earlier drm/panfrost: Add sanity checks to submit IOCTL drm/etnaviv: initialize idle mask before querying the HW db drm: introduce a capability flag for syncobj timeline support drm: report consistent errors when checking syncobj capibility drm/nouveau/nouveau: forward error generated while resuming objects tree drm/nouveau/fb/ramgk104: fix spelling mistake "sucessfully" -> "successfully" drm/nouveau/i2c: Disable i2c bus access after ->fini() drm/nouveau: Remove duplicate ACPI_VIDEO_NOTIFY_PROBE definition ...
This commit is contained in:
Linus Torvalds
@@ -210,6 +210,9 @@ union drm_amdgpu_bo_list {
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#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
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/* indicate some job from this context once cause gpu hang */
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#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
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/* indicate some errors are detected by RAS */
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#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
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#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
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/* Context priority level */
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#define AMDGPU_CTX_PRIORITY_UNSET -2048
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@@ -525,6 +528,8 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
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#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
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#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
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#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
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#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
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struct drm_amdgpu_cs_chunk {
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__u32 chunk_id;
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@@ -605,6 +610,12 @@ struct drm_amdgpu_cs_chunk_sem {
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__u32 handle;
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};
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struct drm_amdgpu_cs_chunk_syncobj {
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__u32 handle;
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__u32 flags;
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__u64 point;
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};
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#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
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#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
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#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
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@@ -680,6 +691,7 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
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/* Subquery id: Query DMCU firmware version */
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#define AMDGPU_INFO_FW_DMCU 0x12
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#define AMDGPU_INFO_FW_TA 0x13
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/* number of bytes moved for TTM migration */
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#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
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/* the used VRAM size */
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@@ -733,6 +745,37 @@ struct drm_amdgpu_cs_chunk_data {
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/* Number of VRAM page faults on CPU access. */
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#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
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#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
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/* query ras mask of enabled features*/
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#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
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/* RAS MASK: UMC (VRAM) */
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#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
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/* RAS MASK: SDMA */
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#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
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/* RAS MASK: GFX */
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#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
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/* RAS MASK: MMHUB */
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#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
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/* RAS MASK: ATHUB */
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#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
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/* RAS MASK: PCIE */
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#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
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/* RAS MASK: HDP */
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#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
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/* RAS MASK: XGMI */
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#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
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/* RAS MASK: DF */
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#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
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/* RAS MASK: SMN */
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#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
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/* RAS MASK: SEM */
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#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
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/* RAS MASK: MP0 */
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#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
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/* RAS MASK: MP1 */
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#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
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/* RAS MASK: FUSE */
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#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@@ -649,6 +649,7 @@ struct drm_gem_open {
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#define DRM_CAP_PAGE_FLIP_TARGET 0x11
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#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
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#define DRM_CAP_SYNCOBJ 0x13
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#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
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/** DRM_IOCTL_GET_CAP ioctl argument type */
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struct drm_get_cap {
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@@ -735,8 +736,18 @@ struct drm_syncobj_handle {
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__u32 pad;
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};
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struct drm_syncobj_transfer {
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__u32 src_handle;
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__u32 dst_handle;
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__u64 src_point;
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__u64 dst_point;
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__u32 flags;
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__u32 pad;
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};
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
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#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
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struct drm_syncobj_wait {
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__u64 handles;
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/* absolute timeout */
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@@ -747,12 +758,33 @@ struct drm_syncobj_wait {
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__u32 pad;
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};
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struct drm_syncobj_timeline_wait {
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__u64 handles;
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/* wait on specific timeline point for every handles*/
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__u64 points;
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/* absolute timeout */
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__s64 timeout_nsec;
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__u32 count_handles;
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__u32 flags;
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__u32 first_signaled; /* only valid when not waiting all */
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__u32 pad;
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};
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struct drm_syncobj_array {
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__u64 handles;
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__u32 count_handles;
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__u32 pad;
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};
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struct drm_syncobj_timeline_array {
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__u64 handles;
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__u64 points;
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__u32 count_handles;
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__u32 pad;
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};
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/* Query current scanout sequence number */
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struct drm_crtc_get_sequence {
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__u32 crtc_id; /* requested crtc_id */
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@@ -909,6 +941,11 @@ extern "C" {
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#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
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#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
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#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
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#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
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#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
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#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
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/**
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* Device specific ioctls should only be in their respective headers
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* The device specific ioctl range is from 0x40 to 0x9f.
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@@ -144,6 +144,17 @@ extern "C" {
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#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
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#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
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/*
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* Floating point 64bpp RGB
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* IEEE 754-2008 binary16 half-precision float
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* [15:0] sign:exponent:mantissa 1:5:10
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*/
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#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
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#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
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#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
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#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
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/* packed YCbCr */
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#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
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#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
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@@ -151,7 +162,29 @@ extern "C" {
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#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
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#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
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#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
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#define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
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#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
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#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
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/*
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* packed Y2xx indicate for each component, xx valid data occupy msb
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* 16-xx padding occupy lsb
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*/
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#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
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#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
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#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
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/*
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* packed Y4xx indicate for each component, xx valid data occupy msb
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* 16-xx padding occupy lsb except Y410
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*/
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#define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
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#define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
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#define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
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#define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
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#define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
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#define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
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/*
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* packed YCbCr420 2x2 tiled formats
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@@ -167,6 +200,15 @@ extern "C" {
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/* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
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#define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
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/*
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* 1-plane YUV 4:2:0
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* In these formats, the component ordering is specified (Y, followed by U
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* then V), but the exact Linear layout is undefined.
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* These formats can only be used with a non-Linear modifier.
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*/
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#define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
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#define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
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/*
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* 2 plane RGB + A
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* index 0 = RGB plane, same format as the corresponding non _A8 format has
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@@ -195,6 +237,13 @@ extern "C" {
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#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
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#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y:x [10:6] little endian
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* index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
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*/
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#define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
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/*
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* 2 plane YCbCr MSB aligned
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* index 0 = Y plane, [15:0] Y:x [10:6] little endian
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@@ -33,7 +33,6 @@
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extern "C" {
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#endif
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#define DRM_DISPLAY_INFO_LEN 32
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#define DRM_CONNECTOR_NAME_LEN 32
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#define DRM_DISPLAY_MODE_LEN 32
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#define DRM_PROP_NAME_LEN 32
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@@ -622,7 +621,8 @@ struct drm_color_ctm {
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struct drm_color_lut {
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/*
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* Data is U0.16 fixed point format.
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* Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and
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* 0xffff == 1.0.
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*/
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__u16 red;
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__u16 green;
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@@ -62,6 +62,28 @@ extern "C" {
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#define I915_ERROR_UEVENT "ERROR"
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#define I915_RESET_UEVENT "RESET"
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/*
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* i915_user_extension: Base class for defining a chain of extensions
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*
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* Many interfaces need to grow over time. In most cases we can simply
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* extend the struct and have userspace pass in more data. Another option,
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* as demonstrated by Vulkan's approach to providing extensions for forward
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* and backward compatibility, is to use a list of optional structs to
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* provide those extra details.
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*
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* The key advantage to using an extension chain is that it allows us to
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* redefine the interface more easily than an ever growing struct of
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* increasing complexity, and for large parts of that interface to be
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* entirely optional. The downside is more pointer chasing; chasing across
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* the __user boundary with pointers encapsulated inside u64.
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*/
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struct i915_user_extension {
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__u64 next_extension;
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__u32 name;
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__u32 flags; /* All undefined bits must be zero. */
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__u32 rsvd[4]; /* Reserved for future use; must be zero. */
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};
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/*
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* MOCS indexes used for GPU surfaces, defining the cacheability of the
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* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
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@@ -99,9 +121,23 @@ enum drm_i915_gem_engine_class {
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I915_ENGINE_CLASS_VIDEO = 2,
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I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
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/* should be kept compact */
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I915_ENGINE_CLASS_INVALID = -1
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};
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/*
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* There may be more than one engine fulfilling any role within the system.
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* Each engine of a class is given a unique instance number and therefore
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* any engine can be specified by its class:instance tuplet. APIs that allow
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* access to any engine in the system will use struct i915_engine_class_instance
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* for this identification.
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*/
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struct i915_engine_class_instance {
|
||||
__u16 engine_class; /* see enum drm_i915_gem_engine_class */
|
||||
__u16 engine_instance;
|
||||
};
|
||||
|
||||
/**
|
||||
* DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
|
||||
*
|
||||
@@ -319,6 +355,7 @@ typedef struct _drm_i915_sarea {
|
||||
#define DRM_I915_PERF_ADD_CONFIG 0x37
|
||||
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
|
||||
#define DRM_I915_QUERY 0x39
|
||||
/* Must be kept compact -- no holes */
|
||||
|
||||
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
|
||||
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
|
||||
@@ -367,6 +404,7 @@ typedef struct _drm_i915_sarea {
|
||||
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
|
||||
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
|
||||
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
|
||||
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
|
||||
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
|
||||
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
|
||||
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
|
||||
@@ -476,6 +514,7 @@ typedef struct drm_i915_irq_wait {
|
||||
#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
|
||||
#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
|
||||
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
|
||||
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
|
||||
|
||||
#define I915_PARAM_HUC_STATUS 42
|
||||
|
||||
@@ -559,6 +598,8 @@ typedef struct drm_i915_irq_wait {
|
||||
*/
|
||||
#define I915_PARAM_MMAP_GTT_COHERENT 52
|
||||
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
__s32 param;
|
||||
/*
|
||||
@@ -574,6 +615,7 @@ typedef struct drm_i915_getparam {
|
||||
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
|
||||
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
|
||||
#define I915_SETPARAM_NUM_USED_FENCES 4
|
||||
/* Must be kept compact -- no holes */
|
||||
|
||||
typedef struct drm_i915_setparam {
|
||||
int param;
|
||||
@@ -972,7 +1014,7 @@ struct drm_i915_gem_execbuffer2 {
|
||||
* struct drm_i915_gem_exec_fence *fences.
|
||||
*/
|
||||
__u64 cliprects_ptr;
|
||||
#define I915_EXEC_RING_MASK (7<<0)
|
||||
#define I915_EXEC_RING_MASK (0x3f)
|
||||
#define I915_EXEC_DEFAULT (0<<0)
|
||||
#define I915_EXEC_RENDER (1<<0)
|
||||
#define I915_EXEC_BSD (2<<0)
|
||||
@@ -1120,32 +1162,34 @@ struct drm_i915_gem_busy {
|
||||
* as busy may become idle before the ioctl is completed.
|
||||
*
|
||||
* Furthermore, if the object is busy, which engine is busy is only
|
||||
* provided as a guide. There are race conditions which prevent the
|
||||
* report of which engines are busy from being always accurate.
|
||||
* However, the converse is not true. If the object is idle, the
|
||||
* result of the ioctl, that all engines are idle, is accurate.
|
||||
* provided as a guide and only indirectly by reporting its class
|
||||
* (there may be more than one engine in each class). There are race
|
||||
* conditions which prevent the report of which engines are busy from
|
||||
* being always accurate. However, the converse is not true. If the
|
||||
* object is idle, the result of the ioctl, that all engines are idle,
|
||||
* is accurate.
|
||||
*
|
||||
* The returned dword is split into two fields to indicate both
|
||||
* the engines on which the object is being read, and the
|
||||
* engine on which it is currently being written (if any).
|
||||
* the engine classess on which the object is being read, and the
|
||||
* engine class on which it is currently being written (if any).
|
||||
*
|
||||
* The low word (bits 0:15) indicate if the object is being written
|
||||
* to by any engine (there can only be one, as the GEM implicit
|
||||
* synchronisation rules force writes to be serialised). Only the
|
||||
* engine for the last write is reported.
|
||||
* engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
|
||||
* 1 not 0 etc) for the last write is reported.
|
||||
*
|
||||
* The high word (bits 16:31) are a bitmask of which engines are
|
||||
* currently reading from the object. Multiple engines may be
|
||||
* The high word (bits 16:31) are a bitmask of which engines classes
|
||||
* are currently reading from the object. Multiple engines may be
|
||||
* reading from the object simultaneously.
|
||||
*
|
||||
* The value of each engine is the same as specified in the
|
||||
* EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
|
||||
* Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
|
||||
* the I915_EXEC_RENDER engine for execution, and so it is never
|
||||
* The value of each engine class is the same as specified in the
|
||||
* I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
|
||||
* I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
|
||||
* reported as active itself. Some hardware may have parallel
|
||||
* execution engines, e.g. multiple media engines, which are
|
||||
* mapped to the same identifier in the EXECBUFFER2 ioctl and
|
||||
* so are not separately reported for busyness.
|
||||
* mapped to the same class identifier and so are not separately
|
||||
* reported for busyness.
|
||||
*
|
||||
* Caveat emptor:
|
||||
* Only the boolean result of this query is reliable; that is whether
|
||||
@@ -1412,16 +1456,158 @@ struct drm_i915_gem_wait {
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_create {
|
||||
/* output: id of new context*/
|
||||
__u32 ctx_id;
|
||||
__u32 ctx_id; /* output: id of new context*/
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_create_ext {
|
||||
__u32 ctx_id; /* output: id of new context*/
|
||||
__u32 flags;
|
||||
#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
|
||||
#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
|
||||
(-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))
|
||||
__u64 extensions;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_param {
|
||||
__u32 ctx_id;
|
||||
__u32 size;
|
||||
__u64 param;
|
||||
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
|
||||
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
|
||||
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
|
||||
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
|
||||
#define I915_CONTEXT_PARAM_BANNABLE 0x5
|
||||
#define I915_CONTEXT_PARAM_PRIORITY 0x6
|
||||
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
|
||||
#define I915_CONTEXT_DEFAULT_PRIORITY 0
|
||||
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
|
||||
/*
|
||||
* When using the following param, value should be a pointer to
|
||||
* drm_i915_gem_context_param_sseu.
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_SSEU 0x7
|
||||
|
||||
/*
|
||||
* Not all clients may want to attempt automatic recover of a context after
|
||||
* a hang (for example, some clients may only submit very small incremental
|
||||
* batches relying on known logical state of previous batches which will never
|
||||
* recover correctly and each attempt will hang), and so would prefer that
|
||||
* the context is forever banned instead.
|
||||
*
|
||||
* If set to false (0), after a reset, subsequent (and in flight) rendering
|
||||
* from this context is discarded, and the client will need to create a new
|
||||
* context to use instead.
|
||||
*
|
||||
* If set to true (1), the kernel will automatically attempt to recover the
|
||||
* context by skipping the hanging batch and executing the next batch starting
|
||||
* from the default context state (discarding the incomplete logical context
|
||||
* state lost due to the reset).
|
||||
*
|
||||
* On creation, all new contexts are marked as recoverable.
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_RECOVERABLE 0x8
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* Context SSEU programming
|
||||
*
|
||||
* It may be necessary for either functional or performance reason to configure
|
||||
* a context to run with a reduced number of SSEU (where SSEU stands for Slice/
|
||||
* Sub-slice/EU).
|
||||
*
|
||||
* This is done by configuring SSEU configuration using the below
|
||||
* @struct drm_i915_gem_context_param_sseu for every supported engine which
|
||||
* userspace intends to use.
|
||||
*
|
||||
* Not all GPUs or engines support this functionality in which case an error
|
||||
* code -ENODEV will be returned.
|
||||
*
|
||||
* Also, flexibility of possible SSEU configuration permutations varies between
|
||||
* GPU generations and software imposed limitations. Requesting such a
|
||||
* combination will return an error code of -EINVAL.
|
||||
*
|
||||
* NOTE: When perf/OA is active the context's SSEU configuration is ignored in
|
||||
* favour of a single global setting.
|
||||
*/
|
||||
struct drm_i915_gem_context_param_sseu {
|
||||
/*
|
||||
* Engine class & instance to be configured or queried.
|
||||
*/
|
||||
struct i915_engine_class_instance engine;
|
||||
|
||||
/*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/*
|
||||
* Mask of slices to enable for the context. Valid values are a subset
|
||||
* of the bitmask value returned for I915_PARAM_SLICE_MASK.
|
||||
*/
|
||||
__u64 slice_mask;
|
||||
|
||||
/*
|
||||
* Mask of subslices to enable for the context. Valid values are a
|
||||
* subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
|
||||
*/
|
||||
__u64 subslice_mask;
|
||||
|
||||
/*
|
||||
* Minimum/Maximum number of EUs to enable per subslice for the
|
||||
* context. min_eus_per_subslice must be inferior or equal to
|
||||
* max_eus_per_subslice.
|
||||
*/
|
||||
__u16 min_eus_per_subslice;
|
||||
__u16 max_eus_per_subslice;
|
||||
|
||||
/*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u32 rsvd;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_create_ext_setparam {
|
||||
#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
|
||||
struct i915_user_extension base;
|
||||
struct drm_i915_gem_context_param param;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_destroy {
|
||||
__u32 ctx_id;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/*
|
||||
* DRM_I915_GEM_VM_CREATE -
|
||||
*
|
||||
* Create a new virtual memory address space (ppGTT) for use within a context
|
||||
* on the same file. Extensions can be provided to configure exactly how the
|
||||
* address space is setup upon creation.
|
||||
*
|
||||
* The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
|
||||
* returned in the outparam @id.
|
||||
*
|
||||
* No flags are defined, with all bits reserved and must be zero.
|
||||
*
|
||||
* An extension chain maybe provided, starting with @extensions, and terminated
|
||||
* by the @next_extension being 0. Currently, no extensions are defined.
|
||||
*
|
||||
* DRM_I915_GEM_VM_DESTROY -
|
||||
*
|
||||
* Destroys a previously created VM id, specified in @id.
|
||||
*
|
||||
* No extensions or flags are allowed currently, and so must be zero.
|
||||
*/
|
||||
struct drm_i915_gem_vm_control {
|
||||
__u64 extensions;
|
||||
__u32 flags;
|
||||
__u32 vm_id;
|
||||
};
|
||||
|
||||
struct drm_i915_reg_read {
|
||||
/*
|
||||
* Register offset.
|
||||
@@ -1434,6 +1620,7 @@ struct drm_i915_reg_read {
|
||||
|
||||
__u64 val; /* Return value */
|
||||
};
|
||||
|
||||
/* Known registers:
|
||||
*
|
||||
* Render engine timestamp - 0x2358 + 64bit - gen7+
|
||||
@@ -1473,86 +1660,6 @@ struct drm_i915_gem_userptr {
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_param {
|
||||
__u32 ctx_id;
|
||||
__u32 size;
|
||||
__u64 param;
|
||||
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
|
||||
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
|
||||
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
|
||||
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
|
||||
#define I915_CONTEXT_PARAM_BANNABLE 0x5
|
||||
#define I915_CONTEXT_PARAM_PRIORITY 0x6
|
||||
#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
|
||||
#define I915_CONTEXT_DEFAULT_PRIORITY 0
|
||||
#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
|
||||
/*
|
||||
* When using the following param, value should be a pointer to
|
||||
* drm_i915_gem_context_param_sseu.
|
||||
*/
|
||||
#define I915_CONTEXT_PARAM_SSEU 0x7
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* Context SSEU programming
|
||||
*
|
||||
* It may be necessary for either functional or performance reason to configure
|
||||
* a context to run with a reduced number of SSEU (where SSEU stands for Slice/
|
||||
* Sub-slice/EU).
|
||||
*
|
||||
* This is done by configuring SSEU configuration using the below
|
||||
* @struct drm_i915_gem_context_param_sseu for every supported engine which
|
||||
* userspace intends to use.
|
||||
*
|
||||
* Not all GPUs or engines support this functionality in which case an error
|
||||
* code -ENODEV will be returned.
|
||||
*
|
||||
* Also, flexibility of possible SSEU configuration permutations varies between
|
||||
* GPU generations and software imposed limitations. Requesting such a
|
||||
* combination will return an error code of -EINVAL.
|
||||
*
|
||||
* NOTE: When perf/OA is active the context's SSEU configuration is ignored in
|
||||
* favour of a single global setting.
|
||||
*/
|
||||
struct drm_i915_gem_context_param_sseu {
|
||||
/*
|
||||
* Engine class & instance to be configured or queried.
|
||||
*/
|
||||
__u16 engine_class;
|
||||
__u16 engine_instance;
|
||||
|
||||
/*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/*
|
||||
* Mask of slices to enable for the context. Valid values are a subset
|
||||
* of the bitmask value returned for I915_PARAM_SLICE_MASK.
|
||||
*/
|
||||
__u64 slice_mask;
|
||||
|
||||
/*
|
||||
* Mask of subslices to enable for the context. Valid values are a
|
||||
* subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
|
||||
*/
|
||||
__u64 subslice_mask;
|
||||
|
||||
/*
|
||||
* Minimum/Maximum number of EUs to enable per subslice for the
|
||||
* context. min_eus_per_subslice must be inferior or equal to
|
||||
* max_eus_per_subslice.
|
||||
*/
|
||||
__u16 min_eus_per_subslice;
|
||||
__u16 max_eus_per_subslice;
|
||||
|
||||
/*
|
||||
* Unused for now. Must be cleared to zero.
|
||||
*/
|
||||
__u32 rsvd;
|
||||
};
|
||||
|
||||
enum drm_i915_oa_format {
|
||||
I915_OA_FORMAT_A13 = 1, /* HSW only */
|
||||
I915_OA_FORMAT_A29, /* HSW only */
|
||||
@@ -1714,6 +1821,7 @@ struct drm_i915_perf_oa_config {
|
||||
struct drm_i915_query_item {
|
||||
__u64 query_id;
|
||||
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
|
||||
/* Must be kept compact -- no holes and well documented */
|
||||
|
||||
/*
|
||||
* When set to zero by userspace, this is filled with the size of the
|
||||
|
||||
169
include/uapi/drm/lima_drm.h
Normal file
169
include/uapi/drm/lima_drm.h
Normal file
@@ -0,0 +1,169 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
|
||||
/* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
|
||||
|
||||
#ifndef __LIMA_DRM_H__
|
||||
#define __LIMA_DRM_H__
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
enum drm_lima_param_gpu_id {
|
||||
DRM_LIMA_PARAM_GPU_ID_UNKNOWN,
|
||||
DRM_LIMA_PARAM_GPU_ID_MALI400,
|
||||
DRM_LIMA_PARAM_GPU_ID_MALI450,
|
||||
};
|
||||
|
||||
enum drm_lima_param {
|
||||
DRM_LIMA_PARAM_GPU_ID,
|
||||
DRM_LIMA_PARAM_NUM_PP,
|
||||
DRM_LIMA_PARAM_GP_VERSION,
|
||||
DRM_LIMA_PARAM_PP_VERSION,
|
||||
};
|
||||
|
||||
/**
|
||||
* get various information of the GPU
|
||||
*/
|
||||
struct drm_lima_get_param {
|
||||
__u32 param; /* in, value in enum drm_lima_param */
|
||||
__u32 pad; /* pad, must be zero */
|
||||
__u64 value; /* out, parameter value */
|
||||
};
|
||||
|
||||
/**
|
||||
* create a buffer for used by GPU
|
||||
*/
|
||||
struct drm_lima_gem_create {
|
||||
__u32 size; /* in, buffer size */
|
||||
__u32 flags; /* in, currently no flags, must be zero */
|
||||
__u32 handle; /* out, GEM buffer handle */
|
||||
__u32 pad; /* pad, must be zero */
|
||||
};
|
||||
|
||||
/**
|
||||
* get information of a buffer
|
||||
*/
|
||||
struct drm_lima_gem_info {
|
||||
__u32 handle; /* in, GEM buffer handle */
|
||||
__u32 va; /* out, virtual address mapped into GPU MMU */
|
||||
__u64 offset; /* out, used to mmap this buffer to CPU */
|
||||
};
|
||||
|
||||
#define LIMA_SUBMIT_BO_READ 0x01
|
||||
#define LIMA_SUBMIT_BO_WRITE 0x02
|
||||
|
||||
/* buffer information used by one task */
|
||||
struct drm_lima_gem_submit_bo {
|
||||
__u32 handle; /* in, GEM buffer handle */
|
||||
__u32 flags; /* in, buffer read/write by GPU */
|
||||
};
|
||||
|
||||
#define LIMA_GP_FRAME_REG_NUM 6
|
||||
|
||||
/* frame used to setup GP for each task */
|
||||
struct drm_lima_gp_frame {
|
||||
__u32 frame[LIMA_GP_FRAME_REG_NUM];
|
||||
};
|
||||
|
||||
#define LIMA_PP_FRAME_REG_NUM 23
|
||||
#define LIMA_PP_WB_REG_NUM 12
|
||||
|
||||
/* frame used to setup mali400 GPU PP for each task */
|
||||
struct drm_lima_m400_pp_frame {
|
||||
__u32 frame[LIMA_PP_FRAME_REG_NUM];
|
||||
__u32 num_pp;
|
||||
__u32 wb[3 * LIMA_PP_WB_REG_NUM];
|
||||
__u32 plbu_array_address[4];
|
||||
__u32 fragment_stack_address[4];
|
||||
};
|
||||
|
||||
/* frame used to setup mali450 GPU PP for each task */
|
||||
struct drm_lima_m450_pp_frame {
|
||||
__u32 frame[LIMA_PP_FRAME_REG_NUM];
|
||||
__u32 num_pp;
|
||||
__u32 wb[3 * LIMA_PP_WB_REG_NUM];
|
||||
__u32 use_dlbu;
|
||||
__u32 _pad;
|
||||
union {
|
||||
__u32 plbu_array_address[8];
|
||||
__u32 dlbu_regs[4];
|
||||
};
|
||||
__u32 fragment_stack_address[8];
|
||||
};
|
||||
|
||||
#define LIMA_PIPE_GP 0x00
|
||||
#define LIMA_PIPE_PP 0x01
|
||||
|
||||
#define LIMA_SUBMIT_FLAG_EXPLICIT_FENCE (1 << 0)
|
||||
|
||||
/**
|
||||
* submit a task to GPU
|
||||
*
|
||||
* User can always merge multi sync_file and drm_syncobj
|
||||
* into one drm_syncobj as in_sync[0], but we reserve
|
||||
* in_sync[1] for another task's out_sync to avoid the
|
||||
* export/import/merge pass when explicit sync.
|
||||
*/
|
||||
struct drm_lima_gem_submit {
|
||||
__u32 ctx; /* in, context handle task is submitted to */
|
||||
__u32 pipe; /* in, which pipe to use, GP/PP */
|
||||
__u32 nr_bos; /* in, array length of bos field */
|
||||
__u32 frame_size; /* in, size of frame field */
|
||||
__u64 bos; /* in, array of drm_lima_gem_submit_bo */
|
||||
__u64 frame; /* in, GP/PP frame */
|
||||
__u32 flags; /* in, submit flags */
|
||||
__u32 out_sync; /* in, drm_syncobj handle used to wait task finish after submission */
|
||||
__u32 in_sync[2]; /* in, drm_syncobj handle used to wait before start this task */
|
||||
};
|
||||
|
||||
#define LIMA_GEM_WAIT_READ 0x01
|
||||
#define LIMA_GEM_WAIT_WRITE 0x02
|
||||
|
||||
/**
|
||||
* wait pending GPU task finish of a buffer
|
||||
*/
|
||||
struct drm_lima_gem_wait {
|
||||
__u32 handle; /* in, GEM buffer handle */
|
||||
__u32 op; /* in, CPU want to read/write this buffer */
|
||||
__s64 timeout_ns; /* in, wait timeout in absulute time */
|
||||
};
|
||||
|
||||
/**
|
||||
* create a context
|
||||
*/
|
||||
struct drm_lima_ctx_create {
|
||||
__u32 id; /* out, context handle */
|
||||
__u32 _pad; /* pad, must be zero */
|
||||
};
|
||||
|
||||
/**
|
||||
* free a context
|
||||
*/
|
||||
struct drm_lima_ctx_free {
|
||||
__u32 id; /* in, context handle */
|
||||
__u32 _pad; /* pad, must be zero */
|
||||
};
|
||||
|
||||
#define DRM_LIMA_GET_PARAM 0x00
|
||||
#define DRM_LIMA_GEM_CREATE 0x01
|
||||
#define DRM_LIMA_GEM_INFO 0x02
|
||||
#define DRM_LIMA_GEM_SUBMIT 0x03
|
||||
#define DRM_LIMA_GEM_WAIT 0x04
|
||||
#define DRM_LIMA_CTX_CREATE 0x05
|
||||
#define DRM_LIMA_CTX_FREE 0x06
|
||||
|
||||
#define DRM_IOCTL_LIMA_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GET_PARAM, struct drm_lima_get_param)
|
||||
#define DRM_IOCTL_LIMA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_CREATE, struct drm_lima_gem_create)
|
||||
#define DRM_IOCTL_LIMA_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_LIMA_GEM_INFO, struct drm_lima_gem_info)
|
||||
#define DRM_IOCTL_LIMA_GEM_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_SUBMIT, struct drm_lima_gem_submit)
|
||||
#define DRM_IOCTL_LIMA_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_GEM_WAIT, struct drm_lima_gem_wait)
|
||||
#define DRM_IOCTL_LIMA_CTX_CREATE DRM_IOR(DRM_COMMAND_BASE + DRM_LIMA_CTX_CREATE, struct drm_lima_ctx_create)
|
||||
#define DRM_IOCTL_LIMA_CTX_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_LIMA_CTX_FREE, struct drm_lima_ctx_free)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __LIMA_DRM_H__ */
|
||||
@@ -74,6 +74,8 @@ struct drm_msm_timespec {
|
||||
#define MSM_PARAM_TIMESTAMP 0x05
|
||||
#define MSM_PARAM_GMEM_BASE 0x06
|
||||
#define MSM_PARAM_NR_RINGS 0x07
|
||||
#define MSM_PARAM_PP_PGTABLE 0x08 /* => 1 for per-process pagetables, else 0 */
|
||||
#define MSM_PARAM_FAULTS 0x09
|
||||
|
||||
struct drm_msm_param {
|
||||
__u32 pipe; /* in, MSM_PIPE_x */
|
||||
@@ -286,6 +288,16 @@ struct drm_msm_submitqueue {
|
||||
__u32 id; /* out, identifier */
|
||||
};
|
||||
|
||||
#define MSM_SUBMITQUEUE_PARAM_FAULTS 0
|
||||
|
||||
struct drm_msm_submitqueue_query {
|
||||
__u64 data;
|
||||
__u32 id;
|
||||
__u32 param;
|
||||
__u32 len;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
#define DRM_MSM_GET_PARAM 0x00
|
||||
/* placeholder:
|
||||
#define DRM_MSM_SET_PARAM 0x01
|
||||
@@ -302,6 +314,7 @@ struct drm_msm_submitqueue {
|
||||
*/
|
||||
#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
|
||||
#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
|
||||
#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
|
||||
|
||||
#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
|
||||
#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
|
||||
@@ -313,6 +326,7 @@ struct drm_msm_submitqueue {
|
||||
#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
|
||||
#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
|
||||
#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
|
||||
#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
||||
142
include/uapi/drm/panfrost_drm.h
Normal file
142
include/uapi/drm/panfrost_drm.h
Normal file
@@ -0,0 +1,142 @@
|
||||
/* SPDX-License-Identifier: MIT */
|
||||
/*
|
||||
* Copyright © 2014-2018 Broadcom
|
||||
* Copyright © 2019 Collabora ltd.
|
||||
*/
|
||||
#ifndef _PANFROST_DRM_H_
|
||||
#define _PANFROST_DRM_H_
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DRM_PANFROST_SUBMIT 0x00
|
||||
#define DRM_PANFROST_WAIT_BO 0x01
|
||||
#define DRM_PANFROST_CREATE_BO 0x02
|
||||
#define DRM_PANFROST_MMAP_BO 0x03
|
||||
#define DRM_PANFROST_GET_PARAM 0x04
|
||||
#define DRM_PANFROST_GET_BO_OFFSET 0x05
|
||||
|
||||
#define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit)
|
||||
#define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo)
|
||||
#define DRM_IOCTL_PANFROST_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, struct drm_panfrost_create_bo)
|
||||
#define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, struct drm_panfrost_mmap_bo)
|
||||
#define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param)
|
||||
#define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset)
|
||||
|
||||
#define PANFROST_JD_REQ_FS (1 << 0)
|
||||
/**
|
||||
* struct drm_panfrost_submit - ioctl argument for submitting commands to the 3D
|
||||
* engine.
|
||||
*
|
||||
* This asks the kernel to have the GPU execute a render command list.
|
||||
*/
|
||||
struct drm_panfrost_submit {
|
||||
|
||||
/** Address to GPU mapping of job descriptor */
|
||||
__u64 jc;
|
||||
|
||||
/** An optional array of sync objects to wait on before starting this job. */
|
||||
__u64 in_syncs;
|
||||
|
||||
/** Number of sync objects to wait on before starting this job. */
|
||||
__u32 in_sync_count;
|
||||
|
||||
/** An optional sync object to place the completion fence in. */
|
||||
__u32 out_sync;
|
||||
|
||||
/** Pointer to a u32 array of the BOs that are referenced by the job. */
|
||||
__u64 bo_handles;
|
||||
|
||||
/** Number of BO handles passed in (size is that times 4). */
|
||||
__u32 bo_handle_count;
|
||||
|
||||
/** A combination of PANFROST_JD_REQ_* */
|
||||
__u32 requirements;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_panfrost_wait_bo - ioctl argument for waiting for
|
||||
* completion of the last DRM_PANFROST_SUBMIT on a BO.
|
||||
*
|
||||
* This is useful for cases where multiple processes might be
|
||||
* rendering to a BO and you want to wait for all rendering to be
|
||||
* completed.
|
||||
*/
|
||||
struct drm_panfrost_wait_bo {
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
__s64 timeout_ns; /* absolute */
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs.
|
||||
*
|
||||
* There are currently no values for the flags argument, but it may be
|
||||
* used in a future extension.
|
||||
*/
|
||||
struct drm_panfrost_create_bo {
|
||||
__u32 size;
|
||||
__u32 flags;
|
||||
/** Returned GEM handle for the BO. */
|
||||
__u32 handle;
|
||||
/* Pad, must be zero-filled. */
|
||||
__u32 pad;
|
||||
/**
|
||||
* Returned offset for the BO in the GPU address space. This offset
|
||||
* is private to the DRM fd and is valid for the lifetime of the GEM
|
||||
* handle.
|
||||
*
|
||||
* This offset value will always be nonzero, since various HW
|
||||
* units treat 0 specially.
|
||||
*/
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_panfrost_mmap_bo - ioctl argument for mapping Panfrost BOs.
|
||||
*
|
||||
* This doesn't actually perform an mmap. Instead, it returns the
|
||||
* offset you need to use in an mmap on the DRM device node. This
|
||||
* means that tools like valgrind end up knowing about the mapped
|
||||
* memory.
|
||||
*
|
||||
* There are currently no values for the flags argument, but it may be
|
||||
* used in a future extension.
|
||||
*/
|
||||
struct drm_panfrost_mmap_bo {
|
||||
/** Handle for the object being mapped. */
|
||||
__u32 handle;
|
||||
__u32 flags;
|
||||
/** offset into the drm node to use for subsequent mmap call. */
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
enum drm_panfrost_param {
|
||||
DRM_PANFROST_PARAM_GPU_PROD_ID,
|
||||
};
|
||||
|
||||
struct drm_panfrost_get_param {
|
||||
__u32 param;
|
||||
__u32 pad;
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
/**
|
||||
* Returns the offset for the BO in the GPU address space for this DRM fd.
|
||||
* This is the same value returned by drm_panfrost_create_bo, if that was called
|
||||
* from this DRM fd.
|
||||
*/
|
||||
struct drm_panfrost_get_bo_offset {
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _PANFROST_DRM_H_ */
|
||||
@@ -211,6 +211,11 @@ struct kfd_ioctl_dbg_wave_control_args {
|
||||
#define KFD_HW_EXCEPTION_GPU_HANG 0
|
||||
#define KFD_HW_EXCEPTION_ECC 1
|
||||
|
||||
/* For kfd_hsa_memory_exception_data.ErrorType */
|
||||
#define KFD_MEM_ERR_NO_RAS 0
|
||||
#define KFD_MEM_ERR_SRAM_ECC 1
|
||||
#define KFD_MEM_ERR_POISON_CONSUMED 2
|
||||
#define KFD_MEM_ERR_GPU_HANG 3
|
||||
|
||||
struct kfd_ioctl_create_event_args {
|
||||
__u64 event_page_offset; /* from KFD */
|
||||
@@ -250,7 +255,12 @@ struct kfd_hsa_memory_exception_data {
|
||||
struct kfd_memory_exception_failure failure;
|
||||
__u64 va;
|
||||
__u32 gpu_id;
|
||||
__u32 pad;
|
||||
__u32 ErrorType; /* 0 = no RAS error,
|
||||
* 1 = ECC_SRAM,
|
||||
* 2 = Link_SYNFLOOD (poison),
|
||||
* 3 = GPU hang (not attributable to a specific cause),
|
||||
* other values reserved
|
||||
*/
|
||||
};
|
||||
|
||||
/* hw exception data */
|
||||
|
||||
@@ -40,8 +40,16 @@
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define VIRTIO_GPU_F_VIRGL 0
|
||||
#define VIRTIO_GPU_F_EDID 1
|
||||
/*
|
||||
* VIRTIO_GPU_CMD_CTX_*
|
||||
* VIRTIO_GPU_CMD_*_3D
|
||||
*/
|
||||
#define VIRTIO_GPU_F_VIRGL 0
|
||||
|
||||
/*
|
||||
* VIRTIO_GPU_CMD_GET_EDID
|
||||
*/
|
||||
#define VIRTIO_GPU_F_EDID 1
|
||||
|
||||
enum virtio_gpu_ctrl_type {
|
||||
VIRTIO_GPU_UNDEFINED = 0,
|
||||
|
||||
Reference in New Issue
Block a user