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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull ARM SoC DT updates from Olof Johansson:
 "DT changes continue to be the bulk of our merge window contents.

  We continue to have a large set of changes across the board as new
  platforms and drivers are added.

  Some of the new platforms are:
   - Alphascale ASM9260
   - Marvell Armada 388
   - CSR Atlas7
   - TI Davinci DM816x
   - Hisilicon HiP01
   - ST STiH418

  There have also been some sweeping changes, including relicensing of
  DTS contents from GPL to GPLv2+/X11 so that the same files can be
  reused in other non-GPL projects more easily.  There's also been
  changes to the DT Makefile to make it a little less conflict-ridden
  and churny down the road"

* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits)
  ARM: dts: Add PPMU node for exynos4412-trats2
  ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato
  ARM: dts: Add PPMU dt node for exynos4 and exynos4210
  ARM: dts: Add PPMU dt node for exynos3250
  ARM: dts: add mipi dsi device node for exynos4415
  ARM: dts: add fimd device node for exynos4415
  ARM: dts: Add syscon phandle to the video-phy node for Exynos4
  ARM: dts: Add sound nodes for exynos4412-trats2
  ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2
  ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi
  ARM: dts: Add max77693 charger node for exynos4412-trats2
  ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2
  ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2
  ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2
  ARM: dts: am57xx-beagle-x15: Fix USB2 mode
  ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB
  ARM: dts: dra72-evm: Add extcon nodes for USB
  ARM: dts: dra7-evm: Add extcon nodes for USB
  ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards
  ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb
  ...
This commit is contained in:
Linus Torvalds
2015-02-17 09:36:52 -08:00
parent 878ba61aa9 880c0d140d
commit a233bb742a
249 changed files with 14922 additions and 2430 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/devicetree/bindings/arm/armada-38x.txt
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@@ -15,6 +15,13 @@ Required root node property:
compatible: must contain "marvell,armada385"
In addition, boards using the Marvell Armada 388 SoC shall have the
following property before the previous one:
Required root node property:
compatible: must contain "marvell,armada388"
Example:
compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada380";

6
Documentation/devicetree/bindings/arm/digicolor.txt Normal file
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@@ -0,0 +1,6 @@
Conexant Digicolor Platforms Device Tree Bindings
Each device tree must specify which Conexant Digicolor SoC it uses.
Must be the following compatible string:
cnxt,cx92755

2
Documentation/devicetree/bindings/arm/exynos/power_domain.txt
View File

@@ -23,7 +23,7 @@ Optional Properties:
devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
are supported currently.
Node of a device using power domains must have a samsung,power-domain property
Node of a device using power domains must have a power-domains property
defined with a phandle to respective power domain.
Example:

8
Documentation/devicetree/bindings/arm/fsl.txt
View File

@@ -124,3 +124,11 @@ Example:
compatible = "fsl,ls1021a-dcfg";
reg = <0x0 0x1ee0000 0x0 0x10000>;
};
Freescale LS2085A SoC Device Tree Bindings
------------------------------------------
LS2085A ARMv8 based Simulator model
Required root node properties:
- compatible = "fsl,ls2085a-simu", "fsl,ls2085a";

25
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
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@@ -9,6 +9,10 @@ HiP04 D01 Board
Required root node properties:
- compatible = "hisilicon,hip04-d01";
HiP01 ca9x2 Board
Required root node properties:
- compatible = "hisilicon,hip01-ca9x2";
Hisilicon system controller
@@ -36,6 +40,27 @@ Example:
reboot-offset = <0x4>;
};
-----------------------------------------------------------------------
Hisilicon HiP01 system controller
Required properties:
- compatible : "hisilicon,hip01-sysctrl"
- reg : Register address and size
The HiP01 system controller is mostly compatible with hisilicon
system controller,but it has some specific control registers for
HIP01 SoC family, such as slave core boot, and also some same
registers located at different offset.
Example:
/* for hip01-ca9x2 */
sysctrl: system-controller@10000000 {
compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
reg = <0x10000000 0x1000>;
reboot-offset = <0x4>;
};
-----------------------------------------------------------------------
Hisilicon CPU controller

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt
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@@ -7,6 +7,7 @@ Required properties:
- compatible: should be one of:
"mediatek,mt8135-sysirq"
"mediatek,mt8127-sysirq"
"mediatek,mt6592-sysirq"
"mediatek,mt6589-sysirq"
"mediatek,mt6582-sysirq"
"mediatek,mt6577-sysirq"

10
Documentation/devicetree/bindings/arm/rockchip.txt
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@@ -9,6 +9,16 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
- ChipSPARK Rayeager PX2 board:
Required root node properties:
- compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";
- Radxa Rock board:
Required root node properties:
- compatible = "radxa,rock", "rockchip,rk3188";
- Firefly Firefly-RK3288 board:
Required root node properties:
- compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
or
- compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288";

12
Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt Normal file
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@@ -0,0 +1,12 @@
SAMSUNG Exynos SoCs Chipid driver.
Required properties:
- compatible : Should at least contain "samsung,exynos4210-chipid".
- reg: offset and length of the register set
Example:
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};

6
Documentation/devicetree/bindings/arm/sirf.txt
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@@ -3,7 +3,9 @@ CSR SiRFprimaII and SiRFmarco device tree bindings.
Required root node properties:
- compatible:
- "sirf,atlas6-cb" : atlas6 "cb" evaluation board
- "sirf,atlas6" : atlas6 device based board
- "sirf,atlas7-cb" : atlas7 "cb" evaluation board
- "sirf,atlas7" : atlas7 device based board
- "sirf,prima2-cb" : prima2 "cb" evaluation board
- "sirf,marco-cb" : marco "cb" evaluation board
- "sirf,prima2" : prima2 device based board
- "sirf,marco" : marco device based board

4
Documentation/devicetree/bindings/bus/mvebu-mbus.txt
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@@ -6,8 +6,8 @@ Required properties:
- compatible: Should be set to one of the following:
marvell,armada370-mbus
marvell,armadaxp-mbus
marvell,armada370-mbus
marvell,armadaxp-mbus
marvell,armada375-mbus
marvell,armada380-mbus
marvell,kirkwood-mbus
marvell,dove-mbus
marvell,orion5x-88f5281-mbus

115
Documentation/devicetree/bindings/clock/alphascale,acc.txt Normal file
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@@ -0,0 +1,115 @@
Alphascale Clock Controller
The ACC (Alphascale Clock Controller) is responsible of choising proper
clock source, setting deviders and clock gates.
Required properties for the ACC node:
- compatible: must be "alphascale,asm9260-clock-controller"
- reg: must contain the ACC register base and size
- #clock-cells : shall be set to 1.
Simple one-cell clock specifier format is used, where the only cell is used
as an index of the clock inside the provider.
It is encouraged to use dt-binding for clock index definitions. SoC specific
dt-binding should be included to the device tree descriptor. For example
Alphascale ASM9260:
#include <dt-bindings/clock/alphascale,asm9260.h>
This binding contains two types of clock providers:
_AHB_ - AHB gate;
_SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
All clock specific details can be found in the SoC documentation.
CLKID_AHB_ROM 0
CLKID_AHB_RAM 1
CLKID_AHB_GPIO 2
CLKID_AHB_MAC 3
CLKID_AHB_EMI 4
CLKID_AHB_USB0 5
CLKID_AHB_USB1 6
CLKID_AHB_DMA0 7
CLKID_AHB_DMA1 8
CLKID_AHB_UART0 9
CLKID_AHB_UART1 10
CLKID_AHB_UART2 11
CLKID_AHB_UART3 12
CLKID_AHB_UART4 13
CLKID_AHB_UART5 14
CLKID_AHB_UART6 15
CLKID_AHB_UART7 16
CLKID_AHB_UART8 17
CLKID_AHB_UART9 18
CLKID_AHB_I2S0 19
CLKID_AHB_I2C0 20
CLKID_AHB_I2C1 21
CLKID_AHB_SSP0 22
CLKID_AHB_IOCONFIG 23
CLKID_AHB_WDT 24
CLKID_AHB_CAN0 25
CLKID_AHB_CAN1 26
CLKID_AHB_MPWM 27
CLKID_AHB_SPI0 28
CLKID_AHB_SPI1 29
CLKID_AHB_QEI 30
CLKID_AHB_QUADSPI0 31
CLKID_AHB_CAMIF 32
CLKID_AHB_LCDIF 33
CLKID_AHB_TIMER0 34
CLKID_AHB_TIMER1 35
CLKID_AHB_TIMER2 36
CLKID_AHB_TIMER3 37
CLKID_AHB_IRQ 38
CLKID_AHB_RTC 39
CLKID_AHB_NAND 40
CLKID_AHB_ADC0 41
CLKID_AHB_LED 42
CLKID_AHB_DAC0 43
CLKID_AHB_LCD 44
CLKID_AHB_I2S1 45
CLKID_AHB_MAC1 46
CLKID_SYS_CPU 47
CLKID_SYS_AHB 48
CLKID_SYS_I2S0M 49
CLKID_SYS_I2S0S 50
CLKID_SYS_I2S1M 51
CLKID_SYS_I2S1S 52
CLKID_SYS_UART0 53
CLKID_SYS_UART1 54
CLKID_SYS_UART2 55
CLKID_SYS_UART3 56
CLKID_SYS_UART4 56
CLKID_SYS_UART5 57
CLKID_SYS_UART6 58
CLKID_SYS_UART7 59
CLKID_SYS_UART8 60
CLKID_SYS_UART9 61
CLKID_SYS_SPI0 62
CLKID_SYS_SPI1 63
CLKID_SYS_QUADSPI 64
CLKID_SYS_SSP0 65
CLKID_SYS_NAND 66
CLKID_SYS_TRACE 67
CLKID_SYS_CAMM 68
CLKID_SYS_WDT 69
CLKID_SYS_CLKOUT 70
CLKID_SYS_MAC 71
CLKID_SYS_LCD 72
CLKID_SYS_ADCANA 73
Example of clock consumer with _SYS_ and _AHB_ sinks.
uart4: serial@80010000 {
compatible = "alphascale,asm9260-uart";
reg = <0x80010000 0x4000>;
clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
interrupts = <19>;
status = "disabled";
};
Clock consumer with only one, _AHB_ sink.
timer0: timer@80088000 {
compatible = "alphascale,asm9260-timer";
reg = <0x80088000 0x4000>;
clocks = <&acc CLKID_AHB_TIMER0>;
interrupts = <29>;
};

6
Documentation/devicetree/bindings/iommu/samsung,sysmmu.txt
View File

@@ -45,7 +45,7 @@ Required properties:
Exynos4 SoCs, there needs no "master" clock.
Exynos5 SoCs, some System MMUs must have "master" clocks.
- clocks: Required if the System MMU is needed to gate its clock.
- samsung,power-domain: Required if the System MMU is needed to gate its power.
- power-domains: Required if the System MMU is needed to gate its power.
Please refer to the following document:
Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -54,7 +54,7 @@ Examples:
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>;
samsung,power-domain = <&pd_gsc>;
power-domains = <&pd_gsc>;
clocks = <&clock CLK_GSCL0>;
clock-names = "gscl";
};
@@ -66,5 +66,5 @@ Examples:
interrupts = <2 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
samsung,power-domain = <&pd_gsc>;
power-domains = <&pd_gsc>;
};

4
Documentation/devicetree/bindings/media/s5p-mfc.txt
View File

@@ -28,7 +28,7 @@ Required properties:
for DMA contiguous memory allocation and its size.
Optional properties:
- samsung,power-domain : power-domain property defined with a phandle
- power-domains : power-domain property defined with a phandle
to respective power domain.
Example:
@@ -38,7 +38,7 @@ mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
interrupts = <0 94 0>;
samsung,power-domain = <&pd_mfc>;
power-domains = <&pd_mfc>;
clocks = <&clock 273>;
clock-names = "mfc";
};

44
Documentation/devicetree/bindings/memory-controllers/renesas-memory-controllers.txt Normal file
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@@ -0,0 +1,44 @@
DT bindings for Renesas R-Mobile and SH-Mobile memory controllers
=================================================================
Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers.
These memory controllers differ from one SoC variant to another, and are called
by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
(DBSC3)", "SDRAM Bus State Controller (SBSC)").
Currently memory controller device nodes are used only to reference PM
domains, and prevent these PM domains from being powered down, which would
crash the system.
As there exist no actual drivers for these controllers yet, these bindings
should be considered EXPERIMENTAL for now.
Required properties:
- compatible: Must be one of the following SoC-specific values:
- "renesas,dbsc-r8a73a4" (R-Mobile APE6)
- "renesas,dbsc3-r8a7740" (R-Mobile A1)
- "renesas,sbsc-sh73a0" (SH-Mobile AG5)
- reg: Must contain the base address and length of the memory controller's
registers.
Optional properties:
- interrupts: Must contain a list of interrupt specifiers for memory
controller interrupts, if available.
- interrupts-names: Must contain a list of interrupt names corresponding to
the interrupts in the interrupts property, if available.
Valid interrupt names are:
- "sec" (secure interrupt)
- "temp" (normal (temperature) interrupt)
- power-domains: Must contain a reference to the PM domain that the memory
controller belongs to, if available.
Example:
sbsc1: memory-controller@fe400000 {
compatible = "renesas,sbsc-sh73a0";
reg = <0xfe400000 0x400>;
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
<0 36 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sec", "temp";
power-domains = <&pd_a4bc0>;
};

40
Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt Normal file
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@@ -0,0 +1,40 @@
* Freescale Management Complex
The Freescale Management Complex (fsl-mc) is a hardware resource
manager that manages specialized hardware objects used in
network-oriented packet processing applications. After the fsl-mc
block is enabled, pools of hardware resources are available, such as
queues, buffer pools, I/O interfaces. These resources are building
blocks that can be used to create functional hardware objects/devices
such as network interfaces, crypto accelerator instances, L2 switches,
etc.
Required properties:
- compatible
Value type: <string>
Definition: Must be "fsl,qoriq-mc". A Freescale Management Complex
compatible with this binding must have Block Revision
Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
the MC control register region.
- reg
Value type: <prop-encoded-array>
Definition: A standard property. Specifies one or two regions
defining the MC's registers:
-the first region is the command portal for the
this machine and must always be present
-the second region is the MC control registers. This
region may not be present in some scenarios, such
as in the device tree presented to a virtual machine.
Example:
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
};

99
Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt Normal file
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@@ -0,0 +1,99 @@
DT bindings for the Renesas R-Mobile System Controller
== System Controller Node ==
The R-Mobile System Controller provides the following functions:
- Boot mode management,
- Reset generation,
- Power management.
Required properties:
- compatible: Should be "renesas,sysc-<soctype>", "renesas,sysc-rmobile" as
fallback.
Examples with soctypes are:
- "renesas,sysc-r8a7740" (R-Mobile A1)
- "renesas,sysc-sh73a0" (SH-Mobile AG5)
- reg: Two address start and address range blocks for the device:
- The first block refers to the normally accessible registers,
- the second block refers to the registers protected by the HPB
semaphore.
Optional nodes:
- pm-domains: This node contains a hierarchy of PM domain nodes, which should
match the Power Area Hierarchy in the Power Domain Specifications section of
the device's datasheet.
== PM Domain Nodes ==
Each of the PM domain nodes represents a PM domain, as documented by the
generic PM domain bindings in
Documentation/devicetree/bindings/power/power_domain.txt.
The nodes should be named by the real power area names, and thus their names
should be unique.
Required properties:
- #power-domain-cells: Must be 0.
Optional properties:
- reg: If the PM domain is not always-on, this property must contain the bit
index number for the corresponding power area in the various Power
Control and Status Registers. The parent's node must contain the
following two properties:
- #address-cells: Must be 1,
- #size-cells: Must be 0.
If the PM domain is always-on, this property must be omitted.
Example:
This shows a subset of the r8a7740 PM domain hierarchy, containing the
C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP domain,
which is a subdomain of A4S.
sysc: system-controller@e6180000 {
compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
pm-domains {
pd_c5: c5 {
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a4s: a4s@10 {
reg = <10>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <0>;
pd_a3sp: a3sp@11 {
reg = <11>;
#power-domain-cells = <0>;
};
};
pd_a4su: a4su@20 {
reg = <20>;
#power-domain-cells = <0>;
};
};
};
};
== PM Domain Consumers ==
Hardware blocks belonging to a PM domain should contain a "power-domains"
property that is a phandle pointing to the corresponding PM domain node.
Example:
tpu: pwm@e6600000 {
compatible = "renesas,tpu-r8a7740", "renesas,tpu";
reg = <0xe6600000 0x100>;
clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
power-domains = <&pd_a3sp>;
#pwm-cells = <3>;
};

2
Documentation/devicetree/bindings/serial/mtk-uart.txt
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@@ -2,6 +2,8 @@
Required properties:
- compatible should contain:
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
* "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577)

12
Documentation/devicetree/bindings/serial/of-serial.txt
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@@ -19,6 +19,7 @@ Required properties:
- "altr,16550-FIFO64"
- "altr,16550-FIFO128"
- "fsl,16550-FIFO64"
- "fsl,ns16550"
- "serial" if the port type is unknown.
- reg : offset and length of the register set for the device.
- interrupts : should contain uart interrupt.
@@ -43,6 +44,17 @@ Optional properties:
driver is allowed to detect support for the capability even without this
property.
Note:
* fsl,ns16550:
------------
Freescale DUART is very similar to the PC16552D (and to a
pair of NS16550A), albeit with some nonstandard behavior such as
erratum A-004737 (relating to incorrect BRK handling).
Represents a single port that is compatible with the DUART found
on many Freescale chips (examples include mpc8349, mpc8548,
mpc8641d, p4080 and ls2085a).
Example:
uart@80230000 {

20
Documentation/devicetree/bindings/sound/atmel_ac97c.txt Normal file
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@@ -0,0 +1,20 @@
* Atmel AC97 controller
Required properties:
- compatible: "atmel,at91sam9263-ac97c"
- reg: Address and length of the register set for the device
- interrupts: Should contain AC97 interrupt
- ac97-gpios: Please refer to soc-ac97link.txt, only ac97-reset is used
Optional properties:
- pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
Example:
sound@fffa0000 {
compatible = "atmel,at91sam9263-ac97c";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ac97>;
reg = <0xfffa0000 0x4000>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
ac97-gpios = <&pioB 0 0 &pioB 2 0 &pioC 29 GPIO_ACTIVE_LOW>;
};

4
Documentation/devicetree/bindings/vendor-prefixes.txt
View File

@@ -12,6 +12,7 @@ adh AD Holdings Plc.
adi Analog Devices, Inc.
aeroflexgaisler Aeroflex Gaisler AB
allwinner Allwinner Technology Co., Ltd.
alphascale AlphaScale Integrated Circuits Systems, Inc.
altr Altera Corp.
amcc Applied Micro Circuits Corporation (APM, formally AMCC)
amd Advanced Micro Devices (AMD), Inc.
@@ -34,9 +35,11 @@ capella Capella Microsystems, Inc
cavium Cavium, Inc.
cdns Cadence Design Systems Inc.
chipidea Chipidea, Inc
chipspark ChipSPARK
chrp Common Hardware Reference Platform
chunghwa Chunghwa Picture Tubes Ltd.
cirrus Cirrus Logic, Inc.
cloudengines Cloud Engines, Inc.
cnm Chips&Media, Inc.
cnxt Conexant Systems, Inc.
cortina Cortina Systems, Inc.
@@ -65,6 +68,7 @@ everest Everest Semiconductor Co. Ltd.
everspin Everspin Technologies, Inc.
excito Excito
fcs Fairchild Semiconductor
firefly Firefly
fsl Freescale Semiconductor
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.

4
Documentation/devicetree/bindings/video/exynos_dsim.txt
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@@ -21,7 +21,7 @@ Required properties:
according to DSI host bindings (see MIPI DSI bindings [1])
Optional properties:
- samsung,power-domain: a phandle to DSIM power domain node
- power-domains: a phandle to DSIM power domain node
Child nodes:
Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
@@ -53,7 +53,7 @@ Example:
phy-names = "dsim";
vddcore-supply = <&vusb_reg>;
vddio-supply = <&vmipi_reg>;
samsung,power-domain = <&pd_lcd0>;
power-domains = <&pd_lcd0>;
#address-cells = <1>;
#size-cells = <0>;
samsung,pll-clock-frequency = <24000000>;

4
Documentation/devicetree/bindings/video/samsung-fimd.txt
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@@ -38,7 +38,7 @@ Required properties:
property. Must contain "sclk_fimd" and "fimd".
Optional Properties:
- samsung,power-domain: a phandle to FIMD power domain node.
- power-domains: a phandle to FIMD power domain node.
- samsung,invert-vden: video enable signal is inverted
- samsung,invert-vclk: video clock signal is inverted
- display-timings: timing settings for FIMD, as described in document [1].
@@ -97,7 +97,7 @@ SoC specific DT entry:
interrupts = <11 0>, <11 1>, <11 2>;
clocks = <&clock 140>, <&clock 283>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
power-domains = <&pd_lcd0>;
status = "disabled";
};