ARM: iop32x: merge everything into mach-iop32x/
Various bits of iop32x are now in their traditional locations in plat-iop, mach-iop/include/mach/ and in include/asm/mach/hardware. As nothing outside of the iop32x mach code references these any more, this can all be moved into one place now. The only remaining things in the include/mach/ directory are now the NR_IRQS definition, the entry-macros.S file and the the decompressor uart access. After the irqchip code has been converted to SPARSE_IRQ and GENERIC_IRQ_MULTI_HANDLER, it can be moved to ARCH_MULTIPLATFORM. Link: https://lore.kernel.org/r/20190809163334.489360-7-arnd@arndb.de Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
401
arch/arm/mach-iop32x/pci.c
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401
arch/arm/mach-iop32x/pci.c
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/plat-iop/pci.c
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*
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* PCI support for the Intel IOP32X and IOP33X processors
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright (C) 2002 Rory Bolt
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <asm/signal.h>
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#include <asm/mach/pci.h>
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#include "hardware.h"
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#include "iop3xx.h"
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// #define DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...) do { } while (0)
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#endif
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/*
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* This routine builds either a type0 or type1 configuration command. If the
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* bus is on the 803xx then a type0 made, else a type1 is created.
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*/
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static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
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{
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struct pci_sys_data *sys = bus->sysdata;
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u32 addr;
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if (sys->busnr == bus->number)
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addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
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else
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addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
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addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
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return addr;
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}
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/*
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* This routine checks the status of the last configuration cycle. If an error
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* was detected it returns a 1, else it returns a 0. The errors being checked
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* are parity, master abort, target abort (master and target). These types of
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* errors occur during a config cycle where there is no device, like during
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* the discovery stage.
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*/
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static int iop3xx_pci_status(void)
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{
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unsigned int status;
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int ret = 0;
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/*
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* Check the status registers.
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*/
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status = *IOP3XX_ATUSR;
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if (status & 0xf900) {
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DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
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*IOP3XX_ATUSR = status & 0xf900;
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ret = 1;
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}
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status = *IOP3XX_ATUISR;
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if (status & 0x679f) {
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DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
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*IOP3XX_ATUISR = status & 0x679f;
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ret = 1;
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}
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return ret;
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}
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/*
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* Simply write the address register and read the configuration
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* data. Note that the 4 nops ensure that we are able to handle
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* a delayed abort (in theory.)
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*/
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static u32 iop3xx_read(unsigned long addr)
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{
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u32 val;
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__asm__ __volatile__(
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"str %1, [%2]\n\t"
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"ldr %0, [%3]\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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: "=r" (val)
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: "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
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return val;
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}
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/*
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* The read routines must check the error status of the last configuration
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* cycle. If there was an error, the routine returns all hex f's.
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*/
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static int
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iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
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u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
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if (iop3xx_pci_status())
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val = 0xffffffff;
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*value = val;
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
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u32 val;
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if (size != 4) {
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val = iop3xx_read(addr);
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if (iop3xx_pci_status())
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return PCIBIOS_SUCCESSFUL;
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where = (where & 3) * 8;
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if (size == 1)
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val &= ~(0xff << where);
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else
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val &= ~(0xffff << where);
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*IOP3XX_OCCDR = val | value << where;
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} else {
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asm volatile(
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"str %1, [%2]\n\t"
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"str %0, [%3]\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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:
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: "r" (value), "r" (addr),
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"r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
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}
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops iop3xx_ops = {
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.read = iop3xx_read_config,
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.write = iop3xx_write_config,
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};
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/*
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* When a PCI device does not exist during config cycles, the 80200 gets a
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* bus error instead of returning 0xffffffff. This handler simply returns.
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*/
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static int
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iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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{
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DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
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addr, fsr, regs->ARM_pc, regs->ARM_lr);
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/*
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* If it was an imprecise abort, then we need to correct the
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* return address to be _after_ the instruction.
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*/
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if (fsr & (1 << 10))
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regs->ARM_pc += 4;
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return 0;
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}
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int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
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{
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struct resource *res;
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if (nr != 0)
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return 0;
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res = kzalloc(sizeof(struct resource), GFP_KERNEL);
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if (!res)
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panic("PCI: unable to alloc resources");
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res->start = IOP3XX_PCI_LOWER_MEM_PA;
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res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
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res->name = "IOP3XX PCI Memory Space";
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res->flags = IORESOURCE_MEM;
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request_resource(&iomem_resource, res);
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/*
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* Use whatever translation is already setup.
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*/
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sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
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pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
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pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
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return 1;
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}
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void __init iop3xx_atu_setup(void)
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{
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/* BAR 0 ( Disabled ) */
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*IOP3XX_IAUBAR0 = 0x0;
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*IOP3XX_IABAR0 = 0x0;
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*IOP3XX_IATVR0 = 0x0;
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*IOP3XX_IALR0 = 0x0;
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/* BAR 1 ( Disabled ) */
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*IOP3XX_IAUBAR1 = 0x0;
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*IOP3XX_IABAR1 = 0x0;
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*IOP3XX_IALR1 = 0x0;
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/* BAR 2 (1:1 mapping with Physical RAM) */
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/* Set limit and enable */
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*IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1;
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*IOP3XX_IAUBAR2 = 0x0;
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/* Align the inbound bar with the base of memory */
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*IOP3XX_IABAR2 = PHYS_OFFSET |
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PCI_BASE_ADDRESS_MEM_TYPE_64 |
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PCI_BASE_ADDRESS_MEM_PREFETCH;
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*IOP3XX_IATVR2 = PHYS_OFFSET;
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/* Outbound window 0 */
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*IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA;
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*IOP3XX_OUMWTVR0 = 0;
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/* Outbound window 1 */
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*IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA +
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IOP3XX_PCI_MEM_WINDOW_SIZE / 2;
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*IOP3XX_OUMWTVR1 = 0;
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/* BAR 3 ( Disabled ) */
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*IOP3XX_IAUBAR3 = 0x0;
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*IOP3XX_IABAR3 = 0x0;
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*IOP3XX_IATVR3 = 0x0;
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*IOP3XX_IALR3 = 0x0;
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/* Setup the I/O Bar
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*/
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*IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA;
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/* Enable inbound and outbound cycles
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*/
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*IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
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*IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN;
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}
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void __init iop3xx_atu_disable(void)
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{
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*IOP3XX_ATUCMD = 0;
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*IOP3XX_ATUCR = 0;
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/* wait for cycles to quiesce */
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while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY |
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IOP3XX_PCSR_IN_Q_BUSY))
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cpu_relax();
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/* BAR 0 ( Disabled ) */
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*IOP3XX_IAUBAR0 = 0x0;
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*IOP3XX_IABAR0 = 0x0;
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*IOP3XX_IATVR0 = 0x0;
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*IOP3XX_IALR0 = 0x0;
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/* BAR 1 ( Disabled ) */
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*IOP3XX_IAUBAR1 = 0x0;
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*IOP3XX_IABAR1 = 0x0;
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*IOP3XX_IALR1 = 0x0;
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/* BAR 2 ( Disabled ) */
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*IOP3XX_IAUBAR2 = 0x0;
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*IOP3XX_IABAR2 = 0x0;
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*IOP3XX_IATVR2 = 0x0;
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*IOP3XX_IALR2 = 0x0;
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/* BAR 3 ( Disabled ) */
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*IOP3XX_IAUBAR3 = 0x0;
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*IOP3XX_IABAR3 = 0x0;
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*IOP3XX_IATVR3 = 0x0;
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*IOP3XX_IALR3 = 0x0;
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/* Clear the outbound windows */
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*IOP3XX_OIOWTVR = 0;
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/* Outbound window 0 */
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*IOP3XX_OMWTVR0 = 0;
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*IOP3XX_OUMWTVR0 = 0;
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/* Outbound window 1 */
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*IOP3XX_OMWTVR1 = 0;
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*IOP3XX_OUMWTVR1 = 0;
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}
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/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
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int init_atu;
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int iop3xx_get_init_atu(void) {
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/* check if default has been overridden */
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if (init_atu != IOP3XX_INIT_ATU_DEFAULT)
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return init_atu;
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else
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return IOP3XX_INIT_ATU_DISABLE;
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}
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static void __init iop3xx_atu_debug(void)
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{
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DBG("PCI: Intel IOP3xx PCI init.\n");
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DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n",
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*IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0);
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DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n",
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*IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1);
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DBG("PCI: Outbound IO window: PCI 0x%08x\n",
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*IOP3XX_OIOWTVR);
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DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
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*IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
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DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n",
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*IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1);
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DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
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*IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
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DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
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*IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
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DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n",
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0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
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DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
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DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
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hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort");
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}
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/* for platforms that might be host-bus-adapters */
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void __init iop3xx_pci_preinit_cond(void)
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{
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if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
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iop3xx_atu_disable();
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iop3xx_atu_setup();
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iop3xx_atu_debug();
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}
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}
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void __init iop3xx_pci_preinit(void)
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{
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pcibios_min_mem = 0;
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iop3xx_atu_disable();
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iop3xx_atu_setup();
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iop3xx_atu_debug();
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}
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/* allow init_atu to be user overridden */
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static int __init iop3xx_init_atu_setup(char *str)
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{
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init_atu = IOP3XX_INIT_ATU_DEFAULT;
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if (str) {
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while (*str != '\0') {
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switch (*str) {
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case 'y':
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case 'Y':
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init_atu = IOP3XX_INIT_ATU_ENABLE;
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break;
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case 'n':
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case 'N':
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init_atu = IOP3XX_INIT_ATU_DISABLE;
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break;
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case ',':
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case '=':
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break;
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default:
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printk(KERN_DEBUG "\"%s\" malformed at "
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"character: \'%c\'",
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__func__,
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*str);
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*(str + 1) = '\0';
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}
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str++;
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}
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}
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return 1;
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}
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__setup("iop3xx_init_atu", iop3xx_init_atu_setup);
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