drm/i915/gvt: Legacy HSW related MMIO handler clean up
remove all the legacy pre-BDW mmio handlers and the corresponding usage/definition since pre-BDW platforms are not supported in GVT environment. v2: - clean up all the left dirty code before BDW, e.g all D_HSW usage and itself, D_IVB, D_PRE_BDW. (Zhenyu) v3: - change is based on gvt-staging. (Zhenyu) Signed-off-by: fred gao <fred.gao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Zhenyu Wang

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a1dcba9058
@@ -39,26 +39,18 @@
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struct intel_gvt;
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struct intel_vgpu;
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#define D_SNB (1 << 0)
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#define D_IVB (1 << 1)
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#define D_HSW (1 << 2)
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#define D_BDW (1 << 3)
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#define D_SKL (1 << 4)
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#define D_KBL (1 << 5)
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#define D_BDW (1 << 0)
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#define D_SKL (1 << 1)
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#define D_KBL (1 << 2)
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#define D_GEN9PLUS (D_SKL | D_KBL)
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#define D_GEN8PLUS (D_BDW | D_SKL | D_KBL)
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#define D_GEN75PLUS (D_HSW | D_BDW | D_SKL | D_KBL)
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#define D_GEN7PLUS (D_IVB | D_HSW | D_BDW | D_SKL | D_KBL)
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#define D_SKL_PLUS (D_SKL | D_KBL)
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#define D_BDW_PLUS (D_BDW | D_SKL | D_KBL)
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#define D_HSW_PLUS (D_HSW | D_BDW | D_SKL | D_KBL)
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#define D_IVB_PLUS (D_IVB | D_HSW | D_BDW | D_SKL | D_KBL)
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#define D_PRE_BDW (D_SNB | D_IVB | D_HSW)
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#define D_PRE_SKL (D_SNB | D_IVB | D_HSW | D_BDW)
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#define D_ALL (D_SNB | D_IVB | D_HSW | D_BDW | D_SKL | D_KBL)
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#define D_PRE_SKL (D_BDW)
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#define D_ALL (D_BDW | D_SKL | D_KBL)
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struct intel_gvt_mmio_info {
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u32 offset;
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