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m68knommu: create bit definitions for the version 2 ColdFire cache controller

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The version 2 ColdFire CPU based cores all contain a similar cache
controller unit. Create a set of bit flag definitions for the supporting
registers.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer
2010-11-09 10:12:29 +10:00
parent 63e83c8a52
commit a12cf0a8c6
8 changed files with 72 additions and 0 deletions
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5
arch/m68k/include/asm/m520xsim.h
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@@ -14,6 +14,8 @@
#define CPU_NAME "COLDFIRE(m520x)"
#define CPU_INSTR_PER_JIFFY 3
#include <asm/m52xxacr.h>
/*
* Define the 520x SIM register set addresses.
*/
@@ -57,6 +59,9 @@
#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
/*
* EPORT and GPIO registers.
*/
#define MCFEPORT_EPDDR 0xFC088002
#define MCFEPORT_EPDR 0xFC088004
#define MCFEPORT_EPPDR 0xFC088005