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drm/radeon/cik: properly set up the clearstate buffer for pg (v2)

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The format of the clearstate buffer used for pg (powergating)
changed between NI and SI.  This formats it properly for what
the hardware expects on SI+.

v2: fix addresses

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2013-08-22 11:57:46 -04:00
parent ddc76ff6c7
commit a0f38609c9
2 changed files with 103 additions and 3 deletions
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93
drivers/gpu/drm/radeon/cik.c
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@@ -5622,7 +5622,7 @@ static void cik_init_gfx_cgpg(struct radeon_device *rdev)
if (rdev->rlc.cs_data) {
WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));
WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_gpu_addr);
WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));
WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);
} else {
WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
@@ -5670,6 +5670,97 @@ static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
cik_enable_gfx_dynamic_mgpg(rdev, enable);
}
u32 cik_get_csb_size(struct radeon_device *rdev)
{
u32 count = 0;
const struct cs_section_def *sect = NULL;
const struct cs_extent_def *ext = NULL;
if (rdev->rlc.cs_data == NULL)
return 0;
/* begin clear state */
count += 2;
/* context control state */
count += 3;
for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
for (ext = sect->section; ext->extent != NULL; ++ext) {
if (sect->id == SECT_CONTEXT)
count += 2 + ext->reg_count;
else
return 0;
}
}
/* pa_sc_raster_config/pa_sc_raster_config1 */
count += 4;
/* end clear state */
count += 2;
/* clear state */
count += 2;
return count;
}
void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
{
u32 count = 0, i;
const struct cs_section_def *sect = NULL;
const struct cs_extent_def *ext = NULL;
if (rdev->rlc.cs_data == NULL)
return;
if (buffer == NULL)
return;
buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0);
buffer[count++] = PACKET3_PREAMBLE_BEGIN_CLEAR_STATE;
buffer[count++] = PACKET3(PACKET3_CONTEXT_CONTROL, 1);
buffer[count++] = 0x80000000;
buffer[count++] = 0x80000000;
for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
for (ext = sect->section; ext->extent != NULL; ++ext) {
if (sect->id == SECT_CONTEXT) {
buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count);
buffer[count++] = ext->reg_index - 0xa000;
for (i = 0; i < ext->reg_count; i++)
buffer[count++] = ext->extent[i];
} else {
return;
}
}
}
buffer[count++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2);
buffer[count++] = PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START;
switch (rdev->family) {
case CHIP_BONAIRE:
buffer[count++] = 0x16000012;
buffer[count++] = 0x00000000;
break;
case CHIP_KAVERI:
buffer[count++] = 0x00000000; /* XXX */
buffer[count++] = 0x00000000;
break;
case CHIP_KABINI:
buffer[count++] = 0x00000000; /* XXX */
buffer[count++] = 0x00000000;
break;
default:
buffer[count++] = 0x00000000;
buffer[count++] = 0x00000000;
break;
}
buffer[count++] = PACKET3(PACKET3_PREAMBLE_CNTL, 0);
buffer[count++] = PACKET3_PREAMBLE_END_CLEAR_STATE;
buffer[count++] = PACKET3(PACKET3_CLEAR_STATE, 0);
buffer[count++] = 0;
}
static void cik_init_pg(struct radeon_device *rdev)
{
if (rdev->pg_flags) {