[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
committed by
Russell King
Russell King
parent
a1b81a84ff
commit
a09e64fbc0
61
arch/arm/mach-integrator/include/mach/bits.h
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61
arch/arm/mach-integrator/include/mach/bits.h
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@@ -0,0 +1,61 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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||||
* You should have received a copy of the GNU General Public License
|
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* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* DO NOT EDIT!! - this file automatically generated
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* from .s file by awk -f s2h.awk
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*/
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/* Bit field definitions
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* Copyright (C) ARM Limited 1998. All rights reserved.
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*/
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#ifndef __bits_h
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#define __bits_h 1
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#define BIT0 0x00000001
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#define BIT1 0x00000002
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#define BIT2 0x00000004
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#define BIT3 0x00000008
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#define BIT4 0x00000010
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#define BIT5 0x00000020
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#define BIT6 0x00000040
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#define BIT7 0x00000080
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#define BIT8 0x00000100
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#define BIT9 0x00000200
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#define BIT10 0x00000400
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#define BIT11 0x00000800
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#define BIT12 0x00001000
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#define BIT13 0x00002000
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#define BIT14 0x00004000
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#define BIT15 0x00008000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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#endif
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/* END */
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36
arch/arm/mach-integrator/include/mach/cm.h
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36
arch/arm/mach-integrator/include/mach/cm.h
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@@ -0,0 +1,36 @@
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/*
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* update the core module control register.
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*/
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void cm_control(u32, u32);
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#define CM_CTRL_LED (1 << 0)
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#define CM_CTRL_nMBDET (1 << 1)
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#define CM_CTRL_REMAP (1 << 2)
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#define CM_CTRL_RESET (1 << 3)
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/*
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* Integrator/AP,PP2 specific
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*/
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#define CM_CTRL_HIGHVECTORS (1 << 4)
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#define CM_CTRL_BIGENDIAN (1 << 5)
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#define CM_CTRL_FASTBUS (1 << 6)
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#define CM_CTRL_SYNC (1 << 7)
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/*
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* ARM926/946/966 Integrator/CP specific
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*/
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#define CM_CTRL_LCDBIASEN (1 << 8)
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#define CM_CTRL_LCDBIASUP (1 << 9)
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#define CM_CTRL_LCDBIASDN (1 << 10)
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#define CM_CTRL_LCDMUXSEL_MASK (7 << 11)
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#define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11)
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#define CM_CTRL_LCDMUXSEL_VGA_16BPP (2 << 11)
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#define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11)
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#define CM_CTRL_LCDMUXSEL_VGA_8421BPP (4 << 11)
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#define CM_CTRL_LCDEN0 (1 << 14)
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#define CM_CTRL_LCDEN1 (1 << 15)
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#define CM_CTRL_STATIC1 (1 << 16)
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#define CM_CTRL_STATIC2 (1 << 17)
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#define CM_CTRL_STATIC (1 << 18)
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#define CM_CTRL_n24BITEN (1 << 19)
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#define CM_CTRL_EBIWP (1 << 20)
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22
arch/arm/mach-integrator/include/mach/debug-macro.S
Normal file
22
arch/arm/mach-integrator/include/mach/debug-macro.S
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@@ -0,0 +1,22 @@
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/* arch/arm/mach-integrator/include/mach/debug-macro.S
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*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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.macro addruart,rx
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mrc p15, 0, \rx, c1, c0
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tst \rx, #1 @ MMU enabled?
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moveq \rx, #0x16000000 @ physical base address
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movne \rx, #0xf0000000 @ virtual base
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addne \rx, \rx, #0x16000000 >> 4
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.endm
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#include <asm/hardware/debug-pl01x.S>
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19
arch/arm/mach-integrator/include/mach/dma.h
Normal file
19
arch/arm/mach-integrator/include/mach/dma.h
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@@ -0,0 +1,19 @@
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/*
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* arch/arm/mach-integrator/include/mach/dma.h
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*
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* Copyright (C) 1997,1998 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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44
arch/arm/mach-integrator/include/mach/entry-macro.S
Normal file
44
arch/arm/mach-integrator/include/mach/entry-macro.S
Normal file
@@ -0,0 +1,44 @@
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/*
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* arch/arm/mach-integrator/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for Integrator platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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/* FIXME: should not be using soo many LDRs here */
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ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
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mov \irqnr, #IRQ_PIC_START
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ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status
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ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
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teq \irqstat, #0
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ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
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moveq \irqnr, #IRQ_CIC_START
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1001: tst \irqstat, #15
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bne 1002f
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add \irqnr, \irqnr, #4
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movs \irqstat, \irqstat, lsr #4
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bne 1001b
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1002: tst \irqstat, #1
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bne 1003f
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add \irqnr, \irqnr, #1
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movs \irqstat, \irqstat, lsr #1
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bne 1002b
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1003: /* EQ will be set if no irqs pending */
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.endm
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48
arch/arm/mach-integrator/include/mach/hardware.h
Normal file
48
arch/arm/mach-integrator/include/mach/hardware.h
Normal file
@@ -0,0 +1,48 @@
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/*
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* arch/arm/mach-integrator/include/mach/hardware.h
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*
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* This file contains the hardware definitions of the Integrator.
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*
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* Copyright (C) 1999 ARM Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <asm/sizes.h>
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#include <mach/platform.h>
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/*
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* Where in virtual memory the IO devices (timers, system controllers
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* and so on)
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*/
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#define IO_BASE 0xF0000000 // VA of IO
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#define IO_SIZE 0x0B000000 // How much?
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#define IO_START INTEGRATOR_HDR_BASE // PA of IO
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#define PCIO_BASE PCI_IO_VADDR
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#define PCIMEM_BASE PCI_MEMORY_VADDR
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/* macro to get at IO space when running virtually */
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#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE)
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#define pcibios_assign_all_busses() 1
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#define PCIBIOS_MIN_IO 0x6000
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#define PCIBIOS_MIN_MEM 0x00100000
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#endif
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18
arch/arm/mach-integrator/include/mach/impd1.h
Normal file
18
arch/arm/mach-integrator/include/mach/impd1.h
Normal file
@@ -0,0 +1,18 @@
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#define IMPD1_OSC1 0x00
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#define IMPD1_OSC2 0x04
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#define IMPD1_LOCK 0x08
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#define IMPD1_LEDS 0x0c
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#define IMPD1_INT 0x10
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#define IMPD1_SW 0x14
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#define IMPD1_CTRL 0x18
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#define IMPD1_CTRL_DISP_LCD (0 << 0)
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#define IMPD1_CTRL_DISP_VGA (1 << 0)
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#define IMPD1_CTRL_DISP_LCD1 (2 << 0)
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#define IMPD1_CTRL_DISP_ENABLE (1 << 2)
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#define IMPD1_CTRL_DISP_MASK (7 << 0)
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struct device;
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void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
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36
arch/arm/mach-integrator/include/mach/io.h
Normal file
36
arch/arm/mach-integrator/include/mach/io.h
Normal file
@@ -0,0 +1,36 @@
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/*
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* arch/arm/mach-integrator/include/mach/io.h
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*
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* Copyright (C) 1999 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
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*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_ARCH_IO_H
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#define __ASM_ARM_ARCH_IO_H
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#define IO_SPACE_LIMIT 0xffff
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/*
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* WARNING: this has to mirror definitions in platform.h
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*/
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#define PCI_MEMORY_VADDR 0xe8000000
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#define PCI_CONFIG_VADDR 0xec000000
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#define PCI_V3_VADDR 0xed000000
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#define PCI_IO_VADDR 0xee000000
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#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
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#define __mem_pci(a) (a)
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#endif
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82
arch/arm/mach-integrator/include/mach/irqs.h
Normal file
82
arch/arm/mach-integrator/include/mach/irqs.h
Normal file
@@ -0,0 +1,82 @@
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/*
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* arch/arm/mach-integrator/include/mach/irqs.h
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*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd.
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
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/*
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* Interrupt numbers
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*/
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#define IRQ_PIC_START 0
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#define IRQ_SOFTINT 0
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#define IRQ_UARTINT0 1
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#define IRQ_UARTINT1 2
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#define IRQ_KMIINT0 3
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#define IRQ_KMIINT1 4
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#define IRQ_TIMERINT0 5
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#define IRQ_TIMERINT1 6
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#define IRQ_TIMERINT2 7
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#define IRQ_RTCINT 8
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#define IRQ_AP_EXPINT0 9
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#define IRQ_AP_EXPINT1 10
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#define IRQ_AP_EXPINT2 11
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#define IRQ_AP_EXPINT3 12
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#define IRQ_AP_PCIINT0 13
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#define IRQ_AP_PCIINT1 14
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#define IRQ_AP_PCIINT2 15
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#define IRQ_AP_PCIINT3 16
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#define IRQ_AP_V3INT 17
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#define IRQ_AP_CPINT0 18
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#define IRQ_AP_CPINT1 19
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#define IRQ_AP_LBUSTIMEOUT 20
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#define IRQ_AP_APCINT 21
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#define IRQ_CP_CLCDCINT 22
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#define IRQ_CP_MMCIINT0 23
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#define IRQ_CP_MMCIINT1 24
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#define IRQ_CP_AACIINT 25
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#define IRQ_CP_CPPLDINT 26
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#define IRQ_CP_ETHINT 27
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#define IRQ_CP_TSPENINT 28
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#define IRQ_PIC_END 31
|
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|
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#define IRQ_CIC_START 32
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#define IRQ_CM_SOFTINT 32
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#define IRQ_CM_COMMRX 33
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#define IRQ_CM_COMMTX 34
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#define IRQ_CIC_END 34
|
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|
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/*
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* IntegratorCP only
|
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*/
|
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#define IRQ_SIC_START 35
|
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#define IRQ_SIC_CP_SOFTINT 35
|
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#define IRQ_SIC_CP_RI0 36
|
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#define IRQ_SIC_CP_RI1 37
|
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#define IRQ_SIC_CP_CARDIN 38
|
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#define IRQ_SIC_CP_LMINT0 39
|
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#define IRQ_SIC_CP_LMINT1 40
|
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#define IRQ_SIC_CP_LMINT2 41
|
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#define IRQ_SIC_CP_LMINT3 42
|
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#define IRQ_SIC_CP_LMINT4 43
|
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#define IRQ_SIC_CP_LMINT5 44
|
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#define IRQ_SIC_CP_LMINT6 45
|
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#define IRQ_SIC_CP_LMINT7 46
|
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#define IRQ_SIC_END 46
|
||||
|
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#define NR_IRQS 47
|
||||
|
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23
arch/arm/mach-integrator/include/mach/lm.h
Normal file
23
arch/arm/mach-integrator/include/mach/lm.h
Normal file
@@ -0,0 +1,23 @@
|
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|
||||
struct lm_device {
|
||||
struct device dev;
|
||||
struct resource resource;
|
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unsigned int irq;
|
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unsigned int id;
|
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};
|
||||
|
||||
struct lm_driver {
|
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struct device_driver drv;
|
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int (*probe)(struct lm_device *);
|
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void (*remove)(struct lm_device *);
|
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int (*suspend)(struct lm_device *, pm_message_t);
|
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int (*resume)(struct lm_device *);
|
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};
|
||||
|
||||
int lm_driver_register(struct lm_driver *drv);
|
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void lm_driver_unregister(struct lm_driver *drv);
|
||||
|
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int lm_device_register(struct lm_device *dev);
|
||||
|
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#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
|
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#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
|
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39
arch/arm/mach-integrator/include/mach/memory.h
Normal file
39
arch/arm/mach-integrator/include/mach/memory.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* arch/arm/mach-integrator/include/mach/memory.h
|
||||
*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
/*
|
||||
* Physical DRAM offset.
|
||||
*/
|
||||
#define PHYS_OFFSET UL(0x00000000)
|
||||
#define BUS_OFFSET UL(0x80000000)
|
||||
|
||||
/*
|
||||
* Virtual view <-> DMA view memory address translations
|
||||
* virt_to_bus: Used to translate the virtual address to an
|
||||
* address suitable to be passed to set_dma_addr
|
||||
* bus_to_virt: Used to convert an address for DMA operations
|
||||
* to an address that the kernel can use.
|
||||
*/
|
||||
#define __virt_to_bus(x) (x - PAGE_OFFSET + BUS_OFFSET)
|
||||
#define __bus_to_virt(x) (x - BUS_OFFSET + PAGE_OFFSET)
|
||||
|
||||
#endif
|
||||
469
arch/arm/mach-integrator/include/mach/platform.h
Normal file
469
arch/arm/mach-integrator/include/mach/platform.h
Normal file
@@ -0,0 +1,469 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
/* DO NOT EDIT!! - this file automatically generated
|
||||
* from .s file by awk -f s2h.awk
|
||||
*/
|
||||
/**************************************************************************
|
||||
* * Copyright © ARM Limited 1998. All rights reserved.
|
||||
* ***********************************************************************/
|
||||
/* ************************************************************************
|
||||
*
|
||||
* Integrator address map
|
||||
*
|
||||
* NOTE: This is a multi-hosted header file for use with uHAL and
|
||||
* supported debuggers.
|
||||
*
|
||||
* $Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $
|
||||
*
|
||||
* ***********************************************************************/
|
||||
|
||||
#ifndef __address_h
|
||||
#define __address_h 1
|
||||
|
||||
/* ========================================================================
|
||||
* Integrator definitions
|
||||
* ========================================================================
|
||||
* ------------------------------------------------------------------------
|
||||
* Memory definitions
|
||||
* ------------------------------------------------------------------------
|
||||
* Integrator memory map
|
||||
*
|
||||
*/
|
||||
#define INTEGRATOR_BOOT_ROM_LO 0x00000000
|
||||
#define INTEGRATOR_BOOT_ROM_HI 0x20000000
|
||||
#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
|
||||
#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
|
||||
|
||||
/*
|
||||
* New Core Modules have different amounts of SSRAM, the amount of SSRAM
|
||||
* fitted can be found in HDR_STAT.
|
||||
*
|
||||
* The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
|
||||
* the minimum amount of SSRAM fitted on any core module.
|
||||
*
|
||||
* New Core Modules also alias the SSRAM.
|
||||
*
|
||||
*/
|
||||
#define INTEGRATOR_SSRAM_BASE 0x00000000
|
||||
#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
|
||||
#define INTEGRATOR_SSRAM_SIZE SZ_256K
|
||||
|
||||
#define INTEGRATOR_FLASH_BASE 0x24000000
|
||||
#define INTEGRATOR_FLASH_SIZE SZ_32M
|
||||
|
||||
#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
|
||||
#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
|
||||
|
||||
/*
|
||||
* SDRAM is a SIMM therefore the size is not known.
|
||||
*
|
||||
*/
|
||||
#define INTEGRATOR_SDRAM_BASE 0x00040000
|
||||
|
||||
#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
|
||||
#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
|
||||
#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
|
||||
#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
|
||||
#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
|
||||
|
||||
/*
|
||||
* Logic expansion modules
|
||||
*
|
||||
*/
|
||||
#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
|
||||
#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
|
||||
#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
|
||||
#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
|
||||
#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* Integrator header card registers
|
||||
* ------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define INTEGRATOR_HDR_ID_OFFSET 0x00
|
||||
#define INTEGRATOR_HDR_PROC_OFFSET 0x04
|
||||
#define INTEGRATOR_HDR_OSC_OFFSET 0x08
|
||||
#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
|
||||
#define INTEGRATOR_HDR_STAT_OFFSET 0x10
|
||||
#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
|
||||
#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
|
||||
#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
|
||||
#define INTEGRATOR_HDR_IC_OFFSET 0x40
|
||||
#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
|
||||
#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
|
||||
|
||||
#define INTEGRATOR_HDR_BASE 0x10000000
|
||||
#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
|
||||
#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
|
||||
#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
|
||||
#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
|
||||
#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
|
||||
#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
|
||||
#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
|
||||
#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
|
||||
#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
|
||||
#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
|
||||
#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
|
||||
|
||||
#define INTEGRATOR_HDR_CTRL_LED 0x01
|
||||
#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
|
||||
#define INTEGRATOR_HDR_CTRL_REMAP 0x04
|
||||
#define INTEGRATOR_HDR_CTRL_RESET 0x08
|
||||
#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
|
||||
#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
|
||||
#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
|
||||
#define INTEGRATOR_HDR_CTRL_SYNC 0x80
|
||||
|
||||
#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
|
||||
#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
|
||||
#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
|
||||
#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
|
||||
#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
|
||||
#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
|
||||
#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
|
||||
#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
|
||||
#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
|
||||
#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
|
||||
#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
|
||||
#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
|
||||
#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
|
||||
#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
|
||||
#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
|
||||
#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
|
||||
#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
|
||||
#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
|
||||
#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
|
||||
#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
|
||||
#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
|
||||
#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
|
||||
#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
|
||||
#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
|
||||
#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
|
||||
#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
|
||||
#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
|
||||
#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
|
||||
#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
|
||||
#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
|
||||
#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
|
||||
#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
|
||||
|
||||
#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
|
||||
#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
|
||||
|
||||
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
|
||||
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
|
||||
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
|
||||
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
|
||||
#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
|
||||
|
||||
#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* Integrator system registers
|
||||
* ------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* System Controller
|
||||
*
|
||||
*/
|
||||
#define INTEGRATOR_SC_ID_OFFSET 0x00
|
||||
#define INTEGRATOR_SC_OSC_OFFSET 0x04
|
||||
#define INTEGRATOR_SC_CTRLS_OFFSET 0x08
|
||||
#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
|
||||
#define INTEGRATOR_SC_DEC_OFFSET 0x10
|
||||
#define INTEGRATOR_SC_ARB_OFFSET 0x14
|
||||
#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
|
||||
#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
|
||||
|
||||
#define INTEGRATOR_SC_BASE 0x11000000
|
||||
#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
|
||||
#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
|
||||
#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
|
||||
#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
|
||||
#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
|
||||
#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
|
||||
#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
|
||||
#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
|
||||
|
||||
#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
|
||||
#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
|
||||
#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
|
||||
#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
|
||||
#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
|
||||
#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
|
||||
|
||||
#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
|
||||
#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
|
||||
#define INTEGRATOR_SC_OSC_PCI_MASK 0x100
|
||||
|
||||
#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
|
||||
#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
|
||||
#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
|
||||
#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
|
||||
#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
|
||||
#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
|
||||
#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
|
||||
|
||||
/*
|
||||
* External Bus Interface
|
||||
*
|
||||
*/
|
||||
#define INTEGRATOR_EBI_BASE 0x12000000
|
||||
|
||||
#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
|
||||
#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
|
||||
#define INTEGRATOR_EBI_CSR2_OFFSET 0x08
|
||||
#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
|
||||
#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
|
||||
|
||||
#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
|
||||
#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
|
||||
#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
|
||||
#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
|
||||
#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
|
||||
|
||||
#define INTEGRATOR_EBI_8_BIT 0x00
|
||||
#define INTEGRATOR_EBI_16_BIT 0x01
|
||||
#define INTEGRATOR_EBI_32_BIT 0x02
|
||||
#define INTEGRATOR_EBI_WRITE_ENABLE 0x04
|
||||
#define INTEGRATOR_EBI_SYNC 0x08
|
||||
#define INTEGRATOR_EBI_WS_2 0x00
|
||||
#define INTEGRATOR_EBI_WS_3 0x10
|
||||
#define INTEGRATOR_EBI_WS_4 0x20
|
||||
#define INTEGRATOR_EBI_WS_5 0x30
|
||||
#define INTEGRATOR_EBI_WS_6 0x40
|
||||
#define INTEGRATOR_EBI_WS_7 0x50
|
||||
#define INTEGRATOR_EBI_WS_8 0x60
|
||||
#define INTEGRATOR_EBI_WS_9 0x70
|
||||
#define INTEGRATOR_EBI_WS_10 0x80
|
||||
#define INTEGRATOR_EBI_WS_11 0x90
|
||||
#define INTEGRATOR_EBI_WS_12 0xA0
|
||||
#define INTEGRATOR_EBI_WS_13 0xB0
|
||||
#define INTEGRATOR_EBI_WS_14 0xC0
|
||||
#define INTEGRATOR_EBI_WS_15 0xD0
|
||||
#define INTEGRATOR_EBI_WS_16 0xE0
|
||||
#define INTEGRATOR_EBI_WS_17 0xF0
|
||||
|
||||
|
||||
#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
|
||||
#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
|
||||
#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
|
||||
#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
|
||||
#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
|
||||
#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
|
||||
#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
|
||||
|
||||
/*
|
||||
* LED's & Switches
|
||||
*
|
||||
*/
|
||||
#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
|
||||
#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
|
||||
#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
|
||||
|
||||
#define INTEGRATOR_DBG_BASE 0x1A000000
|
||||
#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
|
||||
#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
|
||||
#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
|
||||
|
||||
|
||||
#if defined(CONFIG_ARCH_INTEGRATOR_AP)
|
||||
#define INTEGRATOR_GPIO_BASE 0x1B000000 /* GPIO */
|
||||
#elif defined(CONFIG_ARCH_INTEGRATOR_CP)
|
||||
#define INTEGRATOR_GPIO_BASE 0xC9000000 /* GPIO */
|
||||
#endif
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* KMI keyboard/mouse definitions
|
||||
* ------------------------------------------------------------------------
|
||||
*/
|
||||
/* PS2 Keyboard interface */
|
||||
#define KMI0_BASE INTEGRATOR_KBD_BASE
|
||||
|
||||
/* PS2 Mouse interface */
|
||||
#define KMI1_BASE INTEGRATOR_MOUSE_BASE
|
||||
|
||||
/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* Where in the memory map does PCI live?
|
||||
* ------------------------------------------------------------------------
|
||||
* This represents a fairly liberal usage of address space. Even though
|
||||
* the V3 only has two windows (therefore we need to map stuff on the fly),
|
||||
* we maintain the same addresses, even if they're not mapped.
|
||||
*
|
||||
*/
|
||||
#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */
|
||||
/* unused 256M from A0000000-AFFFFFFF might be used for I2O ???
|
||||
*/
|
||||
#define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */
|
||||
/* unused (128-16)M from B1000000-B7FFFFFF
|
||||
*/
|
||||
#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
|
||||
/* unused ((128-16)M - 64K) from XXX
|
||||
*/
|
||||
#define PHYS_PCI_V3_BASE 0x62000000
|
||||
|
||||
#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
|
||||
|
||||
/* 'export' these to UHAL */
|
||||
#define UHAL_PCI_IO PCI_IO_BASE
|
||||
#define UHAL_PCI_MEM PCI_MEM_BASE
|
||||
#define UHAL_PCI_ALLOC_IO_BASE 0x00004000
|
||||
#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
|
||||
#define UHAL_PCI_MAX_SLOT 20
|
||||
|
||||
/* ========================================================================
|
||||
* Start of uHAL definitions
|
||||
* ========================================================================
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* Integrator Interrupt Controllers
|
||||
* ------------------------------------------------------------------------
|
||||
*
|
||||
* Offsets from interrupt controller base
|
||||
*
|
||||
* System Controller interrupt controller base is
|
||||
*
|
||||
* INTEGRATOR_IC_BASE + (header_number << 6)
|
||||
*
|
||||
* Core Module interrupt controller base is
|
||||
*
|
||||
* INTEGRATOR_HDR_IC
|
||||
*
|
||||
*/
|
||||
#define IRQ_STATUS 0
|
||||
#define IRQ_RAW_STATUS 0x04
|
||||
#define IRQ_ENABLE 0x08
|
||||
#define IRQ_ENABLE_SET 0x08
|
||||
#define IRQ_ENABLE_CLEAR 0x0C
|
||||
|
||||
#define INT_SOFT_SET 0x10
|
||||
#define INT_SOFT_CLEAR 0x14
|
||||
|
||||
#define FIQ_STATUS 0x20
|
||||
#define FIQ_RAW_STATUS 0x24
|
||||
#define FIQ_ENABLE 0x28
|
||||
#define FIQ_ENABLE_SET 0x28
|
||||
#define FIQ_ENABLE_CLEAR 0x2C
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* Interrupts
|
||||
* ------------------------------------------------------------------------
|
||||
*
|
||||
*
|
||||
* Each Core Module has two interrupts controllers, one on the core module
|
||||
* itself and one in the system controller on the motherboard. The
|
||||
* READ_INT macro in target.s reads both interrupt controllers and returns
|
||||
* a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
|
||||
* and bits 24 to 31 are from the core module.
|
||||
*
|
||||
* The following definitions relate to the bitmask returned by READ_INT.
|
||||
*
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
* LED's - The header LED is not accessible via the uHAL API
|
||||
* ------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define GREEN_LED 0x01
|
||||
#define YELLOW_LED 0x02
|
||||
#define RED_LED 0x04
|
||||
#define GREEN_LED_2 0x08
|
||||
#define ALL_LEDS 0x0F
|
||||
|
||||
#define LED_BANK INTEGRATOR_DBG_LEDS
|
||||
|
||||
/*
|
||||
* Memory definitions - run uHAL out of SSRAM.
|
||||
*
|
||||
*/
|
||||
#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
|
||||
|
||||
/*
|
||||
* Application Flash
|
||||
*
|
||||
*/
|
||||
#define FLASH_BASE INTEGRATOR_FLASH_BASE
|
||||
#define FLASH_SIZE INTEGRATOR_FLASH_SIZE
|
||||
#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
|
||||
#define FLASH_BLOCK_SIZE SZ_128K
|
||||
|
||||
/*
|
||||
* Boot Flash
|
||||
*
|
||||
*/
|
||||
#define EPROM_BASE INTEGRATOR_BOOT_ROM_HI
|
||||
#define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE
|
||||
#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
|
||||
|
||||
/*
|
||||
* Clean base - dummy
|
||||
*
|
||||
*/
|
||||
#define CLEAN_BASE EPROM_BASE
|
||||
|
||||
/*
|
||||
* Timer definitions
|
||||
*
|
||||
* Only use timer 1 & 2
|
||||
* (both run at 24MHz and will need the clock divider set to 16).
|
||||
*
|
||||
* Timer 0 runs at bus frequency and therefore could vary and currently
|
||||
* uHAL can't handle that.
|
||||
*
|
||||
*/
|
||||
|
||||
#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
|
||||
#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
|
||||
#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
|
||||
|
||||
#define MAX_TIMER 2
|
||||
#define MAX_PERIOD 699050
|
||||
#define TICKS_PER_uSEC 24
|
||||
|
||||
/*
|
||||
* These are useconds NOT ticks.
|
||||
*
|
||||
*/
|
||||
#define mSEC_1 1000
|
||||
#define mSEC_5 (mSEC_1 * 5)
|
||||
#define mSEC_10 (mSEC_1 * 10)
|
||||
#define mSEC_25 (mSEC_1 * 25)
|
||||
#define SEC_1 (mSEC_1 * 1000)
|
||||
|
||||
#define INTEGRATOR_CSR_BASE 0x10000000
|
||||
#define INTEGRATOR_CSR_SIZE 0x10000000
|
||||
|
||||
#endif
|
||||
|
||||
/* END */
|
||||
44
arch/arm/mach-integrator/include/mach/system.h
Normal file
44
arch/arm/mach-integrator/include/mach/system.h
Normal file
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* arch/arm/mach-integrator/include/mach/system.h
|
||||
*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
* Copyright (C) 2000 Deep Blue Solutions Ltd
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <mach/cm.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
/*
|
||||
* This should do all the clock switching
|
||||
* and wait for interrupt tricks
|
||||
*/
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
/*
|
||||
* To reset, we hit the on-board reset register
|
||||
* in the system FPGA
|
||||
*/
|
||||
cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
|
||||
}
|
||||
|
||||
#endif
|
||||
26
arch/arm/mach-integrator/include/mach/timex.h
Normal file
26
arch/arm/mach-integrator/include/mach/timex.h
Normal file
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* arch/arm/mach-integrator/include/mach/timex.h
|
||||
*
|
||||
* Integrator architecture timex specifications
|
||||
*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* ??
|
||||
*/
|
||||
#define CLOCK_TICK_RATE (50000000 / 16)
|
||||
50
arch/arm/mach-integrator/include/mach/uncompress.h
Normal file
50
arch/arm/mach-integrator/include/mach/uncompress.h
Normal file
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* arch/arm/mach-integrator/include/mach/uncompress.h
|
||||
*
|
||||
* Copyright (C) 1999 ARM Limited
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define AMBA_UART_DR (*(volatile unsigned char *)0x16000000)
|
||||
#define AMBA_UART_LCRH (*(volatile unsigned char *)0x16000008)
|
||||
#define AMBA_UART_LCRM (*(volatile unsigned char *)0x1600000c)
|
||||
#define AMBA_UART_LCRL (*(volatile unsigned char *)0x16000010)
|
||||
#define AMBA_UART_CR (*(volatile unsigned char *)0x16000014)
|
||||
#define AMBA_UART_FR (*(volatile unsigned char *)0x16000018)
|
||||
|
||||
/*
|
||||
* This does not append a newline
|
||||
*/
|
||||
static void putc(int c)
|
||||
{
|
||||
while (AMBA_UART_FR & (1 << 5))
|
||||
barrier();
|
||||
|
||||
AMBA_UART_DR = c;
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
while (AMBA_UART_FR & (1 << 3))
|
||||
barrier();
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup()
|
||||
|
||||
#define arch_decomp_wdog()
|
||||
20
arch/arm/mach-integrator/include/mach/vmalloc.h
Normal file
20
arch/arm/mach-integrator/include/mach/vmalloc.h
Normal file
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* arch/arm/mach-integrator/include/mach/vmalloc.h
|
||||
*
|
||||
* Copyright (C) 2000 Russell King.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
|
||||
Reference in New Issue
Block a user