Merge branch 'mlx5-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux
Merge mlx5-next patches needed for upcoming mlx5 software steering. 1) Alex adds HW bits and definitions required for SW steering 2) Ariel moves device memory management to mlx5_core (From mlx5_ib) 3) Maor, Cleanups and fixups for eswitch mode and RoCE 4) Mark, Set only stag for match untagged packets Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
This commit is contained in:
@@ -1162,6 +1162,9 @@ enum mlx5_qcam_feature_groups {
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#define MLX5_CAP_FLOWTABLE(mdev, cap) \
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MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
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#define MLX5_CAP64_FLOWTABLE(mdev, cap) \
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MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
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#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
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MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
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@@ -1225,6 +1228,10 @@ enum mlx5_qcam_feature_groups {
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MLX5_GET(e_switch_cap, \
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mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
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#define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
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MLX5_GET64(flow_table_eswitch_cap, \
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(mdev)->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
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#define MLX5_CAP_ESW_MAX(mdev, cap) \
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MLX5_GET(e_switch_cap, \
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mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
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@@ -626,6 +626,11 @@ struct mlx5e_resources {
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struct mlx5_sq_bfreg bfreg;
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};
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enum mlx5_sw_icm_type {
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MLX5_SW_ICM_TYPE_STEERING,
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MLX5_SW_ICM_TYPE_HEADER_MODIFY,
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};
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#define MLX5_MAX_RESERVED_GIDS 8
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struct mlx5_rsvd_gids {
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@@ -657,11 +662,15 @@ struct mlx5_clock {
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struct mlx5_pps pps_info;
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};
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struct mlx5_dm;
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struct mlx5_fw_tracer;
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struct mlx5_vxlan;
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struct mlx5_geneve;
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struct mlx5_hv_vhca;
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#define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
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#define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
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struct mlx5_core_dev {
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struct device *device;
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enum mlx5_coredev_type coredev_type;
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@@ -695,6 +704,7 @@ struct mlx5_core_dev {
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atomic_t num_qps;
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u32 issi;
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struct mlx5e_resources mlx5e_res;
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struct mlx5_dm *dm;
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struct mlx5_vxlan *vxlan;
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struct mlx5_geneve *geneve;
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struct {
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@@ -1078,6 +1088,10 @@ int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
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size_t *offsets);
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struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
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void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
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int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
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u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id);
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int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
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u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
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#ifdef CONFIG_MLX5_CORE_IPOIB
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struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
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@@ -60,7 +60,6 @@ void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
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struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
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u16 vport_num);
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void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type);
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u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw);
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struct mlx5_flow_handle *
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mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw,
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u16 vport_num, u32 sqn);
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@@ -74,7 +73,14 @@ mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);
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bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw);
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u32 mlx5_eswitch_get_vport_metadata_for_match(const struct mlx5_eswitch *esw,
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u16 vport_num);
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u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw);
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#else /* CONFIG_MLX5_ESWITCH */
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static inline u8 mlx5_eswitch_mode(struct mlx5_eswitch *esw)
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{
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return MLX5_ESWITCH_NONE;
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}
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static inline enum devlink_eswitch_encap_mode
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mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev)
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{
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@@ -282,6 +282,7 @@ enum {
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MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
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MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
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MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
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MLX5_CMD_OP_SYNC_STEERING = 0xb00,
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MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
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MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
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MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
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@@ -485,7 +486,11 @@ union mlx5_ifc_gre_key_bits {
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};
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struct mlx5_ifc_fte_match_set_misc_bits {
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u8 reserved_at_0[0x8];
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u8 gre_c_present[0x1];
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u8 reserved_auto1[0x1];
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u8 gre_k_present[0x1];
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u8 gre_s_present[0x1];
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u8 source_vhca_port[0x4];
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u8 source_sqn[0x18];
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u8 source_eswitch_owner_vhca_id[0x10];
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@@ -565,12 +570,38 @@ struct mlx5_ifc_fte_match_set_misc2_bits {
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u8 metadata_reg_a[0x20];
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u8 reserved_at_1a0[0x60];
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u8 metadata_reg_b[0x20];
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u8 reserved_at_1c0[0x40];
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};
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struct mlx5_ifc_fte_match_set_misc3_bits {
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u8 reserved_at_0[0x120];
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u8 inner_tcp_seq_num[0x20];
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u8 outer_tcp_seq_num[0x20];
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u8 inner_tcp_ack_num[0x20];
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u8 outer_tcp_ack_num[0x20];
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u8 reserved_at_80[0x8];
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u8 outer_vxlan_gpe_vni[0x18];
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u8 outer_vxlan_gpe_next_protocol[0x8];
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u8 outer_vxlan_gpe_flags[0x8];
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u8 reserved_at_b0[0x10];
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u8 icmp_header_data[0x20];
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u8 icmpv6_header_data[0x20];
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u8 icmp_type[0x8];
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u8 icmp_code[0x8];
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u8 icmpv6_type[0x8];
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u8 icmpv6_code[0x8];
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u8 geneve_tlv_option_0_data[0x20];
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u8 reserved_at_140[0xc0];
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};
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@@ -666,7 +697,15 @@ struct mlx5_ifc_flow_table_nic_cap_bits {
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struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
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u8 reserved_at_e00[0x7200];
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u8 reserved_at_e00[0x1200];
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u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
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u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
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u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
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u8 reserved_at_20c0[0x5f40];
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};
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enum {
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@@ -698,7 +737,17 @@ struct mlx5_ifc_flow_table_eswitch_cap_bits {
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struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
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u8 reserved_at_800[0x7800];
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u8 reserved_at_800[0x1000];
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u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
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u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
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u8 sw_steering_uplink_icm_address_rx[0x40];
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u8 sw_steering_uplink_icm_address_tx[0x40];
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u8 reserved_at_1900[0x6700];
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};
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enum {
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@@ -849,6 +898,25 @@ struct mlx5_ifc_roce_cap_bits {
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u8 reserved_at_100[0x700];
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};
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struct mlx5_ifc_sync_steering_in_bits {
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u8 opcode[0x10];
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u8 uid[0x10];
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u8 reserved_at_20[0x10];
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u8 op_mod[0x10];
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u8 reserved_at_40[0xc0];
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};
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struct mlx5_ifc_sync_steering_out_bits {
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u8 status[0x8];
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u8 reserved_at_8[0x18];
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u8 syndrome[0x20];
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u8 reserved_at_40[0x40];
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};
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struct mlx5_ifc_device_mem_cap_bits {
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u8 memic[0x1];
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u8 reserved_at_1[0x1f];
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@@ -1041,6 +1109,12 @@ enum {
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MLX5_CAP_UMR_FENCE_NONE = 0x2,
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};
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enum {
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MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
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MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
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MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
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};
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enum {
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MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
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MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
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@@ -1414,7 +1488,14 @@ struct mlx5_ifc_cmd_hca_cap_bits {
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u8 reserved_at_6c0[0x4];
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u8 flex_parser_id_geneve_tlv_option_0[0x4];
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u8 reserved_at_6c8[0x28];
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u8 flex_parser_id_icmp_dw1[0x4];
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u8 flex_parser_id_icmp_dw0[0x4];
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u8 flex_parser_id_icmpv6_dw1[0x4];
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u8 flex_parser_id_icmpv6_dw0[0x4];
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u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
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u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
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u8 reserved_at_6e0[0x10];
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u8 sf_base_id[0x10];
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u8 reserved_at_700[0x80];
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@@ -2652,6 +2733,7 @@ union mlx5_ifc_hca_cap_union_bits {
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struct mlx5_ifc_debug_cap_bits debug_cap;
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struct mlx5_ifc_fpga_cap_bits fpga_cap;
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struct mlx5_ifc_tls_cap_bits tls_cap;
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struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
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u8 reserved_at_0[0x8000];
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};
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@@ -3255,7 +3337,11 @@ struct mlx5_ifc_esw_vport_context_bits {
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u8 cvlan_pcp[0x3];
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u8 cvlan_id[0xc];
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u8 reserved_at_60[0x7a0];
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u8 reserved_at_60[0x720];
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u8 sw_steering_vport_icm_address_rx[0x40];
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u8 sw_steering_vport_icm_address_tx[0x40];
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};
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enum {
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@@ -4941,7 +5027,87 @@ struct mlx5_ifc_query_hca_cap_in_bits {
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u8 reserved_at_20[0x10];
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u8 op_mod[0x10];
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u8 reserved_at_40[0x40];
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u8 other_function[0x1];
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u8 reserved_at_41[0xf];
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u8 function_id[0x10];
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u8 reserved_at_60[0x20];
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};
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struct mlx5_ifc_other_hca_cap_bits {
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u8 roce[0x1];
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u8 reserved_0[0x27f];
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};
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struct mlx5_ifc_query_other_hca_cap_out_bits {
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u8 status[0x8];
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u8 reserved_0[0x18];
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u8 syndrome[0x20];
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u8 reserved_1[0x40];
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struct mlx5_ifc_other_hca_cap_bits other_capability;
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};
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struct mlx5_ifc_query_other_hca_cap_in_bits {
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u8 opcode[0x10];
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u8 reserved_0[0x10];
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u8 reserved_1[0x10];
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u8 op_mod[0x10];
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u8 reserved_2[0x10];
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u8 function_id[0x10];
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u8 reserved_3[0x20];
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};
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struct mlx5_ifc_modify_other_hca_cap_out_bits {
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u8 status[0x8];
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u8 reserved_0[0x18];
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u8 syndrome[0x20];
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u8 reserved_1[0x40];
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};
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struct mlx5_ifc_modify_other_hca_cap_in_bits {
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u8 opcode[0x10];
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u8 reserved_0[0x10];
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u8 reserved_1[0x10];
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u8 op_mod[0x10];
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u8 reserved_2[0x10];
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u8 function_id[0x10];
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u8 field_select[0x20];
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struct mlx5_ifc_other_hca_cap_bits other_capability;
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};
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struct mlx5_ifc_flow_table_context_bits {
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u8 reformat_en[0x1];
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u8 decap_en[0x1];
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u8 sw_owner[0x1];
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u8 termination_table[0x1];
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u8 table_miss_action[0x4];
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u8 level[0x8];
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u8 reserved_at_10[0x8];
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u8 log_size[0x8];
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u8 reserved_at_20[0x8];
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u8 table_miss_id[0x18];
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u8 reserved_at_40[0x8];
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u8 lag_master_next_table_id[0x18];
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u8 reserved_at_60[0x60];
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u8 sw_owner_icm_root_1[0x40];
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u8 sw_owner_icm_root_0[0x40];
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};
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struct mlx5_ifc_query_flow_table_out_bits {
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@@ -4952,12 +5118,7 @@ struct mlx5_ifc_query_flow_table_out_bits {
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u8 reserved_at_40[0x80];
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u8 reserved_at_c0[0x8];
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u8 level[0x8];
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u8 reserved_at_d0[0x8];
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u8 log_size[0x8];
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u8 reserved_at_e0[0x120];
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struct mlx5_ifc_flow_table_context_bits flow_table_context;
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};
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struct mlx5_ifc_query_flow_table_in_bits {
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@@ -5227,7 +5388,7 @@ struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
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u8 reserved_at_60[0x20];
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};
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enum {
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enum mlx5_reformat_ctx_type {
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MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
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MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
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MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
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@@ -5323,7 +5484,16 @@ enum {
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MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
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MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
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MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
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MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
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MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
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MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
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MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
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MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
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MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
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MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
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MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
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MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
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MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
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};
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struct mlx5_ifc_alloc_modify_header_context_out_bits {
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@@ -7371,35 +7541,26 @@ struct mlx5_ifc_create_mkey_in_bits {
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||||
u8 klm_pas_mtt[0][0x20];
|
||||
};
|
||||
|
||||
enum {
|
||||
MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
|
||||
MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
|
||||
MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
|
||||
MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
|
||||
MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
|
||||
MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
|
||||
MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
|
||||
};
|
||||
|
||||
struct mlx5_ifc_create_flow_table_out_bits {
|
||||
u8 status[0x8];
|
||||
u8 reserved_at_8[0x18];
|
||||
u8 icm_address_63_40[0x18];
|
||||
|
||||
u8 syndrome[0x20];
|
||||
|
||||
u8 reserved_at_40[0x8];
|
||||
u8 icm_address_39_32[0x8];
|
||||
u8 table_id[0x18];
|
||||
|
||||
u8 reserved_at_60[0x20];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_flow_table_context_bits {
|
||||
u8 reformat_en[0x1];
|
||||
u8 decap_en[0x1];
|
||||
u8 reserved_at_2[0x1];
|
||||
u8 termination_table[0x1];
|
||||
u8 table_miss_action[0x4];
|
||||
u8 level[0x8];
|
||||
u8 reserved_at_10[0x8];
|
||||
u8 log_size[0x8];
|
||||
|
||||
u8 reserved_at_20[0x8];
|
||||
u8 table_miss_id[0x18];
|
||||
|
||||
u8 reserved_at_40[0x8];
|
||||
u8 lag_master_next_table_id[0x18];
|
||||
|
||||
u8 reserved_at_60[0xe0];
|
||||
u8 icm_address_31_0[0x20];
|
||||
};
|
||||
|
||||
struct mlx5_ifc_create_flow_table_in_bits {
|
||||
|
Reference in New Issue
Block a user