xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[SPARC64]: Fix TLB context allocation with SMT style shared TLBs.

Browse Source 
The context allocation scheme we use depends upon there being a 1<-->1
mapping from cpu to physical TLB for correctness.  Chips like Niagara
break this assumption.

So what we do is notify all cpus with a cross call when the context
version number changes, and if necessary this makes them allocate
a valid context for the address space they are running at the time.

Stress tested with make -j1024, make -j2048, and make -j4096 kernel
builds on a 32-strand, 8 core, T2000 with 16GB of ram.

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2006-02-23 14:19:28 -08:00
committed by David S. Miller
parent 074d82cf68
commit a0663a79ad
4 changed files with 50 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
include/asm-sparc64/mmu.h
View File

@@ -102,6 +102,7 @@ extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte
extern void tsb_flush(unsigned long ent, unsigned long tag);
typedef struct {
spinlock_t lock;
unsigned long sparc64_ctx_val;
struct tsb *tsb;
unsigned long tsb_rss_limit;