Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: sunxi-ng: Fix wrong reset register offsets clk: sunxi-ng: nk: Make ccu_nk_find_best static clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock clk: sunxi: Fix return value check in sun8i_a23_mbus_setup() clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
Este cometimento está contido em:
@@ -73,7 +73,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
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SUN4I_PLL2_PRE_DIV_WIDTH,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&sun4i_a10_pll2_lock);
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if (!prediv_clk) {
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if (IS_ERR(prediv_clk)) {
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pr_err("Couldn't register the prediv clock\n");
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goto err_free_array;
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}
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@@ -106,7 +106,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
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&mult->hw, &clk_multiplier_ops,
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&gate->hw, &clk_gate_ops,
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CLK_SET_RATE_PARENT);
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if (!base_clk) {
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if (IS_ERR(base_clk)) {
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pr_err("Couldn't register the base multiplier clock\n");
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goto err_free_multiplier;
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}
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@@ -48,7 +48,7 @@ static void __init sun8i_a23_mbus_setup(struct device_node *node)
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return;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (!reg) {
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if (IS_ERR(reg)) {
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pr_err("Could not get registers for sun8i-mbus-clk\n");
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goto err_free_parents;
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}
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