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MIPS: Loongson1B: Some updates/fixes for LS1B

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- Add DMA device
- Add NAND device
- Add GPIO device
- Add LED device
- Update the defconfig and rename it to loongson1b_defconfig
- Fix ioremap size
- Other minor fixes

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vinod Koul <vinod.koul@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Brian Norris <computersforpeace@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-clk@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: dmaengine@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-mtd@lists.infradead.org
Patchwork: https://patchwork.linux-mips.org/patch/13033/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Kelvin Cheung
2016-04-06 20:34:54 +08:00
committed by Ralf Baechle
parent 0d61ed17dd
commit 9ec88b60cb
15 changed files with 340 additions and 104 deletions
Download Patch File Download Diff File Expand all files Collapse all files

105
arch/mips/loongson32/common/platform.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
* Copyright (c) 2011-2016 Zhang, Keguang <keguang.zhang@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -10,14 +10,17 @@
#include <linux/clk.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/mtd/partitions.h>
#include <linux/sizes.h>
#include <linux/phy.h>
#include <linux/serial_8250.h>
#include <linux/stmmac.h>
#include <linux/usb/ehci_pdriver.h>
#include <asm-generic/sizes.h>
#include <cpufreq.h>
#include <loongson1.h>
#include <cpufreq.h>
#include <dma.h>
#include <nand.h>
/* 8250/16550 compatible UART */
#define LS1X_UART(_id) \
@@ -45,7 +48,7 @@ struct platform_device ls1x_uart_pdev = {
},
};
void __init ls1x_serial_setup(struct platform_device *pdev)
void __init ls1x_serial_set_uartclk(struct platform_device *pdev)
{
struct clk *clk;
struct plat_serial8250_port *p;
@@ -77,6 +80,42 @@ struct platform_device ls1x_cpufreq_pdev = {
},
};
/* DMA */
static struct resource ls1x_dma_resources[] = {
[0] = {
.start = LS1X_DMAC_BASE,
.end = LS1X_DMAC_BASE + SZ_4 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = LS1X_DMA0_IRQ,
.end = LS1X_DMA0_IRQ,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = LS1X_DMA1_IRQ,
.end = LS1X_DMA1_IRQ,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = LS1X_DMA2_IRQ,
.end = LS1X_DMA2_IRQ,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device ls1x_dma_pdev = {
.name = "ls1x-dma",
.id = -1,
.num_resources = ARRAY_SIZE(ls1x_dma_resources),
.resource = ls1x_dma_resources,
};
void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata)
{
ls1x_dma_pdev.dev.platform_data = pdata;
}
/* Synopsys Ethernet GMAC */
static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
.phy_mask = 0,
@@ -198,6 +237,64 @@ struct platform_device ls1x_eth1_pdev = {
},
};
/* GPIO */
static struct resource ls1x_gpio0_resources[] = {
[0] = {
.start = LS1X_GPIO0_BASE,
.end = LS1X_GPIO0_BASE + SZ_4 - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device ls1x_gpio0_pdev = {
.name = "ls1x-gpio",
.id = 0,
.num_resources = ARRAY_SIZE(ls1x_gpio0_resources),
.resource = ls1x_gpio0_resources,
};
static struct resource ls1x_gpio1_resources[] = {
[0] = {
.start = LS1X_GPIO1_BASE,
.end = LS1X_GPIO1_BASE + SZ_4 - 1,
.flags = IORESOURCE_MEM,
},
};
struct platform_device ls1x_gpio1_pdev = {
.name = "ls1x-gpio",
.id = 1,
.num_resources = ARRAY_SIZE(ls1x_gpio1_resources),
.resource = ls1x_gpio1_resources,
};
/* NAND Flash */
static struct resource ls1x_nand_resources[] = {
[0] = {
.start = LS1X_NAND_BASE,
.end = LS1X_NAND_BASE + SZ_32 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
/* DMA channel 0 is dedicated to NAND */
.start = LS1X_DMA_CHANNEL0,
.end = LS1X_DMA_CHANNEL0,
.flags = IORESOURCE_DMA,
},
};
struct platform_device ls1x_nand_pdev = {
.name = "ls1x-nand",
.id = -1,
.num_resources = ARRAY_SIZE(ls1x_nand_resources),
.resource = ls1x_nand_resources,
};
void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata)
{
ls1x_nand_pdev.dev.platform_data = pdata;
}
/* USB EHCI */
static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);

13
arch/mips/loongson32/common/reset.c
View File

@@ -9,12 +9,13 @@
#include <linux/io.h>
#include <linux/pm.h>
#include <linux/sizes.h>
#include <asm/idle.h>
#include <asm/reboot.h>
#include <loongson1.h>
static void __iomem *wdt_base;
static void __iomem *wdt_reg_base;
static void ls1x_halt(void)
{
@@ -26,9 +27,9 @@ static void ls1x_halt(void)
static void ls1x_restart(char *command)
{
__raw_writel(0x1, wdt_base + WDT_EN);
__raw_writel(0x1, wdt_base + WDT_TIMER);
__raw_writel(0x1, wdt_base + WDT_SET);
__raw_writel(0x1, wdt_reg_base + WDT_EN);
__raw_writel(0x1, wdt_reg_base + WDT_TIMER);
__raw_writel(0x1, wdt_reg_base + WDT_SET);
ls1x_halt();
}
@@ -40,8 +41,8 @@ static void ls1x_power_off(void)
static int __init ls1x_reboot_setup(void)
{
wdt_base = ioremap_nocache(LS1X_WDT_BASE, 0x0f);
if (!wdt_base)
wdt_reg_base = ioremap_nocache(LS1X_WDT_BASE, (SZ_4 + SZ_8));
if (!wdt_reg_base)
panic("Failed to remap watchdog registers");
_machine_restart = ls1x_restart;

27
arch/mips/loongson32/common/time.c
View File

@@ -9,6 +9,7 @@
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/sizes.h>
#include <asm/time.h>
#include <loongson1.h>
@@ -35,25 +36,25 @@
DEFINE_RAW_SPINLOCK(ls1x_timer_lock);
static void __iomem *timer_base;
static void __iomem *timer_reg_base;
static uint32_t ls1x_jiffies_per_tick;
static inline void ls1x_pwmtimer_set_period(uint32_t period)
{
__raw_writel(period, timer_base + PWM_HRC);
__raw_writel(period, timer_base + PWM_LRC);
__raw_writel(period, timer_reg_base + PWM_HRC);
__raw_writel(period, timer_reg_base + PWM_LRC);
}
static inline void ls1x_pwmtimer_restart(void)
{
__raw_writel(0x0, timer_base + PWM_CNT);
__raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL);
__raw_writel(0x0, timer_reg_base + PWM_CNT);
__raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
}
void __init ls1x_pwmtimer_init(void)
{
timer_base = ioremap(LS1X_TIMER_BASE, 0xf);
if (!timer_base)
timer_reg_base = ioremap_nocache(LS1X_TIMER_BASE, SZ_16);
if (!timer_reg_base)
panic("Failed to remap timer registers");
ls1x_jiffies_per_tick = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ);
@@ -86,7 +87,7 @@ static cycle_t ls1x_clocksource_read(struct clocksource *cs)
*/
jifs = jiffies;
/* read the count */
count = __raw_readl(timer_base + PWM_CNT);
count = __raw_readl(timer_reg_base + PWM_CNT);
/*
* It's possible for count to appear to go the wrong way for this
@@ -131,7 +132,7 @@ static int ls1x_clockevent_set_state_periodic(struct clock_event_device *cd)
raw_spin_lock(&ls1x_timer_lock);
ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick);
ls1x_pwmtimer_restart();
__raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL);
__raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
raw_spin_unlock(&ls1x_timer_lock);
return 0;
@@ -140,7 +141,7 @@ static int ls1x_clockevent_set_state_periodic(struct clock_event_device *cd)
static int ls1x_clockevent_tick_resume(struct clock_event_device *cd)
{
raw_spin_lock(&ls1x_timer_lock);
__raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL);
__raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL);
raw_spin_unlock(&ls1x_timer_lock);
return 0;
@@ -149,8 +150,8 @@ static int ls1x_clockevent_tick_resume(struct clock_event_device *cd)
static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *cd)
{
raw_spin_lock(&ls1x_timer_lock);
__raw_writel(__raw_readl(timer_base + PWM_CTRL) & ~CNT_EN,
timer_base + PWM_CTRL);
__raw_writel(__raw_readl(timer_reg_base + PWM_CTRL) & ~CNT_EN,
timer_reg_base + PWM_CTRL);
raw_spin_unlock(&ls1x_timer_lock);
return 0;
@@ -220,7 +221,7 @@ void __init plat_time_init(void)
#ifdef CONFIG_CEVT_CSRC_LS1X
/* setup LS1X PWM timer */
clk = clk_get(NULL, "ls1x_pwmtimer");
clk = clk_get(NULL, "ls1x-pwmtimer");
if (IS_ERR(clk))
panic("unable to get timer clock, err=%ld", PTR_ERR(clk));