MIPS: Loongson1B: Some updates/fixes for LS1B
- Add DMA device - Add NAND device - Add GPIO device - Add LED device - Update the defconfig and rename it to loongson1b_defconfig - Fix ioremap size - Other minor fixes Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Richard Weinberger <richard@nod.at> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Cc: linux-pm@vger.kernel.org Cc: dmaengine@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: linux-mtd@lists.infradead.org Patchwork: https://patchwork.linux-mips.org/patch/13033/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Kelvin Cheung
committed by
Ralf Baechle
Ralf Baechle
parent
0d61ed17dd
commit
9ec88b60cb
@@ -9,7 +9,6 @@
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON32_CPUFREQ_H
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#define __ASM_MACH_LOONGSON32_CPUFREQ_H
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25
arch/mips/include/asm/mach-loongson32/dma.h
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25
arch/mips/include/asm/mach-loongson32/dma.h
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@@ -0,0 +1,25 @@
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/*
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* Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Loongson 1 NAND platform support.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON32_DMA_H
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#define __ASM_MACH_LOONGSON32_DMA_H
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#define LS1X_DMA_CHANNEL0 0
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#define LS1X_DMA_CHANNEL1 1
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#define LS1X_DMA_CHANNEL2 2
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struct plat_ls1x_dma {
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int nr_channels;
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};
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extern struct plat_ls1x_dma ls1b_dma_pdata;
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#endif /* __ASM_MACH_LOONGSON32_DMA_H */
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@@ -9,7 +9,6 @@
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON32_IRQ_H
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#define __ASM_MACH_LOONGSON32_IRQ_H
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@@ -9,7 +9,6 @@
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
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#define __ASM_MACH_LOONGSON32_LOONGSON1_H
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@@ -18,6 +17,9 @@
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/* Loongson 1 Register Bases */
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#define LS1X_MUX_BASE 0x1fd00420
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#define LS1X_INTC_BASE 0x1fd01040
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#define LS1X_GPIO0_BASE 0x1fd010c0
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#define LS1X_GPIO1_BASE 0x1fd010c4
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#define LS1X_DMAC_BASE 0x1fd01160
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#define LS1X_EHCI_BASE 0x1fe00000
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#define LS1X_OHCI_BASE 0x1fe08000
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#define LS1X_GMAC0_BASE 0x1fe10000
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30
arch/mips/include/asm/mach-loongson32/nand.h
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30
arch/mips/include/asm/mach-loongson32/nand.h
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@@ -0,0 +1,30 @@
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/*
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* Copyright (c) 2015 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Loongson 1 NAND platform support.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON32_NAND_H
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#define __ASM_MACH_LOONGSON32_NAND_H
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#include <linux/dmaengine.h>
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#include <linux/mtd/partitions.h>
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struct plat_ls1x_nand {
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struct mtd_partition *parts;
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unsigned int nr_parts;
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int hold_cycle;
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int wait_cycle;
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};
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extern struct plat_ls1x_nand ls1b_nand_pdata;
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bool ls1x_dma_filter_fn(struct dma_chan *chan, void *param);
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#endif /* __ASM_MACH_LOONGSON32_NAND_H */
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@@ -7,20 +7,28 @@
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON32_PLATFORM_H
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#define __ASM_MACH_LOONGSON32_PLATFORM_H
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#include <linux/platform_device.h>
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#include <dma.h>
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#include <nand.h>
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extern struct platform_device ls1x_uart_pdev;
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extern struct platform_device ls1x_cpufreq_pdev;
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extern struct platform_device ls1x_dma_pdev;
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extern struct platform_device ls1x_eth0_pdev;
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extern struct platform_device ls1x_eth1_pdev;
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extern struct platform_device ls1x_ehci_pdev;
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extern struct platform_device ls1x_gpio0_pdev;
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extern struct platform_device ls1x_gpio1_pdev;
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extern struct platform_device ls1x_nand_pdev;
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extern struct platform_device ls1x_rtc_pdev;
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extern void __init ls1x_clk_init(void);
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extern void __init ls1x_serial_setup(struct platform_device *pdev);
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void __init ls1x_clk_init(void);
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void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata);
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void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata);
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void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
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#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */
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@@ -19,18 +19,18 @@
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#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
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/* Clock PLL Divisor Register Bits */
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#define DIV_DC_EN (0x1 << 31)
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#define DIV_DC_RST (0x1 << 30)
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#define DIV_CPU_EN (0x1 << 25)
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#define DIV_CPU_RST (0x1 << 24)
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#define DIV_DDR_EN (0x1 << 19)
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#define DIV_DDR_RST (0x1 << 18)
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#define RST_DC_EN (0x1 << 5)
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#define RST_DC (0x1 << 4)
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#define RST_DDR_EN (0x1 << 3)
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#define RST_DDR (0x1 << 2)
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#define RST_CPU_EN (0x1 << 1)
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#define RST_CPU 0x1
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#define DIV_DC_EN BIT(31)
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#define DIV_DC_RST BIT(30)
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#define DIV_CPU_EN BIT(25)
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#define DIV_CPU_RST BIT(24)
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#define DIV_DDR_EN BIT(19)
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#define DIV_DDR_RST BIT(18)
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#define RST_DC_EN BIT(5)
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#define RST_DC BIT(4)
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#define RST_DDR_EN BIT(3)
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#define RST_DDR BIT(2)
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#define RST_CPU_EN BIT(1)
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#define RST_CPU BIT(0)
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#define DIV_DC_SHIFT 26
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#define DIV_CPU_SHIFT 20
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@@ -19,49 +19,49 @@
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#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
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/* MUX CTRL0 Register Bits */
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#define UART0_USE_PWM23 (0x1 << 28)
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#define UART0_USE_PWM01 (0x1 << 27)
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#define UART1_USE_LCD0_5_6_11 (0x1 << 26)
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#define I2C2_USE_CAN1 (0x1 << 25)
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#define I2C1_USE_CAN0 (0x1 << 24)
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#define NAND3_USE_UART5 (0x1 << 23)
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#define NAND3_USE_UART4 (0x1 << 22)
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#define NAND3_USE_UART1_DAT (0x1 << 21)
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#define NAND3_USE_UART1_CTS (0x1 << 20)
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#define NAND3_USE_PWM23 (0x1 << 19)
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#define NAND3_USE_PWM01 (0x1 << 18)
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#define NAND2_USE_UART5 (0x1 << 17)
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#define NAND2_USE_UART4 (0x1 << 16)
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#define NAND2_USE_UART1_DAT (0x1 << 15)
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#define NAND2_USE_UART1_CTS (0x1 << 14)
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#define NAND2_USE_PWM23 (0x1 << 13)
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#define NAND2_USE_PWM01 (0x1 << 12)
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#define NAND1_USE_UART5 (0x1 << 11)
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#define NAND1_USE_UART4 (0x1 << 10)
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#define NAND1_USE_UART1_DAT (0x1 << 9)
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#define NAND1_USE_UART1_CTS (0x1 << 8)
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#define NAND1_USE_PWM23 (0x1 << 7)
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#define NAND1_USE_PWM01 (0x1 << 6)
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#define GMAC1_USE_UART1 (0x1 << 4)
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#define GMAC1_USE_UART0 (0x1 << 3)
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#define LCD_USE_UART0_DAT (0x1 << 2)
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#define LCD_USE_UART15 (0x1 << 1)
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#define LCD_USE_UART0 0x1
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#define UART0_USE_PWM23 BIT(28)
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#define UART0_USE_PWM01 BIT(27)
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#define UART1_USE_LCD0_5_6_11 BIT(26)
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#define I2C2_USE_CAN1 BIT(25)
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#define I2C1_USE_CAN0 BIT(24)
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#define NAND3_USE_UART5 BIT(23)
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#define NAND3_USE_UART4 BIT(22)
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#define NAND3_USE_UART1_DAT BIT(21)
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#define NAND3_USE_UART1_CTS BIT(20)
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#define NAND3_USE_PWM23 BIT(19)
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#define NAND3_USE_PWM01 BIT(18)
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#define NAND2_USE_UART5 BIT(17)
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#define NAND2_USE_UART4 BIT(16)
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#define NAND2_USE_UART1_DAT BIT(15)
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#define NAND2_USE_UART1_CTS BIT(14)
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#define NAND2_USE_PWM23 BIT(13)
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#define NAND2_USE_PWM01 BIT(12)
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#define NAND1_USE_UART5 BIT(11)
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#define NAND1_USE_UART4 BIT(10)
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#define NAND1_USE_UART1_DAT BIT(9)
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#define NAND1_USE_UART1_CTS BIT(8)
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#define NAND1_USE_PWM23 BIT(7)
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#define NAND1_USE_PWM01 BIT(6)
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#define GMAC1_USE_UART1 BIT(4)
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#define GMAC1_USE_UART0 BIT(3)
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#define LCD_USE_UART0_DAT BIT(2)
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#define LCD_USE_UART15 BIT(1)
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#define LCD_USE_UART0 BIT(0)
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/* MUX CTRL1 Register Bits */
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#define USB_RESET (0x1 << 31)
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#define SPI1_CS_USE_PWM01 (0x1 << 24)
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#define SPI1_USE_CAN (0x1 << 23)
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#define DISABLE_DDR_CONFSPACE (0x1 << 20)
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#define DDR32TO16EN (0x1 << 16)
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#define GMAC1_SHUT (0x1 << 13)
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#define GMAC0_SHUT (0x1 << 12)
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#define USB_SHUT (0x1 << 11)
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#define UART1_3_USE_CAN1 (0x1 << 5)
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#define UART1_2_USE_CAN0 (0x1 << 4)
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#define GMAC1_USE_TXCLK (0x1 << 3)
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#define GMAC0_USE_TXCLK (0x1 << 2)
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#define GMAC1_USE_PWM23 (0x1 << 1)
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#define GMAC0_USE_PWM01 0x1
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#define USB_RESET BIT(31)
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#define SPI1_CS_USE_PWM01 BIT(24)
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#define SPI1_USE_CAN BIT(23)
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#define DISABLE_DDR_CONFSPACE BIT(20)
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#define DDR32TO16EN BIT(16)
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#define GMAC1_SHUT BIT(13)
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#define GMAC0_SHUT BIT(12)
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#define USB_SHUT BIT(11)
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#define UART1_3_USE_CAN1 BIT(5)
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#define UART1_2_USE_CAN0 BIT(4)
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#define GMAC1_USE_TXCLK BIT(3)
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#define GMAC0_USE_TXCLK BIT(2)
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#define GMAC1_USE_PWM23 BIT(1)
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#define GMAC0_USE_PWM01 BIT(0)
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#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */
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@@ -19,11 +19,11 @@
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#define PWM_CTRL 0xc
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/* PWM Control Register Bits */
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#define CNT_RST (0x1 << 7)
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#define INT_SR (0x1 << 6)
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#define INT_EN (0x1 << 5)
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#define PWM_SINGLE (0x1 << 4)
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#define PWM_OE (0x1 << 3)
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#define CNT_EN 0x1
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#define CNT_RST BIT(7)
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#define INT_SR BIT(6)
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#define INT_EN BIT(5)
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#define PWM_SINGLE BIT(4)
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#define PWM_OE BIT(3)
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#define CNT_EN BIT(0)
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#endif /* __ASM_MACH_LOONGSON32_REGS_PWM_H */
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