Merge commit 'v2.6.28-rc5' into x86/cleanups
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@@ -1343,7 +1343,6 @@ static void __init acpi_process_madt(void)
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error = acpi_parse_madt_ioapic_entries();
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if (!error) {
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acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC;
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acpi_irq_balance_set(NULL);
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acpi_ioapic = 1;
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smp_found_config = 1;
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@@ -188,20 +188,6 @@ static void __init ati_bugs_contd(int num, int slot, int func)
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}
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#endif
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#ifdef CONFIG_DMAR
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static void __init intel_g33_dmar(int num, int slot, int func)
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{
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struct acpi_table_header *dmar_tbl;
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acpi_status status;
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status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
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if (ACPI_SUCCESS(status)) {
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printk(KERN_INFO "BIOS BUG: DMAR advertised on Intel G31/G33 chipset -- ignoring\n");
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dmar_disabled = 1;
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}
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}
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#endif
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#define QFLAG_APPLY_ONCE 0x1
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#define QFLAG_APPLIED 0x2
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#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
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@@ -225,10 +211,6 @@ static struct chipset early_qrk[] __initdata = {
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
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#ifdef CONFIG_DMAR
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{ PCI_VENDOR_ID_INTEL, 0x29c0,
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PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, intel_g33_dmar },
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#endif
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{}
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};
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@@ -322,7 +322,7 @@ static int hpet_next_event(unsigned long delta,
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* what we wrote hit the chip before we compare it to the
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* counter.
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*/
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WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt);
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WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt);
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return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
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}
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@@ -445,7 +445,7 @@ static int hpet_setup_irq(struct hpet_dev *dev)
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{
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if (request_irq(dev->irq, hpet_interrupt_handler,
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IRQF_SHARED|IRQF_NOBALANCING, dev->name, dev))
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IRQF_DISABLED|IRQF_NOBALANCING, dev->name, dev))
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return -1;
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disable_irq(dev->irq);
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@@ -128,7 +128,7 @@ static int kvm_register_clock(char *txt)
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}
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#ifdef CONFIG_X86_LOCAL_APIC
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static void kvm_setup_secondary_clock(void)
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static void __devinit kvm_setup_secondary_clock(void)
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{
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/*
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* Now that the first cpu already had this clocksource initialized,
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