usb: dwc2: Cleanup some checkpatch issues
This commmit is the result of running checkpatch --fix. The results were verified for correctness. Some of the fixes result in line over 80 char which we will fix manually later. The following is a summary of what was done by checkpatch: * Remove externs on function prototypes. * Replace symbolic permissions with octal. * Align code to open parens. * Replace 'unsigned' with 'unsigned int'. * Remove unneccessary blank lines. * Add blank lines after declarations. * Add spaces around operators. * Remove unnecessary spaces after casts. * Replace 'x == NULL' with '!x'. * Replace kzalloc() with kcalloc(). * Concatenate multi-line strings. * Use the BIT() macro. Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This commit is contained in:
John Youn
@@ -40,37 +40,37 @@
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#define HSOTG_REG(x) (x)
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#define GOTGCTL HSOTG_REG(0x000)
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#define GOTGCTL_CHIRPEN (1 << 27)
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#define GOTGCTL_CHIRPEN BIT(27)
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#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
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#define GOTGCTL_MULT_VALID_BC_SHIFT 22
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#define GOTGCTL_OTGVER (1 << 20)
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#define GOTGCTL_BSESVLD (1 << 19)
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#define GOTGCTL_ASESVLD (1 << 18)
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#define GOTGCTL_DBNC_SHORT (1 << 17)
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#define GOTGCTL_CONID_B (1 << 16)
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#define GOTGCTL_DBNCE_FLTR_BYPASS (1 << 15)
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#define GOTGCTL_DEVHNPEN (1 << 11)
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#define GOTGCTL_HSTSETHNPEN (1 << 10)
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#define GOTGCTL_HNPREQ (1 << 9)
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#define GOTGCTL_HSTNEGSCS (1 << 8)
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#define GOTGCTL_SESREQ (1 << 1)
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#define GOTGCTL_SESREQSCS (1 << 0)
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#define GOTGCTL_OTGVER BIT(20)
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#define GOTGCTL_BSESVLD BIT(19)
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#define GOTGCTL_ASESVLD BIT(18)
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#define GOTGCTL_DBNC_SHORT BIT(17)
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#define GOTGCTL_CONID_B BIT(16)
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#define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
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#define GOTGCTL_DEVHNPEN BIT(11)
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#define GOTGCTL_HSTSETHNPEN BIT(10)
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#define GOTGCTL_HNPREQ BIT(9)
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#define GOTGCTL_HSTNEGSCS BIT(8)
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#define GOTGCTL_SESREQ BIT(1)
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#define GOTGCTL_SESREQSCS BIT(0)
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#define GOTGINT HSOTG_REG(0x004)
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#define GOTGINT_DBNCE_DONE (1 << 19)
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#define GOTGINT_A_DEV_TOUT_CHG (1 << 18)
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#define GOTGINT_HST_NEG_DET (1 << 17)
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#define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9)
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#define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8)
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#define GOTGINT_SES_END_DET (1 << 2)
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#define GOTGINT_DBNCE_DONE BIT(19)
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#define GOTGINT_A_DEV_TOUT_CHG BIT(18)
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#define GOTGINT_HST_NEG_DET BIT(17)
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#define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
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#define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
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#define GOTGINT_SES_END_DET BIT(2)
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#define GAHBCFG HSOTG_REG(0x008)
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#define GAHBCFG_AHB_SINGLE (1 << 23)
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#define GAHBCFG_NOTI_ALL_DMA_WRIT (1 << 22)
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#define GAHBCFG_REM_MEM_SUPP (1 << 21)
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#define GAHBCFG_P_TXF_EMP_LVL (1 << 8)
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#define GAHBCFG_NP_TXF_EMP_LVL (1 << 7)
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#define GAHBCFG_DMA_EN (1 << 5)
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#define GAHBCFG_AHB_SINGLE BIT(23)
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#define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
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#define GAHBCFG_REM_MEM_SUPP BIT(21)
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#define GAHBCFG_P_TXF_EMP_LVL BIT(8)
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#define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
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#define GAHBCFG_DMA_EN BIT(5)
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#define GAHBCFG_HBSTLEN_MASK (0xf << 1)
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#define GAHBCFG_HBSTLEN_SHIFT 1
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#define GAHBCFG_HBSTLEN_SINGLE 0
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@@ -78,38 +78,38 @@
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#define GAHBCFG_HBSTLEN_INCR4 3
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#define GAHBCFG_HBSTLEN_INCR8 5
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#define GAHBCFG_HBSTLEN_INCR16 7
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#define GAHBCFG_GLBL_INTR_EN (1 << 0)
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#define GAHBCFG_GLBL_INTR_EN BIT(0)
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#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
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GAHBCFG_NP_TXF_EMP_LVL | \
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GAHBCFG_DMA_EN | \
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GAHBCFG_GLBL_INTR_EN)
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#define GUSBCFG HSOTG_REG(0x00C)
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#define GUSBCFG_FORCEDEVMODE (1 << 30)
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#define GUSBCFG_FORCEHOSTMODE (1 << 29)
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#define GUSBCFG_TXENDDELAY (1 << 28)
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#define GUSBCFG_ICTRAFFICPULLREMOVE (1 << 27)
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#define GUSBCFG_ICUSBCAP (1 << 26)
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#define GUSBCFG_ULPI_INT_PROT_DIS (1 << 25)
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#define GUSBCFG_INDICATORPASSTHROUGH (1 << 24)
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#define GUSBCFG_INDICATORCOMPLEMENT (1 << 23)
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#define GUSBCFG_TERMSELDLPULSE (1 << 22)
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#define GUSBCFG_ULPI_INT_VBUS_IND (1 << 21)
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#define GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20)
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#define GUSBCFG_ULPI_CLK_SUSP_M (1 << 19)
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#define GUSBCFG_ULPI_AUTO_RES (1 << 18)
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#define GUSBCFG_ULPI_FS_LS (1 << 17)
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#define GUSBCFG_OTG_UTMI_FS_SEL (1 << 16)
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#define GUSBCFG_PHY_LP_CLK_SEL (1 << 15)
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#define GUSBCFG_FORCEDEVMODE BIT(30)
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#define GUSBCFG_FORCEHOSTMODE BIT(29)
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#define GUSBCFG_TXENDDELAY BIT(28)
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#define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
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#define GUSBCFG_ICUSBCAP BIT(26)
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#define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
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#define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
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#define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
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#define GUSBCFG_TERMSELDLPULSE BIT(22)
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#define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
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#define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
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#define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
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#define GUSBCFG_ULPI_AUTO_RES BIT(18)
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#define GUSBCFG_ULPI_FS_LS BIT(17)
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#define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
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#define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
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#define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
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#define GUSBCFG_USBTRDTIM_SHIFT 10
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#define GUSBCFG_HNPCAP (1 << 9)
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#define GUSBCFG_SRPCAP (1 << 8)
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#define GUSBCFG_DDRSEL (1 << 7)
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#define GUSBCFG_PHYSEL (1 << 6)
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#define GUSBCFG_FSINTF (1 << 5)
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#define GUSBCFG_ULPI_UTMI_SEL (1 << 4)
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#define GUSBCFG_PHYIF16 (1 << 3)
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#define GUSBCFG_HNPCAP BIT(9)
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#define GUSBCFG_SRPCAP BIT(8)
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#define GUSBCFG_DDRSEL BIT(7)
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#define GUSBCFG_PHYSEL BIT(6)
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#define GUSBCFG_FSINTF BIT(5)
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#define GUSBCFG_ULPI_UTMI_SEL BIT(4)
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#define GUSBCFG_PHYIF16 BIT(3)
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#define GUSBCFG_PHYIF8 (0 << 3)
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#define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
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#define GUSBCFG_TOUTCAL_SHIFT 0
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@@ -117,54 +117,54 @@
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#define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
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#define GRSTCTL HSOTG_REG(0x010)
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#define GRSTCTL_AHBIDLE (1 << 31)
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#define GRSTCTL_DMAREQ (1 << 30)
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#define GRSTCTL_AHBIDLE BIT(31)
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#define GRSTCTL_DMAREQ BIT(30)
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#define GRSTCTL_TXFNUM_MASK (0x1f << 6)
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#define GRSTCTL_TXFNUM_SHIFT 6
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#define GRSTCTL_TXFNUM_LIMIT 0x1f
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#define GRSTCTL_TXFNUM(_x) ((_x) << 6)
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#define GRSTCTL_TXFFLSH (1 << 5)
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#define GRSTCTL_RXFFLSH (1 << 4)
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#define GRSTCTL_IN_TKNQ_FLSH (1 << 3)
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#define GRSTCTL_FRMCNTRRST (1 << 2)
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#define GRSTCTL_HSFTRST (1 << 1)
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#define GRSTCTL_CSFTRST (1 << 0)
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#define GRSTCTL_TXFFLSH BIT(5)
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#define GRSTCTL_RXFFLSH BIT(4)
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#define GRSTCTL_IN_TKNQ_FLSH BIT(3)
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#define GRSTCTL_FRMCNTRRST BIT(2)
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#define GRSTCTL_HSFTRST BIT(1)
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#define GRSTCTL_CSFTRST BIT(0)
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#define GINTSTS HSOTG_REG(0x014)
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#define GINTMSK HSOTG_REG(0x018)
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#define GINTSTS_WKUPINT (1 << 31)
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#define GINTSTS_SESSREQINT (1 << 30)
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#define GINTSTS_DISCONNINT (1 << 29)
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#define GINTSTS_CONIDSTSCHNG (1 << 28)
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#define GINTSTS_LPMTRANRCVD (1 << 27)
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#define GINTSTS_PTXFEMP (1 << 26)
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#define GINTSTS_HCHINT (1 << 25)
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#define GINTSTS_PRTINT (1 << 24)
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#define GINTSTS_RESETDET (1 << 23)
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#define GINTSTS_FET_SUSP (1 << 22)
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#define GINTSTS_INCOMPL_IP (1 << 21)
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#define GINTSTS_INCOMPL_SOOUT (1 << 21)
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#define GINTSTS_INCOMPL_SOIN (1 << 20)
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#define GINTSTS_OEPINT (1 << 19)
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#define GINTSTS_IEPINT (1 << 18)
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#define GINTSTS_EPMIS (1 << 17)
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#define GINTSTS_RESTOREDONE (1 << 16)
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#define GINTSTS_EOPF (1 << 15)
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#define GINTSTS_ISOUTDROP (1 << 14)
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#define GINTSTS_ENUMDONE (1 << 13)
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#define GINTSTS_USBRST (1 << 12)
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#define GINTSTS_USBSUSP (1 << 11)
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#define GINTSTS_ERLYSUSP (1 << 10)
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#define GINTSTS_I2CINT (1 << 9)
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#define GINTSTS_ULPI_CK_INT (1 << 8)
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#define GINTSTS_GOUTNAKEFF (1 << 7)
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#define GINTSTS_GINNAKEFF (1 << 6)
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#define GINTSTS_NPTXFEMP (1 << 5)
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#define GINTSTS_RXFLVL (1 << 4)
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#define GINTSTS_SOF (1 << 3)
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#define GINTSTS_OTGINT (1 << 2)
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#define GINTSTS_MODEMIS (1 << 1)
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#define GINTSTS_CURMODE_HOST (1 << 0)
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#define GINTSTS_WKUPINT BIT(31)
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#define GINTSTS_SESSREQINT BIT(30)
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#define GINTSTS_DISCONNINT BIT(29)
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#define GINTSTS_CONIDSTSCHNG BIT(28)
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#define GINTSTS_LPMTRANRCVD BIT(27)
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#define GINTSTS_PTXFEMP BIT(26)
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#define GINTSTS_HCHINT BIT(25)
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#define GINTSTS_PRTINT BIT(24)
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#define GINTSTS_RESETDET BIT(23)
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#define GINTSTS_FET_SUSP BIT(22)
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#define GINTSTS_INCOMPL_IP BIT(21)
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#define GINTSTS_INCOMPL_SOOUT BIT(21)
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#define GINTSTS_INCOMPL_SOIN BIT(20)
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#define GINTSTS_OEPINT BIT(19)
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#define GINTSTS_IEPINT BIT(18)
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#define GINTSTS_EPMIS BIT(17)
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#define GINTSTS_RESTOREDONE BIT(16)
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#define GINTSTS_EOPF BIT(15)
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#define GINTSTS_ISOUTDROP BIT(14)
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#define GINTSTS_ENUMDONE BIT(13)
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#define GINTSTS_USBRST BIT(12)
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#define GINTSTS_USBSUSP BIT(11)
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#define GINTSTS_ERLYSUSP BIT(10)
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#define GINTSTS_I2CINT BIT(9)
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#define GINTSTS_ULPI_CK_INT BIT(8)
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#define GINTSTS_GOUTNAKEFF BIT(7)
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#define GINTSTS_GINNAKEFF BIT(6)
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#define GINTSTS_NPTXFEMP BIT(5)
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#define GINTSTS_RXFLVL BIT(4)
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#define GINTSTS_SOF BIT(3)
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#define GINTSTS_OTGINT BIT(2)
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#define GINTSTS_MODEMIS BIT(1)
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#define GINTSTS_CURMODE_HOST BIT(0)
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#define GRXSTSR HSOTG_REG(0x01C)
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#define GRXSTSP HSOTG_REG(0x020)
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@@ -208,14 +208,14 @@
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#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
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#define GI2CCTL HSOTG_REG(0x0030)
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#define GI2CCTL_BSYDNE (1 << 31)
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#define GI2CCTL_RW (1 << 30)
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#define GI2CCTL_I2CDATSE0 (1 << 28)
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#define GI2CCTL_BSYDNE BIT(31)
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#define GI2CCTL_RW BIT(30)
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#define GI2CCTL_I2CDATSE0 BIT(28)
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#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
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#define GI2CCTL_I2CDEVADDR_SHIFT 26
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#define GI2CCTL_I2CSUSPCTL (1 << 25)
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#define GI2CCTL_ACK (1 << 24)
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#define GI2CCTL_I2CEN (1 << 23)
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#define GI2CCTL_I2CSUSPCTL BIT(25)
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#define GI2CCTL_ACK BIT(24)
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#define GI2CCTL_I2CEN BIT(23)
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#define GI2CCTL_ADDR_MASK (0x7f << 16)
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#define GI2CCTL_ADDR_SHIFT 16
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#define GI2CCTL_REGADDR_MASK (0xff << 8)
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@@ -230,16 +230,16 @@
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#define GHWCFG1 HSOTG_REG(0x0044)
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#define GHWCFG2 HSOTG_REG(0x0048)
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#define GHWCFG2_OTG_ENABLE_IC_USB (1 << 31)
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#define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
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#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
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#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
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#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
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#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
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#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
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#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
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#define GHWCFG2_MULTI_PROC_INT (1 << 20)
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#define GHWCFG2_DYNAMIC_FIFO (1 << 19)
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#define GHWCFG2_PERIO_EP_SUPPORTED (1 << 18)
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#define GHWCFG2_MULTI_PROC_INT BIT(20)
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#define GHWCFG2_DYNAMIC_FIFO BIT(19)
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#define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
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#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
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#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
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#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
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@@ -256,7 +256,7 @@
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#define GHWCFG2_HS_PHY_TYPE_UTMI 1
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#define GHWCFG2_HS_PHY_TYPE_ULPI 2
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#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
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#define GHWCFG2_POINT2POINT (1 << 5)
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#define GHWCFG2_POINT2POINT BIT(5)
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#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
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#define GHWCFG2_ARCHITECTURE_SHIFT 3
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#define GHWCFG2_SLAVE_ONLY_ARCH 0
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@@ -276,32 +276,32 @@
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#define GHWCFG3 HSOTG_REG(0x004c)
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#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
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#define GHWCFG3_DFIFO_DEPTH_SHIFT 16
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#define GHWCFG3_OTG_LPM_EN (1 << 15)
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#define GHWCFG3_BC_SUPPORT (1 << 14)
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#define GHWCFG3_OTG_ENABLE_HSIC (1 << 13)
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#define GHWCFG3_ADP_SUPP (1 << 12)
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#define GHWCFG3_SYNCH_RESET_TYPE (1 << 11)
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#define GHWCFG3_OPTIONAL_FEATURES (1 << 10)
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#define GHWCFG3_VENDOR_CTRL_IF (1 << 9)
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#define GHWCFG3_I2C (1 << 8)
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#define GHWCFG3_OTG_FUNC (1 << 7)
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#define GHWCFG3_OTG_LPM_EN BIT(15)
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#define GHWCFG3_BC_SUPPORT BIT(14)
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#define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
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#define GHWCFG3_ADP_SUPP BIT(12)
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#define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
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#define GHWCFG3_OPTIONAL_FEATURES BIT(10)
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#define GHWCFG3_VENDOR_CTRL_IF BIT(9)
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#define GHWCFG3_I2C BIT(8)
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#define GHWCFG3_OTG_FUNC BIT(7)
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#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
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#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
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#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
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#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
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#define GHWCFG4 HSOTG_REG(0x0050)
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#define GHWCFG4_DESC_DMA_DYN (1 << 31)
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#define GHWCFG4_DESC_DMA (1 << 30)
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#define GHWCFG4_DESC_DMA_DYN BIT(31)
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#define GHWCFG4_DESC_DMA BIT(30)
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#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
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#define GHWCFG4_NUM_IN_EPS_SHIFT 26
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#define GHWCFG4_DED_FIFO_EN (1 << 25)
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#define GHWCFG4_DED_FIFO_EN BIT(25)
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#define GHWCFG4_DED_FIFO_SHIFT 25
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#define GHWCFG4_SESSION_END_FILT_EN (1 << 24)
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#define GHWCFG4_B_VALID_FILT_EN (1 << 23)
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#define GHWCFG4_A_VALID_FILT_EN (1 << 22)
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#define GHWCFG4_VBUS_VALID_FILT_EN (1 << 21)
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#define GHWCFG4_IDDIG_FILT_EN (1 << 20)
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#define GHWCFG4_SESSION_END_FILT_EN BIT(24)
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#define GHWCFG4_B_VALID_FILT_EN BIT(23)
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#define GHWCFG4_A_VALID_FILT_EN BIT(22)
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#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
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#define GHWCFG4_IDDIG_FILT_EN BIT(20)
|
||||
#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
|
||||
#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
|
||||
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
|
||||
@@ -309,64 +309,64 @@
|
||||
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
|
||||
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
|
||||
#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
|
||||
#define GHWCFG4_XHIBER (1 << 7)
|
||||
#define GHWCFG4_HIBER (1 << 6)
|
||||
#define GHWCFG4_MIN_AHB_FREQ (1 << 5)
|
||||
#define GHWCFG4_POWER_OPTIMIZ (1 << 4)
|
||||
#define GHWCFG4_XHIBER BIT(7)
|
||||
#define GHWCFG4_HIBER BIT(6)
|
||||
#define GHWCFG4_MIN_AHB_FREQ BIT(5)
|
||||
#define GHWCFG4_POWER_OPTIMIZ BIT(4)
|
||||
#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
|
||||
#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
|
||||
|
||||
#define GLPMCFG HSOTG_REG(0x0054)
|
||||
#define GLPMCFG_INV_SEL_HSIC (1 << 31)
|
||||
#define GLPMCFG_HSIC_CONNECT (1 << 30)
|
||||
#define GLPMCFG_INV_SEL_HSIC BIT(31)
|
||||
#define GLPMCFG_HSIC_CONNECT BIT(30)
|
||||
#define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25)
|
||||
#define GLPMCFG_RETRY_COUNT_STS_SHIFT 25
|
||||
#define GLPMCFG_SEND_LPM (1 << 24)
|
||||
#define GLPMCFG_SEND_LPM BIT(24)
|
||||
#define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21)
|
||||
#define GLPMCFG_RETRY_COUNT_SHIFT 21
|
||||
#define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17)
|
||||
#define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17
|
||||
#define GLPMCFG_SLEEP_STATE_RESUMEOK (1 << 16)
|
||||
#define GLPMCFG_PRT_SLEEP_STS (1 << 15)
|
||||
#define GLPMCFG_SLEEP_STATE_RESUMEOK BIT(16)
|
||||
#define GLPMCFG_PRT_SLEEP_STS BIT(15)
|
||||
#define GLPMCFG_LPM_RESP_MASK (0x3 << 13)
|
||||
#define GLPMCFG_LPM_RESP_SHIFT 13
|
||||
#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
|
||||
#define GLPMCFG_HIRD_THRES_SHIFT 8
|
||||
#define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
|
||||
#define GLPMCFG_EN_UTMI_SLEEP (1 << 7)
|
||||
#define GLPMCFG_REM_WKUP_EN (1 << 6)
|
||||
#define GLPMCFG_EN_UTMI_SLEEP BIT(7)
|
||||
#define GLPMCFG_REM_WKUP_EN BIT(6)
|
||||
#define GLPMCFG_HIRD_MASK (0xf << 2)
|
||||
#define GLPMCFG_HIRD_SHIFT 2
|
||||
#define GLPMCFG_APPL_RESP (1 << 1)
|
||||
#define GLPMCFG_LPM_CAP_EN (1 << 0)
|
||||
#define GLPMCFG_APPL_RESP BIT(1)
|
||||
#define GLPMCFG_LPM_CAP_EN BIT(0)
|
||||
|
||||
#define GPWRDN HSOTG_REG(0x0058)
|
||||
#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
|
||||
#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
|
||||
#define GPWRDN_ADP_INT (1 << 23)
|
||||
#define GPWRDN_BSESSVLD (1 << 22)
|
||||
#define GPWRDN_IDSTS (1 << 21)
|
||||
#define GPWRDN_ADP_INT BIT(23)
|
||||
#define GPWRDN_BSESSVLD BIT(22)
|
||||
#define GPWRDN_IDSTS BIT(21)
|
||||
#define GPWRDN_LINESTATE_MASK (0x3 << 19)
|
||||
#define GPWRDN_LINESTATE_SHIFT 19
|
||||
#define GPWRDN_STS_CHGINT_MSK (1 << 18)
|
||||
#define GPWRDN_STS_CHGINT (1 << 17)
|
||||
#define GPWRDN_SRP_DET_MSK (1 << 16)
|
||||
#define GPWRDN_SRP_DET (1 << 15)
|
||||
#define GPWRDN_CONNECT_DET_MSK (1 << 14)
|
||||
#define GPWRDN_CONNECT_DET (1 << 13)
|
||||
#define GPWRDN_DISCONN_DET_MSK (1 << 12)
|
||||
#define GPWRDN_DISCONN_DET (1 << 11)
|
||||
#define GPWRDN_RST_DET_MSK (1 << 10)
|
||||
#define GPWRDN_RST_DET (1 << 9)
|
||||
#define GPWRDN_LNSTSCHG_MSK (1 << 8)
|
||||
#define GPWRDN_LNSTSCHG (1 << 7)
|
||||
#define GPWRDN_DIS_VBUS (1 << 6)
|
||||
#define GPWRDN_PWRDNSWTCH (1 << 5)
|
||||
#define GPWRDN_PWRDNRSTN (1 << 4)
|
||||
#define GPWRDN_PWRDNCLMP (1 << 3)
|
||||
#define GPWRDN_RESTORE (1 << 2)
|
||||
#define GPWRDN_PMUACTV (1 << 1)
|
||||
#define GPWRDN_PMUINTSEL (1 << 0)
|
||||
#define GPWRDN_STS_CHGINT_MSK BIT(18)
|
||||
#define GPWRDN_STS_CHGINT BIT(17)
|
||||
#define GPWRDN_SRP_DET_MSK BIT(16)
|
||||
#define GPWRDN_SRP_DET BIT(15)
|
||||
#define GPWRDN_CONNECT_DET_MSK BIT(14)
|
||||
#define GPWRDN_CONNECT_DET BIT(13)
|
||||
#define GPWRDN_DISCONN_DET_MSK BIT(12)
|
||||
#define GPWRDN_DISCONN_DET BIT(11)
|
||||
#define GPWRDN_RST_DET_MSK BIT(10)
|
||||
#define GPWRDN_RST_DET BIT(9)
|
||||
#define GPWRDN_LNSTSCHG_MSK BIT(8)
|
||||
#define GPWRDN_LNSTSCHG BIT(7)
|
||||
#define GPWRDN_DIS_VBUS BIT(6)
|
||||
#define GPWRDN_PWRDNSWTCH BIT(5)
|
||||
#define GPWRDN_PWRDNRSTN BIT(4)
|
||||
#define GPWRDN_PWRDNCLMP BIT(3)
|
||||
#define GPWRDN_RESTORE BIT(2)
|
||||
#define GPWRDN_PMUACTV BIT(1)
|
||||
#define GPWRDN_PMUINTSEL BIT(0)
|
||||
|
||||
#define GDFIFOCFG HSOTG_REG(0x005c)
|
||||
#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
|
||||
@@ -377,16 +377,16 @@
|
||||
#define ADPCTL HSOTG_REG(0x0060)
|
||||
#define ADPCTL_AR_MASK (0x3 << 27)
|
||||
#define ADPCTL_AR_SHIFT 27
|
||||
#define ADPCTL_ADP_TMOUT_INT_MSK (1 << 26)
|
||||
#define ADPCTL_ADP_SNS_INT_MSK (1 << 25)
|
||||
#define ADPCTL_ADP_PRB_INT_MSK (1 << 24)
|
||||
#define ADPCTL_ADP_TMOUT_INT (1 << 23)
|
||||
#define ADPCTL_ADP_SNS_INT (1 << 22)
|
||||
#define ADPCTL_ADP_PRB_INT (1 << 21)
|
||||
#define ADPCTL_ADPENA (1 << 20)
|
||||
#define ADPCTL_ADPRES (1 << 19)
|
||||
#define ADPCTL_ENASNS (1 << 18)
|
||||
#define ADPCTL_ENAPRB (1 << 17)
|
||||
#define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
|
||||
#define ADPCTL_ADP_SNS_INT_MSK BIT(25)
|
||||
#define ADPCTL_ADP_PRB_INT_MSK BIT(24)
|
||||
#define ADPCTL_ADP_TMOUT_INT BIT(23)
|
||||
#define ADPCTL_ADP_SNS_INT BIT(22)
|
||||
#define ADPCTL_ADP_PRB_INT BIT(21)
|
||||
#define ADPCTL_ADPENA BIT(20)
|
||||
#define ADPCTL_ADPRES BIT(19)
|
||||
#define ADPCTL_ENASNS BIT(18)
|
||||
#define ADPCTL_ENAPRB BIT(17)
|
||||
#define ADPCTL_RTIM_MASK (0x7ff << 6)
|
||||
#define ADPCTL_RTIM_SHIFT 6
|
||||
#define ADPCTL_PRB_PER_MASK (0x3 << 4)
|
||||
@@ -412,7 +412,7 @@
|
||||
/* Device mode registers */
|
||||
|
||||
#define DCFG HSOTG_REG(0x800)
|
||||
#define DCFG_DESCDMA_EN (1 << 23)
|
||||
#define DCFG_DESCDMA_EN BIT(23)
|
||||
#define DCFG_EPMISCNT_MASK (0x1f << 18)
|
||||
#define DCFG_EPMISCNT_SHIFT 18
|
||||
#define DCFG_EPMISCNT_LIMIT 0x1f
|
||||
@@ -425,7 +425,7 @@
|
||||
#define DCFG_DEVADDR_SHIFT 4
|
||||
#define DCFG_DEVADDR_LIMIT 0x7f
|
||||
#define DCFG_DEVADDR(_x) ((_x) << 4)
|
||||
#define DCFG_NZ_STS_OUT_HSHK (1 << 2)
|
||||
#define DCFG_NZ_STS_OUT_HSHK BIT(2)
|
||||
#define DCFG_DEVSPD_MASK (0x3 << 0)
|
||||
#define DCFG_DEVSPD_SHIFT 0
|
||||
#define DCFG_DEVSPD_HS 0
|
||||
@@ -434,54 +434,54 @@
|
||||
#define DCFG_DEVSPD_FS48 3
|
||||
|
||||
#define DCTL HSOTG_REG(0x804)
|
||||
#define DCTL_PWRONPRGDONE (1 << 11)
|
||||
#define DCTL_CGOUTNAK (1 << 10)
|
||||
#define DCTL_SGOUTNAK (1 << 9)
|
||||
#define DCTL_CGNPINNAK (1 << 8)
|
||||
#define DCTL_SGNPINNAK (1 << 7)
|
||||
#define DCTL_PWRONPRGDONE BIT(11)
|
||||
#define DCTL_CGOUTNAK BIT(10)
|
||||
#define DCTL_SGOUTNAK BIT(9)
|
||||
#define DCTL_CGNPINNAK BIT(8)
|
||||
#define DCTL_SGNPINNAK BIT(7)
|
||||
#define DCTL_TSTCTL_MASK (0x7 << 4)
|
||||
#define DCTL_TSTCTL_SHIFT 4
|
||||
#define DCTL_GOUTNAKSTS (1 << 3)
|
||||
#define DCTL_GNPINNAKSTS (1 << 2)
|
||||
#define DCTL_SFTDISCON (1 << 1)
|
||||
#define DCTL_RMTWKUPSIG (1 << 0)
|
||||
#define DCTL_GOUTNAKSTS BIT(3)
|
||||
#define DCTL_GNPINNAKSTS BIT(2)
|
||||
#define DCTL_SFTDISCON BIT(1)
|
||||
#define DCTL_RMTWKUPSIG BIT(0)
|
||||
|
||||
#define DSTS HSOTG_REG(0x808)
|
||||
#define DSTS_SOFFN_MASK (0x3fff << 8)
|
||||
#define DSTS_SOFFN_SHIFT 8
|
||||
#define DSTS_SOFFN_LIMIT 0x3fff
|
||||
#define DSTS_SOFFN(_x) ((_x) << 8)
|
||||
#define DSTS_ERRATICERR (1 << 3)
|
||||
#define DSTS_ERRATICERR BIT(3)
|
||||
#define DSTS_ENUMSPD_MASK (0x3 << 1)
|
||||
#define DSTS_ENUMSPD_SHIFT 1
|
||||
#define DSTS_ENUMSPD_HS 0
|
||||
#define DSTS_ENUMSPD_FS 1
|
||||
#define DSTS_ENUMSPD_LS 2
|
||||
#define DSTS_ENUMSPD_FS48 3
|
||||
#define DSTS_SUSPSTS (1 << 0)
|
||||
#define DSTS_SUSPSTS BIT(0)
|
||||
|
||||
#define DIEPMSK HSOTG_REG(0x810)
|
||||
#define DIEPMSK_NAKMSK (1 << 13)
|
||||
#define DIEPMSK_BNAININTRMSK (1 << 9)
|
||||
#define DIEPMSK_TXFIFOUNDRNMSK (1 << 8)
|
||||
#define DIEPMSK_TXFIFOEMPTY (1 << 7)
|
||||
#define DIEPMSK_INEPNAKEFFMSK (1 << 6)
|
||||
#define DIEPMSK_INTKNEPMISMSK (1 << 5)
|
||||
#define DIEPMSK_INTKNTXFEMPMSK (1 << 4)
|
||||
#define DIEPMSK_TIMEOUTMSK (1 << 3)
|
||||
#define DIEPMSK_AHBERRMSK (1 << 2)
|
||||
#define DIEPMSK_EPDISBLDMSK (1 << 1)
|
||||
#define DIEPMSK_XFERCOMPLMSK (1 << 0)
|
||||
#define DIEPMSK_NAKMSK BIT(13)
|
||||
#define DIEPMSK_BNAININTRMSK BIT(9)
|
||||
#define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
|
||||
#define DIEPMSK_TXFIFOEMPTY BIT(7)
|
||||
#define DIEPMSK_INEPNAKEFFMSK BIT(6)
|
||||
#define DIEPMSK_INTKNEPMISMSK BIT(5)
|
||||
#define DIEPMSK_INTKNTXFEMPMSK BIT(4)
|
||||
#define DIEPMSK_TIMEOUTMSK BIT(3)
|
||||
#define DIEPMSK_AHBERRMSK BIT(2)
|
||||
#define DIEPMSK_EPDISBLDMSK BIT(1)
|
||||
#define DIEPMSK_XFERCOMPLMSK BIT(0)
|
||||
|
||||
#define DOEPMSK HSOTG_REG(0x814)
|
||||
#define DOEPMSK_BNAMSK (1 << 9)
|
||||
#define DOEPMSK_BACK2BACKSETUP (1 << 6)
|
||||
#define DOEPMSK_STSPHSERCVDMSK (1 << 5)
|
||||
#define DOEPMSK_OUTTKNEPDISMSK (1 << 4)
|
||||
#define DOEPMSK_SETUPMSK (1 << 3)
|
||||
#define DOEPMSK_AHBERRMSK (1 << 2)
|
||||
#define DOEPMSK_EPDISBLDMSK (1 << 1)
|
||||
#define DOEPMSK_XFERCOMPLMSK (1 << 0)
|
||||
#define DOEPMSK_BNAMSK BIT(9)
|
||||
#define DOEPMSK_BACK2BACKSETUP BIT(6)
|
||||
#define DOEPMSK_STSPHSERCVDMSK BIT(5)
|
||||
#define DOEPMSK_OUTTKNEPDISMSK BIT(4)
|
||||
#define DOEPMSK_SETUPMSK BIT(3)
|
||||
#define DOEPMSK_AHBERRMSK BIT(2)
|
||||
#define DOEPMSK_EPDISBLDMSK BIT(1)
|
||||
#define DOEPMSK_XFERCOMPLMSK BIT(0)
|
||||
|
||||
#define DAINT HSOTG_REG(0x818)
|
||||
#define DAINTMSK HSOTG_REG(0x81C)
|
||||
@@ -516,30 +516,30 @@
|
||||
#define D0EPCTL_MPS_16 2
|
||||
#define D0EPCTL_MPS_8 3
|
||||
|
||||
#define DXEPCTL_EPENA (1 << 31)
|
||||
#define DXEPCTL_EPDIS (1 << 30)
|
||||
#define DXEPCTL_SETD1PID (1 << 29)
|
||||
#define DXEPCTL_SETODDFR (1 << 29)
|
||||
#define DXEPCTL_SETD0PID (1 << 28)
|
||||
#define DXEPCTL_SETEVENFR (1 << 28)
|
||||
#define DXEPCTL_SNAK (1 << 27)
|
||||
#define DXEPCTL_CNAK (1 << 26)
|
||||
#define DXEPCTL_EPENA BIT(31)
|
||||
#define DXEPCTL_EPDIS BIT(30)
|
||||
#define DXEPCTL_SETD1PID BIT(29)
|
||||
#define DXEPCTL_SETODDFR BIT(29)
|
||||
#define DXEPCTL_SETD0PID BIT(28)
|
||||
#define DXEPCTL_SETEVENFR BIT(28)
|
||||
#define DXEPCTL_SNAK BIT(27)
|
||||
#define DXEPCTL_CNAK BIT(26)
|
||||
#define DXEPCTL_TXFNUM_MASK (0xf << 22)
|
||||
#define DXEPCTL_TXFNUM_SHIFT 22
|
||||
#define DXEPCTL_TXFNUM_LIMIT 0xf
|
||||
#define DXEPCTL_TXFNUM(_x) ((_x) << 22)
|
||||
#define DXEPCTL_STALL (1 << 21)
|
||||
#define DXEPCTL_SNP (1 << 20)
|
||||
#define DXEPCTL_STALL BIT(21)
|
||||
#define DXEPCTL_SNP BIT(20)
|
||||
#define DXEPCTL_EPTYPE_MASK (0x3 << 18)
|
||||
#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
|
||||
#define DXEPCTL_EPTYPE_ISO (0x1 << 18)
|
||||
#define DXEPCTL_EPTYPE_BULK (0x2 << 18)
|
||||
#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
|
||||
|
||||
#define DXEPCTL_NAKSTS (1 << 17)
|
||||
#define DXEPCTL_DPID (1 << 16)
|
||||
#define DXEPCTL_EOFRNUM (1 << 16)
|
||||
#define DXEPCTL_USBACTEP (1 << 15)
|
||||
#define DXEPCTL_NAKSTS BIT(17)
|
||||
#define DXEPCTL_DPID BIT(16)
|
||||
#define DXEPCTL_EOFRNUM BIT(16)
|
||||
#define DXEPCTL_USBACTEP BIT(15)
|
||||
#define DXEPCTL_NEXTEP_MASK (0xf << 11)
|
||||
#define DXEPCTL_NEXTEP_SHIFT 11
|
||||
#define DXEPCTL_NEXTEP_LIMIT 0xf
|
||||
@@ -551,26 +551,26 @@
|
||||
|
||||
#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
|
||||
#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
|
||||
#define DXEPINT_SETUP_RCVD (1 << 15)
|
||||
#define DXEPINT_NYETINTRPT (1 << 14)
|
||||
#define DXEPINT_NAKINTRPT (1 << 13)
|
||||
#define DXEPINT_BBLEERRINTRPT (1 << 12)
|
||||
#define DXEPINT_PKTDRPSTS (1 << 11)
|
||||
#define DXEPINT_BNAINTR (1 << 9)
|
||||
#define DXEPINT_TXFIFOUNDRN (1 << 8)
|
||||
#define DXEPINT_OUTPKTERR (1 << 8)
|
||||
#define DXEPINT_TXFEMP (1 << 7)
|
||||
#define DXEPINT_INEPNAKEFF (1 << 6)
|
||||
#define DXEPINT_BACK2BACKSETUP (1 << 6)
|
||||
#define DXEPINT_INTKNEPMIS (1 << 5)
|
||||
#define DXEPINT_STSPHSERCVD (1 << 5)
|
||||
#define DXEPINT_INTKNTXFEMP (1 << 4)
|
||||
#define DXEPINT_OUTTKNEPDIS (1 << 4)
|
||||
#define DXEPINT_TIMEOUT (1 << 3)
|
||||
#define DXEPINT_SETUP (1 << 3)
|
||||
#define DXEPINT_AHBERR (1 << 2)
|
||||
#define DXEPINT_EPDISBLD (1 << 1)
|
||||
#define DXEPINT_XFERCOMPL (1 << 0)
|
||||
#define DXEPINT_SETUP_RCVD BIT(15)
|
||||
#define DXEPINT_NYETINTRPT BIT(14)
|
||||
#define DXEPINT_NAKINTRPT BIT(13)
|
||||
#define DXEPINT_BBLEERRINTRPT BIT(12)
|
||||
#define DXEPINT_PKTDRPSTS BIT(11)
|
||||
#define DXEPINT_BNAINTR BIT(9)
|
||||
#define DXEPINT_TXFIFOUNDRN BIT(8)
|
||||
#define DXEPINT_OUTPKTERR BIT(8)
|
||||
#define DXEPINT_TXFEMP BIT(7)
|
||||
#define DXEPINT_INEPNAKEFF BIT(6)
|
||||
#define DXEPINT_BACK2BACKSETUP BIT(6)
|
||||
#define DXEPINT_INTKNEPMIS BIT(5)
|
||||
#define DXEPINT_STSPHSERCVD BIT(5)
|
||||
#define DXEPINT_INTKNTXFEMP BIT(4)
|
||||
#define DXEPINT_OUTTKNEPDIS BIT(4)
|
||||
#define DXEPINT_TIMEOUT BIT(3)
|
||||
#define DXEPINT_SETUP BIT(3)
|
||||
#define DXEPINT_AHBERR BIT(2)
|
||||
#define DXEPINT_EPDISBLD BIT(1)
|
||||
#define DXEPINT_XFERCOMPL BIT(0)
|
||||
|
||||
#define DIEPTSIZ0 HSOTG_REG(0x910)
|
||||
#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
|
||||
@@ -587,7 +587,7 @@
|
||||
#define DOEPTSIZ0_SUPCNT_SHIFT 29
|
||||
#define DOEPTSIZ0_SUPCNT_LIMIT 0x3
|
||||
#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
|
||||
#define DOEPTSIZ0_PKTCNT (1 << 19)
|
||||
#define DOEPTSIZ0_PKTCNT BIT(19)
|
||||
#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
|
||||
#define DOEPTSIZ0_XFERSIZE_SHIFT 0
|
||||
|
||||
@@ -614,55 +614,55 @@
|
||||
#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
|
||||
|
||||
#define PCGCTL HSOTG_REG(0x0e00)
|
||||
#define PCGCTL_IF_DEV_MODE (1 << 31)
|
||||
#define PCGCTL_IF_DEV_MODE BIT(31)
|
||||
#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
|
||||
#define PCGCTL_P2HD_PRT_SPD_SHIFT 29
|
||||
#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
|
||||
#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
|
||||
#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
|
||||
#define PCGCTL_MAC_DEV_ADDR_SHIFT 20
|
||||
#define PCGCTL_MAX_TERMSEL (1 << 19)
|
||||
#define PCGCTL_MAX_TERMSEL BIT(19)
|
||||
#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
|
||||
#define PCGCTL_MAX_XCVRSELECT_SHIFT 17
|
||||
#define PCGCTL_PORT_POWER (1 << 16)
|
||||
#define PCGCTL_PORT_POWER BIT(16)
|
||||
#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
|
||||
#define PCGCTL_PRT_CLK_SEL_SHIFT 14
|
||||
#define PCGCTL_ESS_REG_RESTORED (1 << 13)
|
||||
#define PCGCTL_EXTND_HIBER_SWITCH (1 << 12)
|
||||
#define PCGCTL_EXTND_HIBER_PWRCLMP (1 << 11)
|
||||
#define PCGCTL_ENBL_EXTND_HIBER (1 << 10)
|
||||
#define PCGCTL_RESTOREMODE (1 << 9)
|
||||
#define PCGCTL_RESETAFTSUSP (1 << 8)
|
||||
#define PCGCTL_DEEP_SLEEP (1 << 7)
|
||||
#define PCGCTL_PHY_IN_SLEEP (1 << 6)
|
||||
#define PCGCTL_ENBL_SLEEP_GATING (1 << 5)
|
||||
#define PCGCTL_RSTPDWNMODULE (1 << 3)
|
||||
#define PCGCTL_PWRCLMP (1 << 2)
|
||||
#define PCGCTL_GATEHCLK (1 << 1)
|
||||
#define PCGCTL_STOPPCLK (1 << 0)
|
||||
#define PCGCTL_ESS_REG_RESTORED BIT(13)
|
||||
#define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
|
||||
#define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
|
||||
#define PCGCTL_ENBL_EXTND_HIBER BIT(10)
|
||||
#define PCGCTL_RESTOREMODE BIT(9)
|
||||
#define PCGCTL_RESETAFTSUSP BIT(8)
|
||||
#define PCGCTL_DEEP_SLEEP BIT(7)
|
||||
#define PCGCTL_PHY_IN_SLEEP BIT(6)
|
||||
#define PCGCTL_ENBL_SLEEP_GATING BIT(5)
|
||||
#define PCGCTL_RSTPDWNMODULE BIT(3)
|
||||
#define PCGCTL_PWRCLMP BIT(2)
|
||||
#define PCGCTL_GATEHCLK BIT(1)
|
||||
#define PCGCTL_STOPPCLK BIT(0)
|
||||
|
||||
#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
|
||||
|
||||
/* Host Mode Registers */
|
||||
|
||||
#define HCFG HSOTG_REG(0x0400)
|
||||
#define HCFG_MODECHTIMEN (1 << 31)
|
||||
#define HCFG_PERSCHEDENA (1 << 26)
|
||||
#define HCFG_MODECHTIMEN BIT(31)
|
||||
#define HCFG_PERSCHEDENA BIT(26)
|
||||
#define HCFG_FRLISTEN_MASK (0x3 << 24)
|
||||
#define HCFG_FRLISTEN_SHIFT 24
|
||||
#define HCFG_FRLISTEN_8 (0 << 24)
|
||||
#define FRLISTEN_8_SIZE 8
|
||||
#define HCFG_FRLISTEN_16 (1 << 24)
|
||||
#define HCFG_FRLISTEN_16 BIT(24)
|
||||
#define FRLISTEN_16_SIZE 16
|
||||
#define HCFG_FRLISTEN_32 (2 << 24)
|
||||
#define FRLISTEN_32_SIZE 32
|
||||
#define HCFG_FRLISTEN_64 (3 << 24)
|
||||
#define FRLISTEN_64_SIZE 64
|
||||
#define HCFG_DESCDMA (1 << 23)
|
||||
#define HCFG_DESCDMA BIT(23)
|
||||
#define HCFG_RESVALID_MASK (0xff << 8)
|
||||
#define HCFG_RESVALID_SHIFT 8
|
||||
#define HCFG_ENA32KHZ (1 << 7)
|
||||
#define HCFG_FSLSSUPP (1 << 2)
|
||||
#define HCFG_ENA32KHZ BIT(7)
|
||||
#define HCFG_FSLSSUPP BIT(2)
|
||||
#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
|
||||
#define HCFG_FSLSPCLKSEL_SHIFT 0
|
||||
#define HCFG_FSLSPCLKSEL_30_60_MHZ 0
|
||||
@@ -672,7 +672,7 @@
|
||||
#define HFIR HSOTG_REG(0x0404)
|
||||
#define HFIR_FRINT_MASK (0xffff << 0)
|
||||
#define HFIR_FRINT_SHIFT 0
|
||||
#define HFIR_RLDCTRL (1 << 16)
|
||||
#define HFIR_RLDCTRL BIT(16)
|
||||
|
||||
#define HFNUM HSOTG_REG(0x0408)
|
||||
#define HFNUM_FRREM_MASK (0xffff << 16)
|
||||
@@ -682,12 +682,12 @@
|
||||
#define HFNUM_MAX_FRNUM 0x3fff
|
||||
|
||||
#define HPTXSTS HSOTG_REG(0x0410)
|
||||
#define TXSTS_QTOP_ODD (1 << 31)
|
||||
#define TXSTS_QTOP_ODD BIT(31)
|
||||
#define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
|
||||
#define TXSTS_QTOP_CHNEP_SHIFT 27
|
||||
#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
|
||||
#define TXSTS_QTOP_TOKEN_SHIFT 25
|
||||
#define TXSTS_QTOP_TERMINATE (1 << 24)
|
||||
#define TXSTS_QTOP_TERMINATE BIT(24)
|
||||
#define TXSTS_QSPCAVAIL_MASK (0xff << 16)
|
||||
#define TXSTS_QSPCAVAIL_SHIFT 16
|
||||
#define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
|
||||
@@ -705,39 +705,39 @@
|
||||
#define HPRT0_SPD_LOW_SPEED 2
|
||||
#define HPRT0_TSTCTL_MASK (0xf << 13)
|
||||
#define HPRT0_TSTCTL_SHIFT 13
|
||||
#define HPRT0_PWR (1 << 12)
|
||||
#define HPRT0_PWR BIT(12)
|
||||
#define HPRT0_LNSTS_MASK (0x3 << 10)
|
||||
#define HPRT0_LNSTS_SHIFT 10
|
||||
#define HPRT0_RST (1 << 8)
|
||||
#define HPRT0_SUSP (1 << 7)
|
||||
#define HPRT0_RES (1 << 6)
|
||||
#define HPRT0_OVRCURRCHG (1 << 5)
|
||||
#define HPRT0_OVRCURRACT (1 << 4)
|
||||
#define HPRT0_ENACHG (1 << 3)
|
||||
#define HPRT0_ENA (1 << 2)
|
||||
#define HPRT0_CONNDET (1 << 1)
|
||||
#define HPRT0_CONNSTS (1 << 0)
|
||||
#define HPRT0_RST BIT(8)
|
||||
#define HPRT0_SUSP BIT(7)
|
||||
#define HPRT0_RES BIT(6)
|
||||
#define HPRT0_OVRCURRCHG BIT(5)
|
||||
#define HPRT0_OVRCURRACT BIT(4)
|
||||
#define HPRT0_ENACHG BIT(3)
|
||||
#define HPRT0_ENA BIT(2)
|
||||
#define HPRT0_CONNDET BIT(1)
|
||||
#define HPRT0_CONNSTS BIT(0)
|
||||
|
||||
#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
|
||||
#define HCCHAR_CHENA (1 << 31)
|
||||
#define HCCHAR_CHDIS (1 << 30)
|
||||
#define HCCHAR_ODDFRM (1 << 29)
|
||||
#define HCCHAR_CHENA BIT(31)
|
||||
#define HCCHAR_CHDIS BIT(30)
|
||||
#define HCCHAR_ODDFRM BIT(29)
|
||||
#define HCCHAR_DEVADDR_MASK (0x7f << 22)
|
||||
#define HCCHAR_DEVADDR_SHIFT 22
|
||||
#define HCCHAR_MULTICNT_MASK (0x3 << 20)
|
||||
#define HCCHAR_MULTICNT_SHIFT 20
|
||||
#define HCCHAR_EPTYPE_MASK (0x3 << 18)
|
||||
#define HCCHAR_EPTYPE_SHIFT 18
|
||||
#define HCCHAR_LSPDDEV (1 << 17)
|
||||
#define HCCHAR_EPDIR (1 << 15)
|
||||
#define HCCHAR_LSPDDEV BIT(17)
|
||||
#define HCCHAR_EPDIR BIT(15)
|
||||
#define HCCHAR_EPNUM_MASK (0xf << 11)
|
||||
#define HCCHAR_EPNUM_SHIFT 11
|
||||
#define HCCHAR_MPS_MASK (0x7ff << 0)
|
||||
#define HCCHAR_MPS_SHIFT 0
|
||||
|
||||
#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
|
||||
#define HCSPLT_SPLTENA (1 << 31)
|
||||
#define HCSPLT_COMPSPLT (1 << 16)
|
||||
#define HCSPLT_SPLTENA BIT(31)
|
||||
#define HCSPLT_COMPSPLT BIT(16)
|
||||
#define HCSPLT_XACTPOS_MASK (0x3 << 14)
|
||||
#define HCSPLT_XACTPOS_SHIFT 14
|
||||
#define HCSPLT_XACTPOS_MID 0
|
||||
@@ -752,23 +752,23 @@
|
||||
#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
|
||||
#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
|
||||
#define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
|
||||
#define HCINTMSK_FRM_LIST_ROLL (1 << 13)
|
||||
#define HCINTMSK_XCS_XACT (1 << 12)
|
||||
#define HCINTMSK_BNA (1 << 11)
|
||||
#define HCINTMSK_DATATGLERR (1 << 10)
|
||||
#define HCINTMSK_FRMOVRUN (1 << 9)
|
||||
#define HCINTMSK_BBLERR (1 << 8)
|
||||
#define HCINTMSK_XACTERR (1 << 7)
|
||||
#define HCINTMSK_NYET (1 << 6)
|
||||
#define HCINTMSK_ACK (1 << 5)
|
||||
#define HCINTMSK_NAK (1 << 4)
|
||||
#define HCINTMSK_STALL (1 << 3)
|
||||
#define HCINTMSK_AHBERR (1 << 2)
|
||||
#define HCINTMSK_CHHLTD (1 << 1)
|
||||
#define HCINTMSK_XFERCOMPL (1 << 0)
|
||||
#define HCINTMSK_FRM_LIST_ROLL BIT(13)
|
||||
#define HCINTMSK_XCS_XACT BIT(12)
|
||||
#define HCINTMSK_BNA BIT(11)
|
||||
#define HCINTMSK_DATATGLERR BIT(10)
|
||||
#define HCINTMSK_FRMOVRUN BIT(9)
|
||||
#define HCINTMSK_BBLERR BIT(8)
|
||||
#define HCINTMSK_XACTERR BIT(7)
|
||||
#define HCINTMSK_NYET BIT(6)
|
||||
#define HCINTMSK_ACK BIT(5)
|
||||
#define HCINTMSK_NAK BIT(4)
|
||||
#define HCINTMSK_STALL BIT(3)
|
||||
#define HCINTMSK_AHBERR BIT(2)
|
||||
#define HCINTMSK_CHHLTD BIT(1)
|
||||
#define HCINTMSK_XFERCOMPL BIT(0)
|
||||
|
||||
#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
|
||||
#define TSIZ_DOPNG (1 << 31)
|
||||
#define TSIZ_DOPNG BIT(31)
|
||||
#define TSIZ_SC_MC_PID_MASK (0x3 << 29)
|
||||
#define TSIZ_SC_MC_PID_SHIFT 29
|
||||
#define TSIZ_SC_MC_PID_DATA0 0
|
||||
@@ -808,14 +808,14 @@ struct dwc2_dma_desc {
|
||||
|
||||
/* Host Mode DMA descriptor status quadlet */
|
||||
|
||||
#define HOST_DMA_A (1 << 31)
|
||||
#define HOST_DMA_A BIT(31)
|
||||
#define HOST_DMA_STS_MASK (0x3 << 28)
|
||||
#define HOST_DMA_STS_SHIFT 28
|
||||
#define HOST_DMA_STS_PKTERR (1 << 28)
|
||||
#define HOST_DMA_EOL (1 << 26)
|
||||
#define HOST_DMA_IOC (1 << 25)
|
||||
#define HOST_DMA_SUP (1 << 24)
|
||||
#define HOST_DMA_ALT_QTD (1 << 23)
|
||||
#define HOST_DMA_STS_PKTERR BIT(28)
|
||||
#define HOST_DMA_EOL BIT(26)
|
||||
#define HOST_DMA_IOC BIT(25)
|
||||
#define HOST_DMA_SUP BIT(24)
|
||||
#define HOST_DMA_ALT_QTD BIT(23)
|
||||
#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
|
||||
#define HOST_DMA_QTD_OFFSET_SHIFT 17
|
||||
#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
|
||||
@@ -837,11 +837,11 @@ struct dwc2_dma_desc {
|
||||
#define DEV_DMA_STS_SUCC 0
|
||||
#define DEV_DMA_STS_BUFF_FLUSH 1
|
||||
#define DEV_DMA_STS_BUFF_ERR 3
|
||||
#define DEV_DMA_L (1 << 27)
|
||||
#define DEV_DMA_SHORT (1 << 26)
|
||||
#define DEV_DMA_IOC (1 << 25)
|
||||
#define DEV_DMA_SR (1 << 24)
|
||||
#define DEV_DMA_MTRF (1 << 23)
|
||||
#define DEV_DMA_L BIT(27)
|
||||
#define DEV_DMA_SHORT BIT(26)
|
||||
#define DEV_DMA_IOC BIT(25)
|
||||
#define DEV_DMA_SR BIT(24)
|
||||
#define DEV_DMA_MTRF BIT(23)
|
||||
#define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
|
||||
#define DEV_DMA_ISOC_PID_SHIFT 23
|
||||
#define DEV_DMA_ISOC_PID_DATA0 0
|
||||
|
||||
Reference in New Issue
Block a user