sh: Mass ctrl_in/outX to __raw_read/writeX conversion.
The old ctrl in/out routines are non-portable and unsuitable for cross-platform use. While drivers/sh has already been sanitized, there is still quite a lot of code that is not. This converts the arch/sh/ bits over, which permits us to flag the routines as deprecated whilst still building with -Werror for the architecture code, and to ensure that future users are not added. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@@ -541,17 +541,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
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void __init plat_irq_setup(void)
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{
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/* disable IRQ3-0 + IRQ7-4 */
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ctrl_outl(0xff000000, INTC_INTMSK0);
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__raw_writel(0xff000000, INTC_INTMSK0);
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/* disable IRL3-0 + IRL7-4 */
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ctrl_outl(0xc0000000, INTC_INTMSK1);
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ctrl_outl(0xfffefffe, INTC_INTMSK2);
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__raw_writel(0xc0000000, INTC_INTMSK1);
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__raw_writel(0xfffefffe, INTC_INTMSK2);
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/* select IRL mode for IRL3-0 + IRL7-4 */
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ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
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__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
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/* disable holding function, ie enable "SH-4 Mode" */
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ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
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__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
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register_intc_controller(&intc_desc);
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}
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@@ -561,32 +561,32 @@ void __init plat_irq_setup_pins(int mode)
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switch (mode) {
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case IRQ_MODE_IRQ7654:
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/* select IRQ mode for IRL7-4 */
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ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
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__raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
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register_intc_controller(&intc_desc_irq4567);
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break;
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case IRQ_MODE_IRQ3210:
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/* select IRQ mode for IRL3-0 */
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ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
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__raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
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register_intc_controller(&intc_desc_irq0123);
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break;
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case IRQ_MODE_IRL7654:
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/* enable IRL7-4 but don't provide any masking */
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ctrl_outl(0x40000000, INTC_INTMSKCLR1);
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ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
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__raw_writel(0x40000000, INTC_INTMSKCLR1);
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__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
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break;
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case IRQ_MODE_IRL3210:
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/* enable IRL0-3 but don't provide any masking */
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ctrl_outl(0x80000000, INTC_INTMSKCLR1);
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ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
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__raw_writel(0x80000000, INTC_INTMSKCLR1);
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__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
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break;
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case IRQ_MODE_IRL7654_MASK:
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/* enable IRL7-4 and mask using cpu intc controller */
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ctrl_outl(0x40000000, INTC_INTMSKCLR1);
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__raw_writel(0x40000000, INTC_INTMSKCLR1);
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register_intc_controller(&intc_desc_irl4567);
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break;
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case IRQ_MODE_IRL3210_MASK:
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/* enable IRL0-3 and mask using cpu intc controller */
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ctrl_outl(0x80000000, INTC_INTMSKCLR1);
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__raw_writel(0x80000000, INTC_INTMSKCLR1);
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register_intc_controller(&intc_desc_irl0123);
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break;
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default:
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