sh: Add support for SH7206 and SH7619 CPU subtypes.
This implements initial support for the SH7206 (SH-2A) and SH7619 (SH-2) MMU-less CPUs. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Yoshinori Sato
committed by
Paul Mundt
Paul Mundt
parent
e62438630c
commit
9d4436a6fb
256
arch/sh/kernel/timers/timer-cmt.c
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256
arch/sh/kernel/timers/timer-cmt.c
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/*
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* arch/sh/kernel/timers/timer-cmt.c - CMT Timer Support
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*
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* Copyright (C) 2005 Yoshinori Sato
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/seqlock.h>
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#include <asm/timer.h>
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#include <asm/rtc.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/clock.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define CMT_CMSTR 0xf84a0070
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#define CMT_CMCSR_0 0xf84a0072
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#define CMT_CMCNT_0 0xf84a0074
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#define CMT_CMCOR_0 0xf84a0076
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#define CMT_CMCSR_1 0xf84a0078
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#define CMT_CMCNT_1 0xf84a007a
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#define CMT_CMCOR_1 0xf84a007c
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#define STBCR3 0xf80a0000
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#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0)
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#define CMT_CMCSR_INIT 0x0040
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#define CMT_CMCSR_CALIB 0x0000
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#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
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#define CMT_CMSTR 0xfffec000
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#define CMT_CMCSR_0 0xfffec002
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#define CMT_CMCNT_0 0xfffec004
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#define CMT_CMCOR_0 0xfffec006
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#define STBCR4 0xfffe040c
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#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR4) & ~0x04, STBCR4); } while(0)
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#define CMT_CMCSR_INIT 0x0040
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#define CMT_CMCSR_CALIB 0x0000
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#else
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#error "Unknown CPU SUBTYPE"
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#endif
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static DEFINE_SPINLOCK(cmt0_lock);
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static unsigned long cmt_timer_get_offset(void)
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{
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int count;
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unsigned long flags;
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static unsigned short count_p = 0xffff; /* for the first call after boot */
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static unsigned long jiffies_p = 0;
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/*
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* cache volatile jiffies temporarily; we have IRQs turned off.
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*/
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unsigned long jiffies_t;
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spin_lock_irqsave(&cmt0_lock, flags);
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/* timer count may underflow right here */
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count = ctrl_inw(CMT_CMCOR_0);
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count -= ctrl_inw(CMT_CMCNT_0);
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jiffies_t = jiffies;
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/*
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* avoiding timer inconsistencies (they are rare, but they happen)...
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* there is one kind of problem that must be avoided here:
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* 1. the timer counter underflows
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*/
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if (jiffies_t == jiffies_p) {
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if (count > count_p) {
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/* the nutcase */
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if (ctrl_inw(CMT_CMCSR_0) & 0x80) { /* Check CMF bit */
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count -= LATCH;
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} else {
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printk("%s (): hardware timer problem?\n",
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__FUNCTION__);
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}
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}
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} else
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jiffies_p = jiffies_t;
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count_p = count;
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spin_unlock_irqrestore(&cmt0_lock, flags);
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count = ((LATCH-1) - count) * TICK_SIZE;
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count = (count + LATCH/2) / LATCH;
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return count;
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}
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static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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unsigned long timer_status;
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/* Clear CMF bit */
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timer_status = ctrl_inw(CMT_CMCSR_0);
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timer_status &= ~0x80;
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ctrl_outw(timer_status, CMT_CMCSR_0);
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/*
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* Here we are in the timer irq handler. We just have irqs locally
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* disabled but we don't know if the timer_bh is running on the other
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* CPU. We need to avoid to SMP race with it. NOTE: we don' t need
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* the irq version of write_lock because as just said we have irq
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* locally disabled. -arca
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*/
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write_seqlock(&xtime_lock);
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handle_timer_tick(regs);
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction cmt_irq = {
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.name = "timer",
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.handler = cmt_timer_interrupt,
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.flags = SA_INTERRUPT,
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.mask = CPU_MASK_NONE,
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};
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/*
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* Hah! We'll see if this works (switching from usecs to nsecs).
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*/
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static unsigned long cmt_timer_get_frequency(void)
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{
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u32 freq;
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struct timespec ts1, ts2;
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unsigned long diff_nsec;
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unsigned long factor;
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/* Setup the timer: We don't want to generate interrupts, just
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* have it count down at its natural rate.
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*/
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ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
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ctrl_outw(CMT_CMCSR_CALIB, CMT_CMCSR_0);
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ctrl_outw(0xffff, CMT_CMCOR_0);
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ctrl_outw(0xffff, CMT_CMCNT_0);
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rtc_sh_get_time(&ts2);
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do {
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rtc_sh_get_time(&ts1);
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} while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
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/* actually start the timer */
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ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
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do {
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rtc_sh_get_time(&ts2);
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} while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
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freq = 0xffff - ctrl_inw(CMT_CMCNT_0);
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if (ts2.tv_nsec < ts1.tv_nsec) {
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ts2.tv_nsec += 1000000000;
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ts2.tv_sec--;
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}
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diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
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/* this should work well if the RTC has a precision of n Hz, where
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* n is an integer. I don't think we have to worry about the other
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* cases. */
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factor = (1000000000 + diff_nsec/2) / diff_nsec;
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if (factor * diff_nsec > 1100000000 ||
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factor * diff_nsec < 900000000)
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panic("weird RTC (diff_nsec %ld)", diff_nsec);
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return freq * factor;
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}
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static void cmt_clk_init(struct clk *clk)
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{
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u8 divisor = CMT_CMCSR_INIT & 0x3;
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ctrl_inw(CMT_CMCSR_0);
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ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0);
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clk->parent = clk_get("module_clk");
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clk->rate = clk->parent->rate / (8 << (divisor << 1));
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}
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static void cmt_clk_recalc(struct clk *clk)
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{
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u8 divisor = ctrl_inw(CMT_CMCSR_0) & 0x3;
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clk->rate = clk->parent->rate / (8 << (divisor << 1));
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}
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static struct clk_ops cmt_clk_ops = {
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.init = cmt_clk_init,
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.recalc = cmt_clk_recalc,
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};
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static struct clk cmt0_clk = {
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.name = "cmt0_clk",
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.ops = &cmt_clk_ops,
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};
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static int cmt_timer_start(void)
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{
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ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
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return 0;
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}
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static int cmt_timer_stop(void)
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{
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ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
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return 0;
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}
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static int cmt_timer_init(void)
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{
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unsigned long interval;
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cmt_clock_enable();
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setup_irq(TIMER_IRQ, &cmt_irq);
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cmt0_clk.parent = clk_get("module_clk");
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cmt_timer_stop();
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interval = cmt0_clk.parent->rate / 8 / HZ;
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printk(KERN_INFO "Interval = %ld\n", interval);
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ctrl_outw(interval, CMT_CMCOR_0);
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clk_register(&cmt0_clk);
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clk_enable(&cmt0_clk);
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cmt_timer_start();
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return 0;
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}
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struct sys_timer_ops cmt_timer_ops = {
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.init = cmt_timer_init,
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.start = cmt_timer_start,
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.stop = cmt_timer_stop,
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.get_frequency = cmt_timer_get_frequency,
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.get_offset = cmt_timer_get_offset,
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};
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struct sys_timer cmt_timer = {
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.name = "cmt",
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.ops = &cmt_timer_ops,
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};
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