Merge branch 'tk_prm_chain_handler_devel_3.3' of git://git.pwsan.com/linux-2.6 into prcm
Conflicts: arch/arm/mach-omap2/Makefile
Этот коммит содержится в:
Tony Lindgren
@@ -195,7 +195,7 @@ static void omap3_save_secure_ram_context(void)
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* that any peripheral wake-up events occurring while attempting to
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* clear the PM_WKST_x are detected and cleared.
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*/
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static int prcm_clear_mod_irqs(s16 module, u8 regs)
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static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
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{
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u32 wkst, fclk, iclk, clken;
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u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
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@@ -207,6 +207,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
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wkst = omap2_prm_read_mod_reg(module, wkst_off);
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wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
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wkst &= ~ignore_bits;
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if (wkst) {
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iclk = omap2_cm_read_mod_reg(module, iclk_off);
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fclk = omap2_cm_read_mod_reg(module, fclk_off);
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@@ -222,6 +223,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
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omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
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omap2_prm_write_mod_reg(wkst, module, wkst_off);
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wkst = omap2_prm_read_mod_reg(module, wkst_off);
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wkst &= ~ignore_bits;
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c++;
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}
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omap2_cm_write_mod_reg(iclk, module, iclk_off);
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@@ -231,76 +233,35 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
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return c;
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}
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static int _prcm_int_handle_wakeup(void)
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static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
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{
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int c;
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c = prcm_clear_mod_irqs(WKUP_MOD, 1);
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c += prcm_clear_mod_irqs(CORE_MOD, 1);
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c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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c += prcm_clear_mod_irqs(CORE_MOD, 3);
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c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
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}
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c = prcm_clear_mod_irqs(WKUP_MOD, 1,
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~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
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return c;
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return c ? IRQ_HANDLED : IRQ_NONE;
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}
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/*
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* PRCM Interrupt Handler
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*
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* The PRM_IRQSTATUS_MPU register indicates if there are any pending
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* interrupts from the PRCM for the MPU. These bits must be cleared in
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* order to clear the PRCM interrupt. The PRCM interrupt handler is
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* implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
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* the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
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* register indicates that a wake-up event is pending for the MPU and
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* this bit can only be cleared if the all the wake-up events latched
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* in the various PM_WKST_x registers have been cleared. The interrupt
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* handler is implemented using a do-while loop so that if a wake-up
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* event occurred during the processing of the prcm interrupt handler
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* (setting a bit in the corresponding PM_WKST_x register and thus
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* preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
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* this would be handled.
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*/
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static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
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static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
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{
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u32 irqenable_mpu, irqstatus_mpu;
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int c = 0;
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int c;
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irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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irqstatus_mpu &= irqenable_mpu;
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/*
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* Clear all except ST_IO and ST_IO_CHAIN for wkup module,
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* these are handled in a separate handler to avoid acking
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* IO events before parsing in mux code
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*/
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c = prcm_clear_mod_irqs(WKUP_MOD, 1,
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OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
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c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
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c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
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if (omap_rev() > OMAP3430_REV_ES1_0) {
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c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
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c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
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}
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do {
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if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
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OMAP3430_IO_ST_MASK)) {
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c = _prcm_int_handle_wakeup();
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/*
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* Is the MPU PRCM interrupt handler racing with the
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* IVA2 PRCM interrupt handler ?
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*/
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WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
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"but no wakeup sources are marked\n");
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} else {
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/* XXX we need to expand our PRCM interrupt handler */
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WARN(1, "prcm: WARNING: PRCM interrupt received, but "
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"no code to handle it (%08x)\n", irqstatus_mpu);
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}
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omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
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irqstatus_mpu &= irqenable_mpu;
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} while (irqstatus_mpu);
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return IRQ_HANDLED;
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return c ? IRQ_HANDLED : IRQ_NONE;
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}
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static void omap34xx_save_context(u32 *save)
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@@ -581,6 +542,7 @@ static int omap3_pm_begin(suspend_state_t state)
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disable_hlt();
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suspend_state = state;
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omap_uart_enable_irqs(0);
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omap_prcm_irq_prepare();
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return 0;
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}
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@@ -592,10 +554,16 @@ static void omap3_pm_end(void)
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return;
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}
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static void omap3_pm_finish(void)
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{
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omap_prcm_irq_complete();
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}
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static const struct platform_suspend_ops omap_pm_ops = {
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.begin = omap3_pm_begin,
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.end = omap3_pm_end,
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.enter = omap3_pm_enter,
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.finish = omap3_pm_finish,
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.valid = suspend_valid_only_mem,
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};
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#endif /* CONFIG_SUSPEND */
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@@ -701,10 +669,6 @@ static void __init prcm_setup_regs(void)
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OMAP3430_GRPSEL_GPT1_MASK |
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OMAP3430_GRPSEL_GPT12_MASK,
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WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
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/* For some reason IO doesn't generate wakeup event even if
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* it is selected to mpu wakeup goup */
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omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
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OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
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/* Enable PM_WKEN to support DSS LPR */
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omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
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@@ -881,12 +845,21 @@ static int __init omap3_pm_init(void)
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* supervised mode for powerdomains */
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prcm_setup_regs();
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ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
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(irq_handler_t)prcm_interrupt_handler,
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IRQF_DISABLED, "prcm", NULL);
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ret = request_irq(omap_prcm_event_to_irq("wkup"),
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_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
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if (ret) {
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printk(KERN_ERR "request_irq failed to register for 0x%x\n",
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INT_34XX_PRCM_MPU_IRQ);
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pr_err("pm: Failed to request pm_wkup irq\n");
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goto err1;
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}
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/* IO interrupt is shared with mux code */
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ret = request_irq(omap_prcm_event_to_irq("io"),
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_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
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omap3_pm_init);
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if (ret) {
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pr_err("pm: Failed to request pm_io irq\n");
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goto err1;
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}
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