Merge tag 'nand/for-4.11' of github.com:linux-nand/linux
From Boris: """ This pull request contains minor fixes/improvements on existing drivers: - sunxi: avoid busy-waiting for NAND events - ifc: fix ECC handling on IFC v1.0 - OX820: add explicit dependency on ARCH_OXNAS in Kconfig - core: add a new manufacture ID and fix a kernel-doc warning - fsmc: kill pdata support - lpc32xx_slc: remove unneeded NULL check """ Conflicts: include/linux/mtd/nand.h [Brian: trivial conflict in the comment section]
This commit is contained in:
Brian Norris
@@ -1,156 +0,0 @@
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/*
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* incude/mtd/fsmc.h
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*
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* ST Microelectronics
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* Flexible Static Memory Controller (FSMC)
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* platform data interface and header file
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*
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* Copyright © 2010 ST Microelectronics
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* Vipin Kumar <vipin.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MTD_FSMC_H
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#define __MTD_FSMC_H
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/types.h>
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#include <linux/mtd/partitions.h>
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#include <asm/param.h>
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#define FSMC_NAND_BW8 1
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#define FSMC_NAND_BW16 2
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#define FSMC_MAX_NOR_BANKS 4
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#define FSMC_MAX_NAND_BANKS 4
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#define FSMC_FLASH_WIDTH8 1
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#define FSMC_FLASH_WIDTH16 2
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/* fsmc controller registers for NOR flash */
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#define CTRL 0x0
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/* ctrl register definitions */
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#define BANK_ENABLE (1 << 0)
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#define MUXED (1 << 1)
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#define NOR_DEV (2 << 2)
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#define WIDTH_8 (0 << 4)
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#define WIDTH_16 (1 << 4)
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#define RSTPWRDWN (1 << 6)
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#define WPROT (1 << 7)
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#define WRT_ENABLE (1 << 12)
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#define WAIT_ENB (1 << 13)
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#define CTRL_TIM 0x4
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/* ctrl_tim register definitions */
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#define FSMC_NOR_BANK_SZ 0x8
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#define FSMC_NOR_REG_SIZE 0x40
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#define FSMC_NOR_REG(base, bank, reg) (base + \
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FSMC_NOR_BANK_SZ * (bank) + \
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reg)
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/* fsmc controller registers for NAND flash */
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#define PC 0x00
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/* pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1)
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#define FSMC_TCLR_SHIFT (9)
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#define FSMC_TCLR_MASK (0xF)
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#define FSMC_TAR_1 (1)
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#define FSMC_TAR_SHIFT (13)
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#define FSMC_TAR_MASK (0xF)
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#define STS 0x04
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/* sts register definitions */
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#define FSMC_CODE_RDY (1 << 15)
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#define COMM 0x08
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/* comm register definitions */
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#define FSMC_TSET_0 0
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#define FSMC_TSET_SHIFT 0
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#define FSMC_TSET_MASK 0xFF
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#define FSMC_TWAIT_6 6
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#define FSMC_TWAIT_SHIFT 8
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#define FSMC_TWAIT_MASK 0xFF
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#define FSMC_THOLD_4 4
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#define FSMC_THOLD_SHIFT 16
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#define FSMC_THOLD_MASK 0xFF
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#define FSMC_THIZ_1 1
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#define FSMC_THIZ_SHIFT 24
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#define FSMC_THIZ_MASK 0xFF
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#define ATTRIB 0x0C
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#define IOATA 0x10
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#define ECC1 0x14
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#define ECC2 0x18
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#define ECC3 0x1C
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#define FSMC_NAND_BANK_SZ 0x20
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#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
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(FSMC_NAND_BANK_SZ * (bank)) + \
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reg)
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#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
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struct fsmc_nand_timings {
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uint8_t tclr;
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uint8_t tar;
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uint8_t thiz;
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uint8_t thold;
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uint8_t twait;
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uint8_t tset;
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};
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enum access_mode {
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USE_DMA_ACCESS = 1,
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USE_WORD_ACCESS,
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};
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/**
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* fsmc_nand_platform_data - platform specific NAND controller config
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* @nand_timings: timing setup for the physical NAND interface
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* @partitions: partition table for the platform, use a default fallback
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* if this is NULL
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* @nr_partitions: the number of partitions in the previous entry
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* @options: different options for the driver
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* @width: bus width
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* @bank: default bank
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* @select_bank: callback to select a certain bank, this is
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* platform-specific. If the controller only supports one bank
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* this may be set to NULL
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*/
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struct fsmc_nand_platform_data {
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struct fsmc_nand_timings *nand_timings;
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struct mtd_partition *partitions;
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unsigned int nr_partitions;
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unsigned int options;
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unsigned int width;
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unsigned int bank;
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enum access_mode mode;
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void (*select_bank)(uint32_t bank, uint32_t busw);
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/* priv structures for dma accesses */
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void *read_dma_priv;
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void *write_dma_priv;
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};
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extern int __init fsmc_nor_init(struct platform_device *pdev,
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unsigned long base, uint32_t bank, uint32_t width);
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extern void __init fsmc_init_board_info(struct platform_device *pdev,
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struct mtd_partition *partitions, unsigned int nr_partitions,
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unsigned int width);
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#endif /* __MTD_FSMC_H */
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@@ -615,7 +615,7 @@ struct nand_buffers {
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* @tALS_min: ALE setup time
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* @tAR_min: ALE to RE# delay
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* @tCEA_max: CE# access time
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* @tCEH_min:
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* @tCEH_min: CE# high hold time
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* @tCH_min: CE# hold time
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* @tCHZ_max: CE# high to output hi-Z
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* @tCLH_min: CLE hold time
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@@ -804,6 +804,7 @@ nand_get_sdr_timings(const struct nand_data_interface *conf)
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* @max_bb_per_die: [INTERN] the max number of bad blocks each die of a
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* this nand device will encounter their life times.
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* @blocks_per_die: [INTERN] The number of PEBs in a die
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* @data_interface: [INTERN] NAND interface timing information
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* @read_retries: [INTERN] the number of read retry modes supported
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* @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
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* @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
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@@ -963,6 +964,7 @@ static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
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#define NAND_MFR_SANDISK 0x45
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#define NAND_MFR_INTEL 0x89
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#define NAND_MFR_ATO 0x9b
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#define NAND_MFR_WINBOND 0xef
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/* The maximum expected count of bytes in the NAND ID sequence */
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#define NAND_MAX_ID_LEN 8
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