Merge branch 'clk-fixes' into clk-next
* clk-fixes: clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM dt-bindings: clock: sunxi-ccu: Add pll-periph to PRCM's needed clocks clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM clk: sunxi-ng: v3s: Fix usb otg device reset bit clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset
This commit is contained in:
@@ -43,6 +43,8 @@
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
|
||||
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
|
||||
|
||||
#define CLK_PLL_PERIPH0 11
|
||||
|
||||
#define CLK_BUS_MIPI_DSI 28
|
||||
#define CLK_BUS_CE 29
|
||||
#define CLK_BUS_DMA 30
|
||||
|
@@ -43,6 +43,8 @@
|
||||
#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
|
||||
#define _DT_BINDINGS_CLK_SUN8I_H3_H_
|
||||
|
||||
#define CLK_PLL_PERIPH0 9
|
||||
|
||||
#define CLK_CPUX 14
|
||||
|
||||
#define CLK_BUS_CE 20
|
||||
|
Reference in New Issue
Block a user