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ARM: arm-soc: Merge branch 'next/pm2' into next/pm

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Another smaller branch merged into next/pm before pull request.

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2012-12-12 16:10:45 -08:00
parent 4a76411ea3 48d224d1ef
commit 9c7466b217
893 changed files with 18629 additions and 7785 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/mach-omap2/Makefile
View File

@@ -5,7 +5,7 @@
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
omap_device.o
omap_device.o sram.o
omap-2-3-common = irq.o
hwmod-common = omap_hwmod.o \
@@ -73,6 +73,8 @@ obj-$(CONFIG_ARCH_OMAP4) += opp4xxx_data.o
endif
# Power Management
obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o

1
arch/arm/mach-omap2/board-2430sdp.c
View File

@@ -28,7 +28,6 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>

2
arch/arm/mach-omap2/board-3430sdp.c
View File

@@ -31,7 +31,7 @@
#include <asm/mach/map.h>
#include "common.h"
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include <video/omapdss.h>
#include <video/omap-panel-tfp410.h>

2
arch/arm/mach-omap2/board-cm-t35.c
View File

@@ -44,8 +44,6 @@
#include <video/omap-panel-tfp410.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <mach/hardware.h>
#include "common.h"
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"

2
arch/arm/mach-omap2/board-cm-t3517.c
View File

@@ -297,6 +297,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
.handle_irq = omap3_intc_handle_irq,
.init_machine = cm_t3517_init,
.init_late = am35xx_init_late,
.timer = &omap3_timer,
.timer = &omap3_gp_timer,
.restart = omap3xxx_restart,
MACHINE_END

17
arch/arm/mach-omap2/board-generic.c
View File

@@ -97,6 +97,23 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
.dt_compat = omap3_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
static const char *omap3_gp_boards_compat[] __initdata = {
"ti,omap3-beagle",
NULL,
};
DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3430_init_early,
.init_irq = omap_intc_of_init,
.handle_irq = omap3_intc_handle_irq,
.init_machine = omap_generic_init,
.timer = &omap3_secure_timer,
.dt_compat = omap3_gp_boards_compat,
.restart = omap3xxx_restart,
MACHINE_END
#endif
#ifdef CONFIG_SOC_AM33XX

4
arch/arm/mach-omap2/board-h4.c
View File

@@ -32,8 +32,8 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat-omap/dma-omap.h>
#include "debug-devices.h"
#include <linux/omap-dma.h>
#include <plat/debug-devices.h>
#include <video/omapdss.h>
#include <video/omap-panel-generic-dpi.h>

5
arch/arm/mach-omap2/board-igep0020.c
View File

@@ -579,6 +579,11 @@ static void __init igep_wlan_bt_init(void)
} else
return;
/* Make sure that the GPIO pins are muxed correctly */
omap_mux_init_gpio(igep_wlan_bt_gpios[0].gpio, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(igep_wlan_bt_gpios[1].gpio, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(igep_wlan_bt_gpios[2].gpio, OMAP_PIN_OUTPUT);
err = gpio_request_array(igep_wlan_bt_gpios,
ARRAY_SIZE(igep_wlan_bt_gpios));
if (err) {

1
arch/arm/mach-omap2/board-overo.c
View File

@@ -45,7 +45,6 @@
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include "common.h"
#include <video/omapdss.h>
#include <video/omap-panel-generic-dpi.h>
#include <video/omap-panel-tfp410.h>

2
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@@ -31,7 +31,7 @@
#include <asm/system_info.h>
#include "common.h"
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include "gpmc-smc91x.h"
#include "board-rx51.h"

2
arch/arm/mach-omap2/board-rx51.c
View File

@@ -24,7 +24,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include "common.h"
#include "mux.h"

3
arch/arm/mach-omap2/clkt2xxx_dpllcore.c
View File

@@ -25,14 +25,13 @@
#include <linux/clk.h>
#include <linux/io.h>
#include "../plat-omap/sram.h"
#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
#include "cm2xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "sram.h"
/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */

3
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
View File

@@ -33,8 +33,6 @@
#include <linux/cpufreq.h>
#include <linux/slab.h>
#include "../plat-omap/sram.h"
#include "soc.h"
#include "clock.h"
#include "clock2xxx.h"
@@ -42,6 +40,7 @@
#include "cm2xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "sram.h"
const struct prcm_config *curr_prcm_set;
const struct prcm_config *rate_table;

3
arch/arm/mach-omap2/clkt34xx_dpll3m2.c
View File

@@ -21,12 +21,11 @@
#include <linux/clk.h>
#include <linux/io.h>
#include "../plat-omap/sram.h"
#include "clock.h"
#include "clock3xxx.h"
#include "clock34xx.h"
#include "sdrc.h"
#include "sram.h"
#define CYCLES_PER_MHZ 1000000

2
arch/arm/mach-omap2/cm33xx.c
View File

@@ -22,8 +22,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include "../plat-omap/common.h"
#include "clockdomain.h"
#include "cm.h"
#include "cm33xx.h"

1
arch/arm/mach-omap2/cm_common.c
View File

@@ -13,6 +13,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include "cm2xxx.h"
#include "cm3xxx.h"

34
arch/arm/mach-omap2/common-board-devices.c
View File

@@ -63,30 +63,36 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
struct spi_board_info *spi_bi = &ads7846_spi_board_info;
int err;
err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
if (err) {
pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
return;
}
/*
* If a board defines get_pendown_state() function, request the pendown
* GPIO and set the GPIO debounce time.
* If a board does not define the get_pendown_state() function, then
* the ads7846 driver will setup the pendown GPIO itself.
*/
if (board_pdata && board_pdata->get_pendown_state) {
err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
if (err) {
pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
return;
}
if (gpio_debounce)
gpio_set_debounce(gpio_pendown, gpio_debounce);
if (gpio_debounce)
gpio_set_debounce(gpio_pendown, gpio_debounce);
gpio_export(gpio_pendown, 0);
}
spi_bi->bus_num = bus_num;
spi_bi->irq = gpio_to_irq(gpio_pendown);
ads7846_config.gpio_pendown = gpio_pendown;
if (board_pdata) {
board_pdata->gpio_pendown = gpio_pendown;
board_pdata->gpio_pendown_debounce = gpio_debounce;
spi_bi->platform_data = board_pdata;
if (board_pdata->get_pendown_state)
gpio_export(gpio_pendown, 0);
} else {
ads7846_config.gpio_pendown = gpio_pendown;
}
if (!board_pdata || (board_pdata && !board_pdata->get_pendown_state))
gpio_free(gpio_pendown);
spi_register_board_info(&ads7846_spi_board_info, 1);
}
#else

6
arch/arm/mach-omap2/common.h
View File

@@ -34,8 +34,6 @@
#include <asm/proc-fns.h>
#include "../plat-omap/common.h"
#include "i2c.h"
#include "serial.h"
@@ -84,6 +82,7 @@ extern void omap2_init_common_infrastructure(void);
extern struct sys_timer omap2_timer;
extern struct sys_timer omap3_timer;
extern struct sys_timer omap3_secure_timer;
extern struct sys_timer omap3_gp_timer;
extern struct sys_timer omap3_am33xx_timer;
extern struct sys_timer omap4_timer;
extern struct sys_timer omap5_timer;
@@ -280,5 +279,8 @@ struct omap2_hsmmc_info;
extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
extern void omap_reserve(void);
struct omap_hwmod;
extern int omap_dss_reset(struct omap_hwmod *);
#endif /* __ASSEMBLER__ */
#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */

9
arch/arm/mach-omap2/debug-devices.h
View File

@@ -1,9 +0,0 @@
#ifndef _OMAP_DEBUG_DEVICES_H
#define _OMAP_DEBUG_DEVICES_H
#include <linux/types.h>
/* for TI reference platforms sharing the same debug card */
extern int debug_card_init(u32 addr, unsigned gpio);
#endif

2
arch/arm/mach-omap2/devices.c
View File

@@ -24,7 +24,7 @@
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include "iomap.h"
#include "omap_hwmod.h"

5
arch/arm/mach-omap2/dma.c
View File

@@ -28,7 +28,7 @@
#include <linux/init.h>
#include <linux/device.h>
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include "soc.h"
#include "omap_hwmod.h"
@@ -276,6 +276,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
return -ENOMEM;
}
if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
d->dev_caps |= HS_CHANNELS_RESERVED;
/* Check the capabilities register for descriptor loading feature */
if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
dma_common_ch_end = CCDN;

1
arch/arm/mach-omap2/hsmmc.c
View File

@@ -14,7 +14,6 @@
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <linux/platform_data/gpio-omap.h>
#include "soc.h"

16
arch/arm/mach-omap2/i2c.c
View File

@@ -107,6 +107,19 @@ int omap_i2c_reset(struct omap_hwmod *oh)
return 0;
}
static int __init omap_i2c_nr_ports(void)
{
int ports = 0;
if (cpu_is_omap24xx())
ports = 2;
else if (cpu_is_omap34xx())
ports = 3;
else if (cpu_is_omap44xx())
ports = 4;
return ports;
}
static const char name[] = "omap_i2c";
int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
@@ -119,6 +132,9 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
struct omap_i2c_bus_platform_data *pdata;
struct omap_i2c_dev_attr *dev_attr;
if (bus_id > omap_i2c_nr_ports())
return -EINVAL;
omap2_i2c_mux_pins(bus_id);
l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);

2
arch/arm/mach-omap2/i2c.h
View File

@@ -19,7 +19,7 @@
*
*/
#include "../plat-omap/i2c.h"
#include <plat/i2c.h>
#ifndef __MACH_OMAP2_I2C_H
#define __MACH_OMAP2_I2C_H

25
arch/arm/mach-omap2/id.c
View File

@@ -28,6 +28,9 @@
#include "soc.h"
#include "control.h"
#define OMAP4_SILICON_TYPE_STANDARD 0x01
#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
static unsigned int omap_revision;
static const char *cpu_rev;
u32 omap_features;
@@ -273,25 +276,11 @@ void __init omap4xxx_check_features(void)
{
u32 si_type;
if (cpu_is_omap443x())
omap_features |= OMAP4_HAS_MPU_1GHZ;
si_type =
(read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
if (cpu_is_omap446x()) {
si_type =
read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
switch ((si_type & (3 << 16)) >> 16) {
case 2:
/* High performance device */
omap_features |= OMAP4_HAS_MPU_1_5GHZ;
break;
case 1:
default:
/* Standard device */
omap_features |= OMAP4_HAS_MPU_1_2GHZ;
break;
}
}
if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
omap_features = OMAP4_HAS_PERF_SILICON;
}
void __init ti81xx_check_features(void)

2
arch/arm/mach-omap2/include/mach/debug-macro.S
View File

@@ -13,7 +13,7 @@
#include <linux/serial_reg.h>
#include <../mach-omap2/serial.h>
#include <mach/serial.h>
#define UART_OFFSET(addr) ((addr) & 0x00ffffff)

3
arch/arm/mach-omap2/include/mach/gpio.h
View File

@@ -1,3 +0,0 @@
/*
* arch/arm/mach-omap2/include/mach/gpio.h
*/

103
arch/arm/mach-omap2/include/mach/serial.h Normal file
View File

@@ -0,0 +1,103 @@
/*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Memory entry used for the DEBUG_LL UART configuration, relative to
* start of RAM. See also uncompress.h and debug-macro.S.
*
* Note that using a memory location for storing the UART configuration
* has at least two limitations:
*
* 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
* uncompress code could then partially overwrite itself
* 2. We assume printascii is called at least once before paging_init,
* and addruart has a chance to read OMAP_UART_INFO
*/
#define OMAP_UART_INFO_OFS 0x3ffc
/* OMAP2 serial ports */
#define OMAP2_UART1_BASE 0x4806a000
#define OMAP2_UART2_BASE 0x4806c000
#define OMAP2_UART3_BASE 0x4806e000
/* OMAP3 serial ports */
#define OMAP3_UART1_BASE OMAP2_UART1_BASE
#define OMAP3_UART2_BASE OMAP2_UART2_BASE
#define OMAP3_UART3_BASE 0x49020000
#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
/* OMAP4 serial ports */
#define OMAP4_UART1_BASE OMAP2_UART1_BASE
#define OMAP4_UART2_BASE OMAP2_UART2_BASE
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
/* TI81XX serial ports */
#define TI81XX_UART1_BASE 0x48020000
#define TI81XX_UART2_BASE 0x48022000
#define TI81XX_UART3_BASE 0x48024000
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
/* AM33XX serial port */
#define AM33XX_UART1_BASE 0x44E09000
/* OMAP5 serial ports */
#define OMAP5_UART1_BASE OMAP2_UART1_BASE
#define OMAP5_UART2_BASE OMAP2_UART2_BASE
#define OMAP5_UART3_BASE OMAP4_UART3_BASE
#define OMAP5_UART4_BASE OMAP4_UART4_BASE
#define OMAP5_UART5_BASE 0x48066000
#define OMAP5_UART6_BASE 0x48068000
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
#define OMAP_PORT_SHIFT 2
#define ZOOM_PORT_SHIFT 1
#define OMAP24XX_BASE_BAUD (48000000/16)
/*
* DEBUG_LL port encoding stored into the UART1 scratchpad register by
* decomp_setup in uncompress.h
*/
#define OMAP2UART1 21
#define OMAP2UART2 22
#define OMAP2UART3 23
#define OMAP3UART1 OMAP2UART1
#define OMAP3UART2 OMAP2UART2
#define OMAP3UART3 33
#define OMAP3UART4 34 /* Only on 36xx */
#define OMAP4UART1 OMAP2UART1
#define OMAP4UART2 OMAP2UART2
#define OMAP4UART3 43
#define OMAP4UART4 44
#define TI81XXUART1 81
#define TI81XXUART2 82
#define TI81XXUART3 83
#define AM33XXUART1 84
#define OMAP5UART3 OMAP4UART3
#define OMAP5UART4 OMAP4UART4
#define ZOOM_UART 95 /* Only on zoom2/3 */
#ifndef __ASSEMBLER__
struct omap_board_data;
struct omap_uart_port_info;
extern void omap_serial_init(void);
extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
extern void omap_serial_init_port(struct omap_board_data *bdata,
struct omap_uart_port_info *platform_data);
#endif

2
arch/arm/mach-omap2/include/mach/uncompress.h
View File

@@ -23,7 +23,7 @@
#include <asm/memory.h>
#include <asm/mach-types.h>
#include <../mach-omap2/serial.h>
#include <mach/serial.h>
#define MDR1_MODE_MASK 0x07

25
arch/arm/mach-omap2/io.c
View File

@@ -25,9 +25,7 @@
#include <asm/tlb.h>
#include <asm/mach/map.h>
#include <plat-omap/dma-omap.h>
#include "../plat-omap/sram.h"
#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "soc.h"
@@ -44,6 +42,7 @@
#include "sdrc.h"
#include "control.h"
#include "serial.h"
#include "sram.h"
#include "cm2xxx.h"
#include "cm3xxx.h"
#include "prm.h"
@@ -51,6 +50,10 @@
#include "prcm_mpu44xx.h"
#include "prminst44xx.h"
#include "cminst44xx.h"
#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm44xx.h"
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
@@ -361,11 +364,6 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}
static void __init omap_common_init_early(void)
{
omap_init_consistent_dma_size();
}
static void __init omap_hwmod_init_postsetup(void)
{
u8 postsetup_state;
@@ -392,8 +390,8 @@ void __init omap2420_init_early(void)
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
omap2xxx_check_revision();
omap2xxx_prm_init();
omap2xxx_cm_init();
omap_common_init_early();
omap2xxx_voltagedomains_init();
omap242x_powerdomains_init();
omap242x_clockdomains_init();
@@ -422,8 +420,8 @@ void __init omap2430_init_early(void)
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
omap2xxx_check_revision();
omap2xxx_prm_init();
omap2xxx_cm_init();
omap_common_init_early();
omap2xxx_voltagedomains_init();
omap243x_powerdomains_init();
omap243x_clockdomains_init();
@@ -457,8 +455,8 @@ void __init omap3_init_early(void)
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
omap3xxx_check_revision();
omap3xxx_check_features();
omap3xxx_prm_init();
omap3xxx_cm_init();
omap_common_init_early();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap3xxx_clockdomains_init();
@@ -497,7 +495,6 @@ void __init ti81xx_init_early(void)
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
ti81xx_check_features();
omap_common_init_early();
omap3xxx_voltagedomains_init();
omap3xxx_powerdomains_init();
omap3xxx_clockdomains_init();
@@ -566,7 +563,6 @@ void __init am33xx_init_early(void)
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
ti81xx_check_features();
omap_common_init_early();
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
@@ -591,7 +587,7 @@ void __init omap4430_init_early(void)
omap_cm_base_init();
omap4xxx_check_revision();
omap4xxx_check_features();
omap_common_init_early();
omap44xx_prm_init();
omap44xx_voltagedomains_init();
omap44xx_powerdomains_init();
omap44xx_clockdomains_init();
@@ -623,7 +619,6 @@ void __init omap5_init_early(void)
omap_prm_base_init();
omap_cm_base_init();
omap5xxx_check_revision();
omap_common_init_early();
}
#endif

2
arch/arm/mach-omap2/mcbsp.c
View File

@@ -21,7 +21,7 @@
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/pm_runtime.h>
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include "omap_device.h"

371
arch/arm/mach-omap2/omap-pm-noop.c Normal file
View File

@@ -0,0 +1,371 @@
/*
* omap-pm-noop.c - OMAP power management interface - dummy version
*
* This code implements the OMAP power management interface to
* drivers, CPUIdle, CPUFreq, and DSP Bridge. It is strictly for
* debug/demonstration use, as it does nothing but printk() whenever a
* function is called (when DEBUG is defined, below)
*
* Copyright (C) 2008-2009 Texas Instruments, Inc.
* Copyright (C) 2008-2009 Nokia Corporation
* Paul Walmsley
*
* Interface developed by (in alphabetical order):
* Karthik Dasu, Tony Lindgren, Rajendra Nayak, Sakari Poussa, Veeramanikandan
* Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, Richard Woodruff
*/
#undef DEBUG
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include "omap_device.h"
#include "omap-pm.h"
static bool off_mode_enabled;
static int dummy_context_loss_counter;
/*
* Device-driver-originated constraints (via board-*.c files)
*/
int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
{
if (!dev || t < -1) {
WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
return -EINVAL;
}
if (t == -1)
pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n",
dev_name(dev));
else
pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n",
dev_name(dev), t);
/*
* For current Linux, this needs to map the MPU to a
* powerdomain, then go through the list of current max lat
* constraints on the MPU and find the smallest. If
* the latency constraint has changed, the code should
* recompute the state to enter for the next powerdomain
* state.
*
* TI CDP code can call constraint_set here.
*/
return 0;
}
int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
{
if (!dev || (agent_id != OCP_INITIATOR_AGENT &&
agent_id != OCP_TARGET_AGENT)) {
WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
return -EINVAL;
}
if (r == 0)
pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n",
dev_name(dev), agent_id);
else
pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n",
dev_name(dev), agent_id, r);
/*
* This code should model the interconnect and compute the
* required clock frequency, convert that to a VDD2 OPP ID, then
* set the VDD2 OPP appropriately.
*
* TI CDP code can call constraint_set here on the VDD2 OPP.
*/
return 0;
}
int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
long t)
{
if (!req_dev || !dev || t < -1) {
WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
return -EINVAL;
}
if (t == -1)
pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
dev_name(dev));
else
pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
dev_name(dev), t);
/*
* For current Linux, this needs to map the device to a
* powerdomain, then go through the list of current max lat
* constraints on that powerdomain and find the smallest. If
* the latency constraint has changed, the code should
* recompute the state to enter for the next powerdomain
* state. Conceivably, this code should also determine
* whether to actually disable the device clocks or not,
* depending on how long it takes to re-enable the clocks.
*
* TI CDP code can call constraint_set here.
*/
return 0;
}
int omap_pm_set_max_sdma_lat(struct device *dev, long t)
{
if (!dev || t < -1) {
WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
return -EINVAL;
}
if (t == -1)
pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
dev_name(dev));
else
pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
dev_name(dev), t);
/*
* For current Linux PM QOS params, this code should scan the
* list of maximum CPU and DMA latencies and select the
* smallest, then set cpu_dma_latency pm_qos_param
* accordingly.
*
* For future Linux PM QOS params, with separate CPU and DMA
* latency params, this code should just set the dma_latency param.
*
* TI CDP code can call constraint_set here.
*/
return 0;
}
int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
{
if (!dev || !c || r < 0) {
WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
return -EINVAL;
}
if (r == 0)
pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
dev_name(dev));
else
pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
dev_name(dev), r);
/*
* Code in a real implementation should keep track of these
* constraints on the clock, and determine the highest minimum
* clock rate. It should iterate over each OPP and determine
* whether the OPP will result in a clock rate that would
* satisfy this constraint (and any other PM constraint in effect
* at that time). Once it finds the lowest-voltage OPP that
* meets those conditions, it should switch to it, or return
* an error if the code is not capable of doing so.
*/
return 0;
}
/*
* DSP Bridge-specific constraints
*/
const struct omap_opp *omap_pm_dsp_get_opp_table(void)
{
pr_debug("OMAP PM: DSP request for OPP table\n");
/*
* Return DSP frequency table here: The final item in the
* array should have .rate = .opp_id = 0.
*/
return NULL;
}
void omap_pm_dsp_set_min_opp(u8 opp_id)
{
if (opp_id == 0) {
WARN_ON(1);
return;
}
pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
/*
*
* For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
* can just test to see which is higher, the CPU's desired OPP
* ID or the DSP's desired OPP ID, and use whichever is
* highest.
*
* In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
* rate is keyed on MPU speed, not the OPP ID. So we need to
* map the OPP ID to the MPU speed for use with clk_set_rate()
* if it is higher than the current OPP clock rate.
*
*/
}
u8 omap_pm_dsp_get_opp(void)
{
pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
/*
* For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
*
* CDP12.14+:
* Call clk_get_rate() on the OPP custom clock, map that to an
* OPP ID using the tables defined in board-*.c/chip-*.c files.
*/
return 0;
}
/*
* CPUFreq-originated constraint
*
* In the future, this should be handled by custom OPP clocktype
* functions.
*/
struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
{
pr_debug("OMAP PM: CPUFreq request for frequency table\n");
/*
* Return CPUFreq frequency table here: loop over
* all VDD1 clkrates, pull out the mpu_ck frequencies, build
* table
*/
return NULL;
}
void omap_pm_cpu_set_freq(unsigned long f)
{
if (f == 0) {
WARN_ON(1);
return;
}
pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
f);
/*
* For l-o dev tree, determine whether MPU freq or DSP OPP id
* freq is higher. Find the OPP ID corresponding to the
* higher frequency. Call clk_round_rate() and clk_set_rate()
* on the OPP custom clock.
*
* CDP should just be able to set the VDD1 OPP clock rate here.
*/
}
unsigned long omap_pm_cpu_get_freq(void)
{
pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
/*
* Call clk_get_rate() on the mpu_ck.
*/
return 0;
}
/**
* omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled
*
* Intended for use only by OMAP PM core code to notify this layer
* that off mode has been enabled.
*/
void omap_pm_enable_off_mode(void)
{
off_mode_enabled = true;
}
/**
* omap_pm_disable_off_mode - notify OMAP PM that off-mode is disabled
*
* Intended for use only by OMAP PM core code to notify this layer
* that off mode has been disabled.
*/
void omap_pm_disable_off_mode(void)
{
off_mode_enabled = false;
}
/*
* Device context loss tracking
*/
#ifdef CONFIG_ARCH_OMAP2PLUS
int omap_pm_get_dev_context_loss_count(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
int count;
if (WARN_ON(!dev))
return -ENODEV;
if (dev->pm_domain == &omap_device_pm_domain) {
count = omap_device_get_context_loss_count(pdev);
} else {
WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device",
dev_name(dev));
count = dummy_context_loss_counter;
if (off_mode_enabled) {
count++;
/*
* Context loss count has to be a non-negative value.
* Clear the sign bit to get a value range from 0 to
* INT_MAX.
*/
count &= INT_MAX;
dummy_context_loss_counter = count;
}
}
pr_debug("OMAP PM: context loss count for dev %s = %d\n",
dev_name(dev), count);
return count;
}
#else
int omap_pm_get_dev_context_loss_count(struct device *dev)
{
return dummy_context_loss_counter;
}
#endif
/* Should be called before clk framework init */
int __init omap_pm_if_early_init(void)
{
return 0;
}
/* Must be called after clock framework is initialized */
int __init omap_pm_if_init(void)
{
return 0;
}
void omap_pm_if_exit(void)
{
/* Deallocate CPUFreq frequency table here */
}

3
arch/arm/mach-omap2/omap4-common.c
View File

@@ -25,8 +25,6 @@
#include <asm/mach/map.h>
#include <asm/memblock.h>
#include "../plat-omap/sram.h"
#include "omap-wakeupgen.h"
#include "soc.h"
#include "iomap.h"
@@ -37,6 +35,7 @@
#include "prcm_mpu44xx.h"
#include "omap4-sar-layout.h"
#include "omap-secure.h"
#include "sram.h"
#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2cache_base;

87
arch/arm/mach-omap2/omap_device.c
View File

@@ -441,19 +441,21 @@ int omap_device_get_context_loss_count(struct platform_device *pdev)
/**
* omap_device_count_resources - count number of struct resource entries needed
* @od: struct omap_device *
* @flags: Type of resources to include when counting (IRQ/DMA/MEM)
*
* Count the number of struct resource entries needed for this
* omap_device @od. Used by omap_device_build_ss() to determine how
* much memory to allocate before calling
* omap_device_fill_resources(). Returns the count.
*/
static int omap_device_count_resources(struct omap_device *od)
static int omap_device_count_resources(struct omap_device *od,
unsigned long flags)
{
int c = 0;
int i;
for (i = 0; i < od->hwmods_cnt; i++)
c += omap_hwmod_count_resources(od->hwmods[i]);
c += omap_hwmod_count_resources(od->hwmods[i], flags);
pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
od->pdev->name, c, od->hwmods_cnt);
@@ -557,52 +559,73 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
od->hwmods = hwmods;
od->pdev = pdev;
res_count = omap_device_count_resources(od);
/*
* Non-DT Boot:
* Here, pdev->num_resources = 0, and we should get all the
* resources from hwmod.
*
* DT Boot:
* OF framework will construct the resource structure (currently
* does for MEM & IRQ resource) and we should respect/use these
* resources, killing hwmod dependency.
* If pdev->num_resources > 0, we assume that MEM & IRQ resources
* have been allocated by OF layer already (through DTB).
*
* Non-DT Boot:
* Here, pdev->num_resources = 0, and we should get all the
* resources from hwmod.
* As preparation for the future we examine the OF provided resources
* to see if we have DMA resources provided already. In this case
* there is no need to update the resources for the device, we use the
* OF provided ones.
*
* TODO: Once DMA resource is available from OF layer, we should
* kill filling any resources from hwmod.
*/
if (res_count > pdev->num_resources) {
/* Allocate resources memory to account for new resources */
res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
if (!res)
goto oda_exit3;
if (!pdev->num_resources) {
/* Count all resources for the device */
res_count = omap_device_count_resources(od, IORESOURCE_IRQ |
IORESOURCE_DMA |
IORESOURCE_MEM);
} else {
/* Take a look if we already have DMA resource via DT */
for (i = 0; i < pdev->num_resources; i++) {
struct resource *r = &pdev->resource[i];
/*
* If pdev->num_resources > 0, then assume that,
* MEM and IRQ resources will only come from DT and only
* fill DMA resource from hwmod layer.
*/
if (pdev->num_resources && pdev->resource) {
dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
__func__, res_count);
memcpy(res, pdev->resource,
sizeof(struct resource) * pdev->num_resources);
_od_fill_dma_resources(od, &res[pdev->num_resources]);
} else {
dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
__func__, res_count);
omap_device_fill_resources(od, res);
/* We have it, no need to touch the resources */
if (r->flags == IORESOURCE_DMA)
goto have_everything;
}
/* Count only DMA resources for the device */
res_count = omap_device_count_resources(od, IORESOURCE_DMA);
/* The device has no DMA resource, no need for update */
if (!res_count)
goto have_everything;
ret = platform_device_add_resources(pdev, res, res_count);
kfree(res);
if (ret)
goto oda_exit3;
res_count += pdev->num_resources;
}
/* Allocate resources memory to account for new resources */
res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
if (!res)
goto oda_exit3;
if (!pdev->num_resources) {
dev_dbg(&pdev->dev, "%s: using %d resources from hwmod\n",
__func__, res_count);
omap_device_fill_resources(od, res);
} else {
dev_dbg(&pdev->dev,
"%s: appending %d DMA resources from hwmod\n",
__func__, res_count - pdev->num_resources);
memcpy(res, pdev->resource,
sizeof(struct resource) * pdev->num_resources);
_od_fill_dma_resources(od, &res[pdev->num_resources]);
}
ret = platform_device_add_resources(pdev, res, res_count);
kfree(res);
if (ret)
goto oda_exit3;
have_everything:
if (!pm_lats) {
pm_lats = omap_default_latency;
pm_lats_cnt = ARRAY_SIZE(omap_default_latency);

82
arch/arm/mach-omap2/omap_hwmod.c
View File

@@ -187,6 +187,8 @@ struct omap_hwmod_soc_ops {
int (*is_hardreset_asserted)(struct omap_hwmod *oh,
struct omap_hwmod_rst_info *ohri);
int (*init_clkdm)(struct omap_hwmod *oh);
void (*update_context_lost)(struct omap_hwmod *oh);
int (*get_context_lost)(struct omap_hwmod *oh);
};
/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
@@ -2014,6 +2016,42 @@ static void _reconfigure_io_chain(void)
spin_unlock_irqrestore(&io_chain_lock, flags);
}
/**
* _omap4_update_context_lost - increment hwmod context loss counter if
* hwmod context was lost, and clear hardware context loss reg
* @oh: hwmod to check for context loss
*
* If the PRCM indicates that the hwmod @oh lost context, increment
* our in-memory context loss counter, and clear the RM_*_CONTEXT
* bits. No return value.
*/
static void _omap4_update_context_lost(struct omap_hwmod *oh)
{
if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT)
return;
if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.context_offs))
return;
oh->prcm.omap4.context_lost_counter++;
prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition,
oh->clkdm->pwrdm.ptr->prcm_offs,
oh->prcm.omap4.context_offs);
}
/**
* _omap4_get_context_lost - get context loss counter for a hwmod
* @oh: hwmod to get context loss counter for
*
* Returns the in-memory context loss counter for a hwmod.
*/
static int _omap4_get_context_lost(struct omap_hwmod *oh)
{
return oh->prcm.omap4.context_lost_counter;
}
/**
* _enable - enable an omap_hwmod
* @oh: struct omap_hwmod *
@@ -2097,6 +2135,9 @@ static int _enable(struct omap_hwmod *oh)
if (soc_ops.enable_module)
soc_ops.enable_module(oh);
if (soc_ops.update_context_lost)
soc_ops.update_context_lost(oh);
r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
-EINVAL;
if (!r) {
@@ -3421,7 +3462,7 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
/**
* omap_hwmod_count_resources - count number of struct resources needed by hwmod
* @oh: struct omap_hwmod *
* @res: pointer to the first element of an array of struct resource to fill
* @flags: Type of resources to include when counting (IRQ/DMA/MEM)
*
* Count the number of struct resource array elements necessary to
* contain omap_hwmod @oh resources. Intended to be called by code
@@ -3434,20 +3475,25 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
* resource IDs.
*
*/
int omap_hwmod_count_resources(struct omap_hwmod *oh)
int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags)
{
struct omap_hwmod_ocp_if *os;
struct list_head *p;
int ret;
int i = 0;
int ret = 0;
ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
if (flags & IORESOURCE_IRQ)
ret += _count_mpu_irqs(oh);
p = oh->slave_ports.next;
if (flags & IORESOURCE_DMA)
ret += _count_sdma_reqs(oh);
while (i < oh->slaves_cnt) {
os = _fetch_next_ocp_if(&p, &i);
ret += _count_ocp_if_addr_spaces(os);
if (flags & IORESOURCE_MEM) {
int i = 0;
struct omap_hwmod_ocp_if *os;
struct list_head *p = oh->slave_ports.next;
while (i < oh->slaves_cnt) {
os = _fetch_next_ocp_if(&p, &i);
ret += _count_ocp_if_addr_spaces(os);
}
}
return ret;
@@ -3942,17 +3988,21 @@ ohsps_unlock:
* omap_hwmod_get_context_loss_count - get lost context count
* @oh: struct omap_hwmod *
*
* Query the powerdomain of of @oh to get the context loss
* count for this device.
* Returns the context loss count of associated @oh
* upon success, or zero if no context loss data is available.
*
* Returns the context loss count of the powerdomain assocated with @oh
* upon success, or zero if no powerdomain exists for @oh.
* On OMAP4, this queries the per-hwmod context loss register,
* assuming one exists. If not, or on OMAP2/3, this queries the
* enclosing powerdomain context loss count.
*/
int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
{
struct powerdomain *pwrdm;
int ret = 0;
if (soc_ops.get_context_lost)
return soc_ops.get_context_lost(oh);
pwrdm = omap_hwmod_get_pwrdm(oh);
if (pwrdm)
ret = pwrdm_get_context_loss_count(pwrdm);
@@ -4067,6 +4117,8 @@ void __init omap_hwmod_init(void)
soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
soc_ops.init_clkdm = _init_clkdm;
soc_ops.update_context_lost = _omap4_update_context_lost;
soc_ops.get_context_lost = _omap4_get_context_lost;
} else if (soc_is_am33xx()) {
soc_ops.enable_module = _am33xx_enable_module;
soc_ops.disable_module = _am33xx_disable_module;

12
arch/arm/mach-omap2/omap_hwmod.h
View File

@@ -2,7 +2,7 @@
* omap_hwmod macros, structures
*
* Copyright (C) 2009-2011 Nokia Corporation
* Copyright (C) 2012 Texas Instruments, Inc.
* Copyright (C) 2011-2012 Texas Instruments, Inc.
* Paul Walmsley
*
* Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -394,12 +394,15 @@ struct omap_hwmod_omap2_prcm {
/**
* struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
* @clkctrl_reg: PRCM address of the clock control register
* @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
* @clkctrl_offs: offset of the PRCM clock control register
* @rstctrl_offs: offset of the XXX_RSTCTRL register located in the PRM
* @context_offs: offset of the RM_*_CONTEXT register
* @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
* @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
* @submodule_wkdep_bit: bit shift of the WKDEP range
* @flags: PRCM register capabilities for this IP block
* @modulemode: allowable modulemodes
* @context_lost_counter: Count of module level context lost
*
* If @lostcontext_mask is not defined, context loss check code uses
* whole register without masking. @lostcontext_mask should only be
@@ -415,6 +418,7 @@ struct omap_hwmod_omap4_prcm {
u8 submodule_wkdep_bit;
u8 modulemode;
u8 flags;
int context_lost_counter;
};
@@ -633,7 +637,7 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
int omap_hwmod_softreset(struct omap_hwmod *oh);
int omap_hwmod_count_resources(struct omap_hwmod *oh);
int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags);
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,

3
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@@ -15,8 +15,7 @@
#include <linux/i2c-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include <plat/dmtimer.h>
#include "omap_hwmod.h"

3
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@@ -16,8 +16,7 @@
#include <linux/i2c-omap.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include <plat/dmtimer.h>
#include "omap_hwmod.h"

5
arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
View File

@@ -10,9 +10,8 @@
* published by the Free Software Foundation.
*/
#include <plat-omap/dma-omap.h>
#include "../plat-omap/common.h"
#include <linux/dmaengine.h>
#include <linux/omap-dma.h>
#include "omap_hwmod.h"
#include "hdq1w.h"

17
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
View File

@@ -10,7 +10,7 @@
*/
#include <linux/platform_data/gpio-omap.h>
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include <plat/dmtimer.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
@@ -58,8 +58,9 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.clockact = CLOCKACT_TEST_ICLK,
.sysc_fields = &omap_hwmod_sysc_type1,
};
@@ -268,6 +269,7 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
},
.dev_attr = &capability_alwon_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer2 */
@@ -286,6 +288,7 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
},
},
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer3 */
@@ -304,6 +307,7 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
},
},
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer4 */
@@ -322,6 +326,7 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
},
},
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer5 */
@@ -341,6 +346,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
},
.dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer6 */
@@ -360,6 +366,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
},
.dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer7 */
@@ -379,6 +386,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
},
.dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer8 */
@@ -398,6 +406,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
},
.dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer9 */
@@ -417,6 +426,7 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
},
.dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer10 */
@@ -436,6 +446,7 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
},
.dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer11 */
@@ -455,6 +466,7 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
},
.dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer12 */
@@ -474,6 +486,7 @@ struct omap_hwmod omap2xxx_timer12_hwmod = {
},
.dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* wd_timer2 */

43
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@@ -19,7 +19,7 @@
#include <linux/power/smartreflex.h>
#include <linux/platform_data/gpio-omap.h>
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include "l3_3xxx.h"
#include "l4_3xxx.h"
#include <linux/platform_data/asoc-ti-mcbsp.h>
@@ -153,29 +153,16 @@ static struct omap_hwmod omap3xxx_debugss_hwmod = {
};
/* timer class */
static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
.name = "timer",
.sysc = &omap3xxx_timer_1ms_sysc,
};
static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.clockact = CLOCKACT_TEST_ICLK,
.sysc_fields = &omap_hwmod_sysc_type1,
};
@@ -224,7 +211,8 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
},
},
.dev_attr = &capability_alwon_dev_attr,
.class = &omap3xxx_timer_1ms_hwmod_class,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer2 */
@@ -241,7 +229,8 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
},
},
.class = &omap3xxx_timer_1ms_hwmod_class,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer3 */
@@ -259,6 +248,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
},
},
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer4 */
@@ -276,6 +266,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
},
},
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer5 */
@@ -294,6 +285,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
},
.dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer6 */
@@ -312,6 +304,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
},
.dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer7 */
@@ -330,6 +323,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
},
.dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer8 */
@@ -348,6 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
},
.dev_attr = &capability_dsp_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer9 */
@@ -366,6 +361,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
},
.dev_attr = &capability_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer10 */
@@ -383,7 +379,8 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
},
},
.dev_attr = &capability_pwm_dev_attr,
.class = &omap3xxx_timer_1ms_hwmod_class,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer11 */
@@ -402,6 +399,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
},
.dev_attr = &capability_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer12 */
@@ -425,6 +423,7 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
},
.dev_attr = &capability_secure_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/*

9
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
View File

@@ -24,15 +24,14 @@
#include <linux/platform_data/omap_ocp2scp.h>
#include <linux/i2c-omap.h>
#include <plat-omap/dma-omap.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/omap_ocp2scp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <plat/dmtimer.h>
#include <plat/iommu.h>
#include "../plat-omap/common.h"
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include "cm1_44xx.h"
@@ -3105,6 +3104,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.clockact = CLOCKACT_TEST_ICLK,
.sysc_fields = &omap_hwmod_sysc_type1,
};
@@ -3158,6 +3158,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_timer1_irqs,
.main_clk = "timer1_fck",
.prcm = {
@@ -3180,6 +3181,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
.name = "timer2",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_timer2_irqs,
.main_clk = "timer2_fck",
.prcm = {
@@ -3354,6 +3356,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
.name = "timer10",
.class = &omap44xx_timer_1ms_hwmod_class,
.clkdm_name = "l4_per_clkdm",
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
.mpu_irqs = omap44xx_timer10_irqs,
.main_clk = "timer10_fck",
.prcm = {

1
arch/arm/mach-omap2/pm-debug.c
View File

@@ -30,7 +30,6 @@
#include "clock.h"
#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/dmtimer.h>
#include "omap-pm.h"
#include "soc.h"

7
arch/arm/mach-omap2/pm24xx.c
View File

@@ -31,14 +31,14 @@
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>
#include <asm/fncpy.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <asm/system_misc.h>
#include <plat-omap/dma-omap.h>
#include "../plat-omap/sram.h"
#include <linux/omap-dma.h>
#include "soc.h"
#include "common.h"
@@ -48,6 +48,7 @@
#include "cm2xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "sram.h"
#include "pm.h"
#include "control.h"
#include "powerdomain.h"

7
arch/arm/mach-omap2/pm34xx.c
View File

@@ -28,19 +28,17 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/omap-dma.h>
#include <linux/platform_data/gpio-omap.h>
#include <trace/events/power.h>
#include <asm/fncpy.h>
#include <asm/suspend.h>
#include <asm/system_misc.h>
#include "clockdomain.h"
#include "powerdomain.h"
#include <plat-omap/dma-omap.h>
#include "../plat-omap/sram.h"
#include "soc.h"
#include "common.h"
#include "cm3xxx.h"
@@ -50,6 +48,7 @@
#include "prm3xxx.h"
#include "pm.h"
#include "sdrc.h"
#include "sram.h"
#include "control.h"
/* pm34xx errata defined in pm.h */

11
arch/arm/mach-omap2/prm.h
View File

@@ -114,16 +114,25 @@ struct prm_reset_src_map {
/**
* struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
* @read_reset_sources: ptr to the Soc PRM-specific get_reset_source impl
* @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
* @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
* @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
*
* XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
* deprecated.
*/
struct prm_ll_data {
u32 (*read_reset_sources)(void);
bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
};
extern int prm_register(struct prm_ll_data *pld);
extern int prm_unregister(struct prm_ll_data *pld);
extern u32 prm_read_reset_sources(void);
extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
#endif

3
arch/arm/mach-omap2/prm2xxx.c
View File

@@ -118,14 +118,13 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
.read_reset_sources = &omap2xxx_prm_read_reset_sources,
};
static int __init omap2xxx_prm_init(void)
int __init omap2xxx_prm_init(void)
{
if (!cpu_is_omap24xx())
return 0;
return prm_register(&omap2xxx_prm_ll_data);
}
subsys_initcall(omap2xxx_prm_init);
static void __exit omap2xxx_prm_exit(void)
{

3
arch/arm/mach-omap2/prm2xxx.h
View File

@@ -126,8 +126,7 @@ extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);
extern void omap2xxx_prm_dpll_reset(void);
extern int __init prm2xxx_init(void);
extern int __exit prm2xxx_exit(void);
extern int __init omap2xxx_prm_init(void);
#endif

2
arch/arm/mach-omap2/prm33xx.c
View File

@@ -19,8 +19,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include "../plat-omap/common.h"
#include "common.h"
#include "powerdomain.h"
#include "prm33xx.h"

17
arch/arm/mach-omap2/prm3xxx.c
View File

@@ -383,27 +383,30 @@ static struct prm_ll_data omap3xxx_prm_ll_data = {
.read_reset_sources = &omap3xxx_prm_read_reset_sources,
};
static int __init omap3xxx_prm_init(void)
int __init omap3xxx_prm_init(void)
{
if (!cpu_is_omap34xx())
return 0;
return prm_register(&omap3xxx_prm_ll_data);
}
static int __init omap3xxx_prm_late_init(void)
{
int ret;
if (!cpu_is_omap34xx())
return 0;
ret = prm_register(&omap3xxx_prm_ll_data);
if (ret)
return ret;
omap3xxx_prm_enable_io_wakeup();
ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
if (!ret)
irq_set_status_flags(omap_prcm_event_to_irq("io"),
IRQ_NOAUTOEN);
return ret;
}
subsys_initcall(omap3xxx_prm_init);
subsys_initcall(omap3xxx_prm_late_init);
static void __exit omap3xxx_prm_exit(void)
{

1
arch/arm/mach-omap2/prm3xxx.h
View File

@@ -154,6 +154,7 @@ extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
extern void omap3xxx_prm_dpll3_reset(void);
extern int __init omap3xxx_prm_init(void);
extern u32 omap3xxx_prm_get_reset_sources(void);
#endif /* __ASSEMBLER */

49
arch/arm/mach-omap2/prm44xx.c
View File

@@ -346,6 +346,37 @@ static u32 omap44xx_prm_read_reset_sources(void)
return r;
}
/**
* omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
* @idx: CONTEXT register offset
*
* Return 1 if any bits were set in the *_CONTEXT_* register
* identified by (@part, @inst, @idx), which means that some context
* was lost for that module; otherwise, return 0.
*/
static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
{
return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
}
/**
* omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
* @idx: CONTEXT register offset
*
* Clear hardware context loss bits for the module identified by
* (@part, @inst, @idx). No return value. XXX Writes to reserved bits;
* is there a way to avoid this?
*/
static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
u16 idx)
{
omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
}
/* Powerdomain low-level functions */
static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
@@ -613,24 +644,28 @@ struct pwrdm_ops omap4_pwrdm_operations = {
*/
static struct prm_ll_data omap44xx_prm_ll_data = {
.read_reset_sources = &omap44xx_prm_read_reset_sources,
.was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
.clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
};
static int __init omap44xx_prm_init(void)
int __init omap44xx_prm_init(void)
{
int ret;
if (!cpu_is_omap44xx())
return 0;
ret = prm_register(&omap44xx_prm_ll_data);
if (ret)
return ret;
return prm_register(&omap44xx_prm_ll_data);
}
static int __init omap44xx_prm_late_init(void)
{
if (!cpu_is_omap44xx())
return 0;
omap44xx_prm_enable_io_wakeup();
return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
}
subsys_initcall(omap44xx_prm_init);
subsys_initcall(omap44xx_prm_late_init);
static void __exit omap44xx_prm_exit(void)
{

1
arch/arm/mach-omap2/prm44xx.h
View File

@@ -771,6 +771,7 @@ extern void omap44xx_prm_ocp_barrier(void);
extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
extern int __init omap44xx_prm_init(void);
extern u32 omap44xx_prm_get_reset_sources(void);
# endif

47
arch/arm/mach-omap2/prm_common.c
View File

@@ -24,8 +24,6 @@
#include <linux/interrupt.h>
#include <linux/slab.h>
#include "../plat-omap/common.h"
#include "prm2xxx_3xxx.h"
#include "prm2xxx.h"
#include "prm3xxx.h"
@@ -366,6 +364,51 @@ u32 prm_read_reset_sources(void)
return ret;
}
/**
* prm_was_any_context_lost_old - was device context lost? (old API)
* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
* @idx: CONTEXT register offset
*
* Return 1 if any bits were set in the *_CONTEXT_* register
* identified by (@part, @inst, @idx), which means that some context
* was lost for that module; otherwise, return 0. XXX Deprecated;
* callers need to use a less-SoC-dependent way to identify hardware
* IP blocks.
*/
bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
{
bool ret = true;
if (prm_ll_data->was_any_context_lost_old)
ret = prm_ll_data->was_any_context_lost_old(part, inst, idx);
else
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
__func__);
return ret;
}
/**
* prm_clear_context_lost_flags_old - clear context loss flags (old API)
* @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
* @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
* @idx: CONTEXT register offset
*
* Clear hardware context loss bits for the module identified by
* (@part, @inst, @idx). No return value. XXX Deprecated; callers
* need to use a less-SoC-dependent way to identify hardware IP
* blocks.
*/
void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx)
{
if (prm_ll_data->clear_context_loss_flags_old)
prm_ll_data->clear_context_loss_flags_old(part, inst, idx);
else
WARN_ONCE(1, "prm: %s: no mapping function defined\n",
__func__);
}
/**
* prm_register - register per-SoC low-level data with the PRM
* @pld: low-level per-SoC OMAP PRM data & function pointers to register

2
arch/arm/mach-omap2/sdrc.c
View File

@@ -23,8 +23,6 @@
#include <linux/clk.h>
#include <linux/io.h>
#include "../plat-omap/sram.h"
#include "common.h"
#include "clock.h"
#include "sdrc.h"

3
arch/arm/mach-omap2/sdrc2xxx.c
View File

@@ -24,14 +24,13 @@
#include <linux/clk.h>
#include <linux/io.h>
#include "../plat-omap/sram.h"
#include "soc.h"
#include "iomap.h"
#include "common.h"
#include "prm2xxx.h"
#include "clock.h"
#include "sdrc.h"
#include "sram.h"
/* Memory timing, DLL mode flags */
#define M_DDR 1

2
arch/arm/mach-omap2/serial.c
View File

@@ -26,9 +26,9 @@
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/console.h>
#include <linux/omap-dma.h>
#include <plat/omap-serial.h>
#include <plat-omap/dma-omap.h>
#include "common.h"
#include "omap_hwmod.h"

113
arch/arm/mach-omap2/serial.h
View File

@@ -1,112 +1 @@
/*
* arch/arm/plat-omap/include/mach/serial.h
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
#include <linux/init.h>
/*
* Memory entry used for the DEBUG_LL UART configuration, relative to
* start of RAM. See also uncompress.h and debug-macro.S.
*
* Note that using a memory location for storing the UART configuration
* has at least two limitations:
*
* 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
* uncompress code could then partially overwrite itself
* 2. We assume printascii is called at least once before paging_init,
* and addruart has a chance to read OMAP_UART_INFO
*/
#define OMAP_UART_INFO_OFS 0x3ffc
/* OMAP2 serial ports */
#define OMAP2_UART1_BASE 0x4806a000
#define OMAP2_UART2_BASE 0x4806c000
#define OMAP2_UART3_BASE 0x4806e000
/* OMAP3 serial ports */
#define OMAP3_UART1_BASE OMAP2_UART1_BASE
#define OMAP3_UART2_BASE OMAP2_UART2_BASE
#define OMAP3_UART3_BASE 0x49020000
#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
/* OMAP4 serial ports */
#define OMAP4_UART1_BASE OMAP2_UART1_BASE
#define OMAP4_UART2_BASE OMAP2_UART2_BASE
#define OMAP4_UART3_BASE 0x48020000
#define OMAP4_UART4_BASE 0x4806e000
/* TI81XX serial ports */
#define TI81XX_UART1_BASE 0x48020000
#define TI81XX_UART2_BASE 0x48022000
#define TI81XX_UART3_BASE 0x48024000
/* AM3505/3517 UART4 */
#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
/* AM33XX serial port */
#define AM33XX_UART1_BASE 0x44E09000
/* OMAP5 serial ports */
#define OMAP5_UART1_BASE OMAP2_UART1_BASE
#define OMAP5_UART2_BASE OMAP2_UART2_BASE
#define OMAP5_UART3_BASE OMAP4_UART3_BASE
#define OMAP5_UART4_BASE OMAP4_UART4_BASE
#define OMAP5_UART5_BASE 0x48066000
#define OMAP5_UART6_BASE 0x48068000
/* External port on Zoom2/3 */
#define ZOOM_UART_BASE 0x10000000
#define ZOOM_UART_VIRT 0xfa400000
#define OMAP_PORT_SHIFT 2
#define ZOOM_PORT_SHIFT 1
#define OMAP24XX_BASE_BAUD (48000000/16)
/*
* DEBUG_LL port encoding stored into the UART1 scratchpad register by
* decomp_setup in uncompress.h
*/
#define OMAP2UART1 21
#define OMAP2UART2 22
#define OMAP2UART3 23
#define OMAP3UART1 OMAP2UART1
#define OMAP3UART2 OMAP2UART2
#define OMAP3UART3 33
#define OMAP3UART4 34 /* Only on 36xx */
#define OMAP4UART1 OMAP2UART1
#define OMAP4UART2 OMAP2UART2
#define OMAP4UART3 43
#define OMAP4UART4 44
#define TI81XXUART1 81
#define TI81XXUART2 82
#define TI81XXUART3 83
#define AM33XXUART1 84
#define OMAP5UART3 OMAP4UART3
#define OMAP5UART4 OMAP4UART4
#define ZOOM_UART 95 /* Only on zoom2/3 */
#ifndef __ASSEMBLER__
struct omap_board_data;
struct omap_uart_port_info;
extern void omap_serial_init(void);
extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
extern void omap_serial_init_port(struct omap_board_data *bdata,
struct omap_uart_port_info *platform_data);
#endif
#endif
#include <mach/serial.h>

3
arch/arm/mach-omap2/sleep34xx.S
View File

@@ -26,13 +26,12 @@
#include <asm/assembler.h>
#include "../plat-omap/sram.h"
#include "omap34xx.h"
#include "iomap.h"
#include "cm3xxx.h"
#include "prm3xxx.h"
#include "sdrc.h"
#include "sram.h"
#include "control.h"
/*

8
arch/arm/mach-omap2/soc.h
View File

@@ -435,9 +435,7 @@ extern u32 omap_features;
#define OMAP3_HAS_IO_WAKEUP BIT(6)
#define OMAP3_HAS_SDRC BIT(7)
#define OMAP3_HAS_IO_CHAIN_CTRL BIT(8)
#define OMAP4_HAS_MPU_1GHZ BIT(9)
#define OMAP4_HAS_MPU_1_2GHZ BIT(10)
#define OMAP4_HAS_MPU_1_5GHZ BIT(11)
#define OMAP4_HAS_PERF_SILICON BIT(9)
#define OMAP3_HAS_FEATURE(feat,flag) \
@@ -465,9 +463,7 @@ static inline unsigned int omap4_has_ ##feat(void) \
return omap_features & OMAP4_HAS_ ##flag; \
} \
OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
OMAP4_HAS_FEATURE(perf_silicon, PERF_SILICON)
#endif /* __ASSEMBLY__ */

305
arch/arm/mach-omap2/sram.c Normal file
View File

@@ -0,0 +1,305 @@
/*
*
* OMAP SRAM detection and management
*
* Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
*
* Copyright (C) 2009-2012 Texas Instruments
* Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/fncpy.h>
#include <asm/tlb.h>
#include <asm/cacheflush.h>
#include <asm/mach/map.h>
#include "soc.h"
#include "iomap.h"
#include "prm2xxx_3xxx.h"
#include "sdrc.h"
#include "sram.h"
#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
#ifdef CONFIG_OMAP4_ERRATA_I688
#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
#else
#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
#endif
#define OMAP5_SRAM_PA 0x40300000
#define SRAM_BOOTLOADER_SZ 0x00
#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
#define GP_DEVICE 0x300
#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
static unsigned long omap_sram_start;
static unsigned long omap_sram_skip;
static unsigned long omap_sram_size;
/*
* Depending on the target RAMFS firewall setup, the public usable amount of
* SRAM varies. The default accessible size for all device types is 2k. A GP
* device allows ARM11 but not other initiators for full size. This
* functionality seems ok until some nice security API happens.
*/
static int is_sram_locked(void)
{
if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
/* RAMFW: R/W access to all initiators for all qualifier sets */
if (cpu_is_omap242x()) {
__raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
__raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
__raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
}
if (cpu_is_omap34xx()) {
__raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
__raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
__raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
__raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
__raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
}
return 0;
} else
return 1; /* assume locked with no PPA or security driver */
}
/*
* The amount of SRAM depends on the core type.
* Note that we cannot try to test for SRAM here because writes
* to secure SRAM will hang the system. Also the SRAM is not
* yet mapped at this point.
*/
static void __init omap_detect_sram(void)
{
omap_sram_skip = SRAM_BOOTLOADER_SZ;
if (is_sram_locked()) {
if (cpu_is_omap34xx()) {
omap_sram_start = OMAP3_SRAM_PUB_PA;
if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
(omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
omap_sram_size = 0x7000; /* 28K */
omap_sram_skip += SZ_16K;
} else {
omap_sram_size = 0x8000; /* 32K */
}
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_PUB_PA;
omap_sram_size = 0xa000; /* 40K */
} else if (soc_is_omap54xx()) {
omap_sram_start = OMAP5_SRAM_PA;
omap_sram_size = SZ_128K; /* 128KB */
} else {
omap_sram_start = OMAP2_SRAM_PUB_PA;
omap_sram_size = 0x800; /* 2K */
}
} else {
if (soc_is_am33xx()) {
omap_sram_start = AM33XX_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap34xx()) {
omap_sram_start = OMAP3_SRAM_PA;
omap_sram_size = 0x10000; /* 64K */
} else if (cpu_is_omap44xx()) {
omap_sram_start = OMAP4_SRAM_PA;
omap_sram_size = 0xe000; /* 56K */
} else if (soc_is_omap54xx()) {
omap_sram_start = OMAP5_SRAM_PA;
omap_sram_size = SZ_128K; /* 128KB */
} else {
omap_sram_start = OMAP2_SRAM_PA;
if (cpu_is_omap242x())
omap_sram_size = 0xa0000; /* 640K */
else if (cpu_is_omap243x())
omap_sram_size = 0x10000; /* 64K */
}
}
}
/*
* Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
*/
static void __init omap2_map_sram(void)
{
int cached = 1;
#ifdef CONFIG_OMAP4_ERRATA_I688
if (cpu_is_omap44xx()) {
omap_sram_start += PAGE_SIZE;
omap_sram_size -= SZ_16K;
}
#endif
if (cpu_is_omap34xx()) {
/*
* SRAM must be marked as non-cached on OMAP3 since the
* CORE DPLL M2 divider change code (in SRAM) runs with the
* SDRAM controller disabled, and if it is marked cached,
* the ARM may attempt to write cache lines back to SDRAM
* which will cause the system to hang.
*/
cached = 0;
}
omap_map_sram(omap_sram_start, omap_sram_size,
omap_sram_skip, cached);
}
static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock);
void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock)
{
BUG_ON(!_omap2_sram_ddr_init);
_omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
base_cs, force_unlock);
}
static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
u32 mem_type);
void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
{
BUG_ON(!_omap2_sram_reprogram_sdrc);
_omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
}
static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
{
BUG_ON(!_omap2_set_prcm);
return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
}
#ifdef CONFIG_SOC_OMAP2420
static int __init omap242x_sram_init(void)
{
_omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
omap242x_sram_ddr_init_sz);
_omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
omap242x_sram_reprogram_sdrc_sz);
_omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
omap242x_sram_set_prcm_sz);
return 0;
}
#else
static inline int omap242x_sram_init(void)
{
return 0;
}
#endif
#ifdef CONFIG_SOC_OMAP2430
static int __init omap243x_sram_init(void)
{
_omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
omap243x_sram_ddr_init_sz);
_omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
omap243x_sram_reprogram_sdrc_sz);
_omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
omap243x_sram_set_prcm_sz);
return 0;
}
#else
static inline int omap243x_sram_init(void)
{
return 0;
}
#endif
#ifdef CONFIG_ARCH_OMAP3
static u32 (*_omap3_sram_configure_core_dpll)(
u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
{
BUG_ON(!_omap3_sram_configure_core_dpll);
return _omap3_sram_configure_core_dpll(
m2, unlock_dll, f, inc,
sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
sdrc_actim_ctrl_b_0, sdrc_mr_0,
sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
sdrc_actim_ctrl_b_1, sdrc_mr_1);
}
void omap3_sram_restore_context(void)
{
omap_sram_reset();
_omap3_sram_configure_core_dpll =
omap_sram_push(omap3_sram_configure_core_dpll,
omap3_sram_configure_core_dpll_sz);
omap_push_sram_idle();
}
static inline int omap34xx_sram_init(void)
{
omap3_sram_restore_context();
return 0;
}
#else
static inline int omap34xx_sram_init(void)
{
return 0;
}
#endif /* CONFIG_ARCH_OMAP3 */
static inline int am33xx_sram_init(void)
{
return 0;
}
int __init omap_sram_init(void)
{
omap_detect_sram();
omap2_map_sram();
if (cpu_is_omap242x())
omap242x_sram_init();
else if (cpu_is_omap2430())
omap243x_sram_init();
else if (soc_is_am33xx())
am33xx_sram_init();
else if (cpu_is_omap34xx())
omap34xx_sram_init();
return 0;
}

83
arch/arm/mach-omap2/sram.h Normal file
View File

@@ -0,0 +1,83 @@
/*
* Interface for functions that need to be run in internal SRAM
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASSEMBLY__
#include <plat/sram.h>
extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock);
extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(
u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
extern void omap3_sram_restore_context(void);
/* Do not use these */
extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
extern unsigned long omap24xx_sram_reprogram_clock_sz;
extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock);
extern unsigned long omap242x_sram_ddr_init_sz;
extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
int bypass);
extern unsigned long omap242x_sram_set_prcm_sz;
extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern unsigned long omap242x_sram_reprogram_sdrc_sz;
extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock);
extern unsigned long omap243x_sram_ddr_init_sz;
extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
int bypass);
extern unsigned long omap243x_sram_set_prcm_sz;
extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type);
extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(
u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
extern unsigned long omap3_sram_configure_core_dpll_sz;
#ifdef CONFIG_PM
extern void omap_push_sram_idle(void);
#else
static inline void omap_push_sram_idle(void) {}
#endif /* CONFIG_PM */
#endif /* __ASSEMBLY__ */
/*
* OMAP2+: define the SRAM PA addresses.
* Used by the SRAM management code and the idle sleep code.
*/
#define OMAP2_SRAM_PA 0x40200000
#define OMAP3_SRAM_PA 0x40200000
#ifdef CONFIG_OMAP4_ERRATA_I688
#define OMAP4_SRAM_PA 0x40304000
#define OMAP4_SRAM_VA 0xfe404000
#else
#define OMAP4_SRAM_PA 0x40300000
#endif
#define AM33XX_SRAM_PA 0x40300000

385
arch/arm/mach-omap2/timer.c
View File

@@ -37,6 +37,10 @@
#include <linux/clockchips.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
#include <asm/mach/time.h>
#include <asm/smp_twd.h>
@@ -45,6 +49,7 @@
#include <asm/arch_timer.h>
#include "omap_hwmod.h"
#include "omap_device.h"
#include <plat/counter-32k.h>
#include <plat/dmtimer.h>
#include "omap-pm.h"
@@ -61,18 +66,6 @@
#define OMAP3_32K_SOURCE "omap_32k_fck"
#define OMAP4_32K_SOURCE "sys_32k_ck"
#ifdef CONFIG_OMAP_32K_TIMER
#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
#define OMAP3_SECURE_TIMER 12
#else
#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
#define OMAP3_SECURE_TIMER 1
#endif
#define REALTIME_COUNTER_BASE 0x48243200
#define INCREMENTER_NUMERATOR_OFFSET 0x10
#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
@@ -103,7 +96,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
__omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
0xffffffff - cycles, 1);
0xffffffff - cycles, OMAP_TIMER_POSTED);
return 0;
}
@@ -113,7 +106,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
{
u32 period;
__omap_dm_timer_stop(&clkev, 1, clkev.rate);
__omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
@@ -121,10 +114,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
period -= 1;
/* Looks like we need to first set the load value separately */
__omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
0xffffffff - period, 1);
0xffffffff - period, OMAP_TIMER_POSTED);
__omap_dm_timer_load_start(&clkev,
OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
0xffffffff - period, 1);
0xffffffff - period, OMAP_TIMER_POSTED);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
@@ -144,36 +137,144 @@ static struct clock_event_device clockevent_gpt = {
.set_mode = omap2_gp_timer_set_mode,
};
static struct property device_disabled = {
.name = "status",
.length = sizeof("disabled"),
.value = "disabled",
};
static struct of_device_id omap_timer_match[] __initdata = {
{ .compatible = "ti,omap2-timer", },
{ }
};
/**
* omap_get_timer_dt - get a timer using device-tree
* @match - device-tree match structure for matching a device type
* @property - optional timer property to match
*
* Helper function to get a timer during early boot using device-tree for use
* as kernel system timer. Optionally, the property argument can be used to
* select a timer with a specific property. Once a timer is found then mark
* the timer node in device-tree as disabled, to prevent the kernel from
* registering this timer as a platform device and so no one else can use it.
*/
static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
const char *property)
{
struct device_node *np;
for_each_matching_node(np, match) {
if (!of_device_is_available(np)) {
of_node_put(np);
continue;
}
if (property && !of_get_property(np, property, NULL)) {
of_node_put(np);
continue;
}
prom_add_property(np, &device_disabled);
return np;
}
return NULL;
}
/**
* omap_dmtimer_init - initialisation function when device tree is used
*
* For secure OMAP3 devices, timers with device type "timer-secure" cannot
* be used by the kernel as they are reserved. Therefore, to prevent the
* kernel registering these devices remove them dynamically from the device
* tree on boot.
*/
void __init omap_dmtimer_init(void)
{
struct device_node *np;
if (!cpu_is_omap34xx())
return;
/* If we are a secure device, remove any secure timer nodes */
if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
if (np)
of_node_put(np);
}
}
/**
* omap_dm_timer_get_errata - get errata flags for a timer
*
* Get the timer errata flags that are specific to the OMAP device being used.
*/
u32 __init omap_dm_timer_get_errata(void)
{
if (cpu_is_omap24xx())
return 0;
return OMAP_TIMER_ERRATA_I103_I767;
}
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
int gptimer_id,
const char *fck_source)
const char *fck_source,
const char *property,
int posted)
{
char name[10]; /* 10 = sizeof("gptXX_Xck0") */
const char *oh_name;
struct device_node *np;
struct omap_hwmod *oh;
struct resource irq_rsrc, mem_rsrc;
size_t size;
int res = 0;
int r;
struct resource irq, mem;
int r = 0;
sprintf(name, "timer%d", gptimer_id);
omap_hwmod_setup_one(name);
oh = omap_hwmod_lookup(name);
if (of_have_populated_dt()) {
np = omap_get_timer_dt(omap_timer_match, NULL);
if (!np)
return -ENODEV;
of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
if (!oh_name)
return -ENODEV;
timer->irq = irq_of_parse_and_map(np, 0);
if (!timer->irq)
return -ENXIO;
timer->io_base = of_iomap(np, 0);
of_node_put(np);
} else {
if (omap_dm_timer_reserve_systimer(gptimer_id))
return -ENODEV;
sprintf(name, "timer%d", gptimer_id);
oh_name = name;
}
oh = omap_hwmod_lookup(oh_name);
if (!oh)
return -ENODEV;
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
if (r)
return -ENXIO;
timer->irq = irq_rsrc.start;
if (!of_have_populated_dt()) {
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
&irq);
if (r)
return -ENXIO;
timer->irq = irq.start;
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
if (r)
return -ENXIO;
timer->phys_base = mem_rsrc.start;
size = mem_rsrc.end - mem_rsrc.start;
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
&mem);
if (r)
return -ENXIO;
/* Static mapping, never released */
timer->io_base = ioremap(mem.start, mem.end - mem.start);
}
/* Static mapping, never released */
timer->io_base = ioremap(timer->phys_base, size);
if (!timer->io_base)
return -ENXIO;
@@ -182,42 +283,56 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
if (IS_ERR(timer->fclk))
return -ENODEV;
omap_hwmod_enable(oh);
if (omap_dm_timer_reserve_systimer(gptimer_id))
return -ENODEV;
/* FIXME: Need to remove hard-coded test on timer ID */
if (gptimer_id != 12) {
struct clk *src;
src = clk_get(NULL, fck_source);
if (IS_ERR(src)) {
res = -EINVAL;
r = -EINVAL;
} else {
res = __omap_dm_timer_set_source(timer->fclk, src);
if (IS_ERR_VALUE(res))
pr_warning("%s: timer%i cannot set source\n",
__func__, gptimer_id);
r = clk_set_parent(timer->fclk, src);
if (IS_ERR_VALUE(r))
pr_warn("%s: %s cannot set source\n",
__func__, oh->name);
clk_put(src);
}
}
omap_hwmod_setup_one(oh_name);
omap_hwmod_enable(oh);
__omap_dm_timer_init_regs(timer);
__omap_dm_timer_reset(timer, 1, 1);
timer->posted = 1;
if (posted)
__omap_dm_timer_enable_posted(timer);
/* Check that the intended posted configuration matches the actual */
if (posted != timer->posted)
return -EINVAL;
timer->rate = clk_get_rate(timer->fclk);
timer->reserved = 1;
return res;
return r;
}
static void __init omap2_gp_clockevent_init(int gptimer_id,
const char *fck_source)
const char *fck_source,
const char *property)
{
int res;
res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
clkev.errata = omap_dm_timer_get_errata();
/*
* For clock-event timers we never read the timer counter and
* so we are not impacted by errata i103 and i767. Therefore,
* we can safely ignore this errata for clock-event timers.
*/
__omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
OMAP_TIMER_POSTED);
BUG_ON(res);
omap2_gp_timer_irq.dev_id = &clkev;
@@ -250,7 +365,8 @@ static bool use_gptimer_clksrc;
*/
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
OMAP_TIMER_NONPOSTED);
}
static struct clocksource clocksource_gpt = {
@@ -264,20 +380,40 @@ static struct clocksource clocksource_gpt = {
static u32 notrace dmtimer_read_sched_clock(void)
{
if (clksrc.reserved)
return __omap_dm_timer_read_counter(&clksrc, 1);
return __omap_dm_timer_read_counter(&clksrc,
OMAP_TIMER_NONPOSTED);
return 0;
}
#ifdef CONFIG_OMAP_32K_TIMER
static struct of_device_id omap_counter_match[] __initdata = {
{ .compatible = "ti,omap-counter32k", },
{ }
};
/* Setup free-running counter for clocksource */
static int __init omap2_sync32k_clocksource_init(void)
{
int ret;
struct device_node *np = NULL;
struct omap_hwmod *oh;
void __iomem *vbase;
const char *oh_name = "counter_32k";
/*
* If device-tree is present, then search the DT blob
* to see if the 32kHz counter is supported.
*/
if (of_have_populated_dt()) {
np = omap_get_timer_dt(omap_counter_match, NULL);
if (!np)
return -ENODEV;
of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
if (!oh_name)
return -ENODEV;
}
/*
* First check hwmod data is available for sync32k counter
*/
@@ -287,7 +423,13 @@ static int __init omap2_sync32k_clocksource_init(void)
omap_hwmod_setup_one(oh_name);
vbase = omap_hwmod_get_mpu_rt_va(oh);
if (np) {
vbase = of_iomap(np, 0);
of_node_put(np);
} else {
vbase = omap_hwmod_get_mpu_rt_va(oh);
}
if (!vbase) {
pr_warn("%s: failed to get counter_32k resource\n", __func__);
return -ENXIO;
@@ -309,23 +451,21 @@ static int __init omap2_sync32k_clocksource_init(void)
return ret;
}
#else
static inline int omap2_sync32k_clocksource_init(void)
{
return -ENODEV;
}
#endif
static void __init omap2_gptimer_clocksource_init(int gptimer_id,
const char *fck_source)
{
int res;
res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
clksrc.errata = omap_dm_timer_get_errata();
res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
OMAP_TIMER_NONPOSTED);
BUG_ON(res);
__omap_dm_timer_load_start(&clksrc,
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
OMAP_TIMER_NONPOSTED);
setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
@@ -336,25 +476,6 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
gptimer_id, clksrc.rate);
}
static void __init omap2_clocksource_init(int gptimer_id,
const char *fck_source)
{
/*
* First give preference to kernel parameter configuration
* by user (clocksource="gp_timer").
*
* In case of missing kernel parameter for clocksource,
* first check for availability for 32k-sync timer, in case
* of failure in finding 32k_counter module or registering
* it as clocksource, execution will fallback to gp-timer.
*/
if (use_gptimer_clksrc == true)
omap2_gptimer_clocksource_init(gptimer_id, fck_source);
else if (omap2_sync32k_clocksource_init())
/* Fall back to gp-timer code */
omap2_gptimer_clocksource_init(gptimer_id, fck_source);
}
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
/*
* The realtime counter also called master counter, is a free-running
@@ -433,48 +554,65 @@ static inline void __init realtime_counter_init(void)
{}
#endif
#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
clksrc_nr, clksrc_src) \
static void __init omap##name##_timer_init(void) \
#define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
clksrc_nr, clksrc_src) \
static void __init omap##name##_gptimer_timer_init(void) \
{ \
omap2_gp_clockevent_init((clkev_nr), clkev_src); \
omap2_clocksource_init((clksrc_nr), clksrc_src); \
omap_dmtimer_init(); \
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \
}
#define OMAP_SYS_TIMER(name) \
#define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
clksrc_nr, clksrc_src) \
static void __init omap##name##_sync32k_timer_init(void) \
{ \
omap_dmtimer_init(); \
omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
/* Enable the use of clocksource="gp_timer" kernel parameter */ \
if (use_gptimer_clksrc) \
omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
else \
omap2_sync32k_clocksource_init(); \
}
#define OMAP_SYS_TIMER(name, clksrc) \
struct sys_timer omap##name##_timer = { \
.init = omap##name##_timer_init, \
.init = omap##name##_##clksrc##_timer_init, \
};
#ifdef CONFIG_ARCH_OMAP2
OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
OMAP_SYS_TIMER(2)
#endif
OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
2, OMAP2_MPU_SOURCE);
OMAP_SYS_TIMER(2, sync32k);
#endif /* CONFIG_ARCH_OMAP2 */
#ifdef CONFIG_ARCH_OMAP3
OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3)
OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
2, OMAP3_MPU_SOURCE)
OMAP_SYS_TIMER(3_secure)
#endif
OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
2, OMAP3_MPU_SOURCE);
OMAP_SYS_TIMER(3, sync32k);
OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
2, OMAP3_MPU_SOURCE);
OMAP_SYS_TIMER(3_secure, sync32k);
OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
2, OMAP3_MPU_SOURCE);
OMAP_SYS_TIMER(3_gp, gptimer);
#endif /* CONFIG_ARCH_OMAP3 */
#ifdef CONFIG_SOC_AM33XX
OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
OMAP_SYS_TIMER(3_am33xx)
#endif
OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
2, OMAP4_MPU_SOURCE);
OMAP_SYS_TIMER(3_am33xx, gptimer);
#endif /* CONFIG_SOC_AM33XX */
#ifdef CONFIG_ARCH_OMAP4
OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
2, OMAP4_MPU_SOURCE);
#ifdef CONFIG_LOCAL_TIMERS
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
OMAP44XX_LOCAL_TWD_BASE, 29);
#endif
static void __init omap4_timer_init(void)
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
static void __init omap4_local_timer_init(void)
{
omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
#ifdef CONFIG_LOCAL_TIMERS
omap4_sync32k_timer_init();
/* Local timers are not supprted on OMAP4430 ES1.0 */
if (omap_rev() != OMAP4430_REV_ES1_0) {
int err;
@@ -488,26 +626,32 @@ static void __init omap4_timer_init(void)
if (err)
pr_err("twd_local_timer_register failed %d\n", err);
}
#endif
}
OMAP_SYS_TIMER(4)
#endif
#else /* CONFIG_LOCAL_TIMERS */
static inline void omap4_local_timer_init(void)
{
omap4_sync32_timer_init();
}
#endif /* CONFIG_LOCAL_TIMERS */
OMAP_SYS_TIMER(4, local);
#endif /* CONFIG_ARCH_OMAP4 */
#ifdef CONFIG_SOC_OMAP5
static void __init omap5_timer_init(void)
OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
2, OMAP4_MPU_SOURCE);
static void __init omap5_realtime_timer_init(void)
{
int err;
omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
omap5_sync32k_timer_init();
realtime_counter_init();
err = arch_timer_of_register();
if (err)
pr_err("%s: arch_timer_register failed %d\n", __func__, err);
}
OMAP_SYS_TIMER(5)
#endif
OMAP_SYS_TIMER(5, realtime);
#endif /* CONFIG_SOC_OMAP5 */
/**
* omap_timer_init - build and register timer device with an
@@ -559,6 +703,9 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
if (timer_dev_attr)
pdata->timer_capability = timer_dev_attr->timer_capability;
pdata->timer_errata = omap_dm_timer_get_errata();
pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
NULL, 0, 0);
@@ -583,6 +730,10 @@ static int __init omap2_dm_timer_init(void)
{
int ret;
/* If dtb is there, the devices will be created dynamically */
if (of_have_populated_dt())
return -ENODEV;
ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
if (unlikely(ret)) {
pr_err("%s: device registration failed.\n", __func__);

1
arch/arm/mach-omap2/twl-common.c
View File

@@ -70,6 +70,7 @@ void __init omap4_pmic_init(const char *pmic_type,
{
/* PMIC part*/
omap_mux_init_signal("sys_nirq1", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
omap_mux_init_signal("fref_clk0_out.sys_drm_msecure", OMAP_PIN_OUTPUT);
omap_pmic_init(1, 400, pmic_type, 7 + OMAP44XX_IRQ_GIC_START, pmic_data);
/* Register additional devices on i2c1 bus if needed */