Merge 5.10.48 into android12-5.10-lts
Changes in 5.10.48 scsi: sr: Return appropriate error code when disk is ejected gpio: mxc: Fix disabled interrupt wake-up support drm/nouveau: fix dma_address check for CPU/GPU sync gpio: AMD8111 and TQMX86 require HAS_IOPORT_MAP RDMA/mlx5: Block FDB rules when not in switchdev mode Revert "KVM: x86/mmu: Drop kvm_mmu_extended_role.cr4_la57 hack" Linux 5.10.48 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: Ie66f49fdd4e28b369b134dfb99aab7c0f0e3bd18
This commit is contained in:
2
Makefile
2
Makefile
@@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 5
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PATCHLEVEL = 10
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SUBLEVEL = 47
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SUBLEVEL = 48
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EXTRAVERSION =
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NAME = Dare mighty things
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@@ -296,6 +296,7 @@ union kvm_mmu_extended_role {
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unsigned int cr4_pke:1;
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unsigned int cr4_smap:1;
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unsigned int cr4_smep:1;
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unsigned int cr4_la57:1;
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unsigned int maxphyaddr:6;
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};
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};
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@@ -4442,6 +4442,7 @@ static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
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ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
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ext.cr4_pse = !!is_pse(vcpu);
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ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
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ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
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ext.maxphyaddr = cpuid_maxphyaddr(vcpu);
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ext.valid = 1;
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@@ -1337,6 +1337,7 @@ config GPIO_TPS68470
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config GPIO_TQMX86
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tristate "TQ-Systems QTMX86 GPIO"
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depends on MFD_TQMX86 || COMPILE_TEST
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depends on HAS_IOPORT_MAP
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select GPIOLIB_IRQCHIP
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help
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This driver supports GPIO on the TQMX86 IO controller.
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@@ -1404,6 +1405,7 @@ menu "PCI GPIO expanders"
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config GPIO_AMD8111
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tristate "AMD 8111 GPIO driver"
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depends on X86 || COMPILE_TEST
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depends on HAS_IOPORT_MAP
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help
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The AMD 8111 south bridge contains 32 GPIO pins which can be used.
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@@ -361,7 +361,7 @@ static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_set_type = gpio_set_irq_type;
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ct->chip.irq_set_wake = gpio_set_wake_irq;
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ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
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ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
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ct->regs.ack = GPIO_ISR;
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ct->regs.mask = GPIO_IMR;
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@@ -590,7 +590,7 @@ nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
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struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
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int i;
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if (!ttm_dma)
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if (!ttm_dma || !ttm_dma->dma_address)
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return;
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/* Don't waste time looping if the object is coherent */
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@@ -610,7 +610,7 @@ nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
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struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
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int i;
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if (!ttm_dma)
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if (!ttm_dma || !ttm_dma->dma_address)
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return;
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/* Don't waste time looping if the object is coherent */
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@@ -2136,6 +2136,13 @@ static int UVERBS_HANDLER(MLX5_IB_METHOD_FLOW_MATCHER_CREATE)(
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if (err)
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goto end;
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if (obj->ns_type == MLX5_FLOW_NAMESPACE_FDB &&
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mlx5_eswitch_mode(dev->mdev->priv.eswitch) !=
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MLX5_ESWITCH_OFFLOADS) {
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err = -EINVAL;
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goto end;
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}
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uobj->object = obj;
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obj->mdev = dev->mdev;
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atomic_set(&obj->usecnt, 0);
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@@ -220,6 +220,8 @@ static unsigned int sr_get_events(struct scsi_device *sdev)
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return DISK_EVENT_EJECT_REQUEST;
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else if (med->media_event_code == 2)
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return DISK_EVENT_MEDIA_CHANGE;
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else if (med->media_event_code == 3)
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return DISK_EVENT_EJECT_REQUEST;
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return 0;
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}
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