xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[PARISC] Properly specify index field to I/D cache flush ops

Browse Source 
replace use of "0" with "%r0" since PA 1.1 I/D flush ops only take a
general register and not an immediate value for the index field.
This just forces the code to always be PA 1.1 "clean".

From: Joel Soete <soete.joel@tiscali.be>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>

Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
This commit is contained in:
Grant Grundler
2005-10-21 22:55:51 -04:00
committed by Kyle McMartin
parent 37318a3cb1
commit 9b3b331d03
2 changed files with 9 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/parisc/kernel/signal.c
View File

@@ -625,11 +625,14 @@ do_signal(sigset_t *oldset, struct pt_regs *regs, int in_syscall)
put_user(0xe0008200, &usp[3]);
put_user(0x34140000, &usp[4]);
/* Stack is 64-byte aligned, and we only
* need to flush 1 cache line */
asm("fdc 0(%%sr3, %0)\n"
/* Stack is 64-byte aligned, and we only need
* to flush 1 cache line.
* Flushing one cacheline is cheap.
* "sync" on bigger (> 4 way) boxes is not.
*/
asm("fdc %%r0(%%sr3, %0)\n"
"sync\n"
"fic 0(%%sr3, %0)\n"
"fic %%r0(%%sr3, %0)\n"
"sync\n"
: : "r"(regs->gr[30]));