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MIPS: Respect the ISA level in FCSR handling

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Define the central place the default FCSR value is set from, initialised
in `cpu_probe'.  Determine the FCSR mask applied to values written to
the register with CTC1 in the full emulation mode and via ptrace(2),
according to the ISA level of processor hardware or the writability of
bits 31:18 if actual FPU hardware is used.

Software may rely on FCSR bits whose functions our emulator does not
implement, so it should not allow them to be set or software may get
confused.  For ptrace(2) it's just sanity.

[ralf@linux-mips.org: Fixed double inclusion of <asm/current.h>.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9711/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki
2015-04-03 23:27:48 +01:00
committed by Ralf Baechle
parent 232b6ec5df
commit 9b26616c8d
10 changed files with 83 additions and 21 deletions
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2
arch/mips/include/asm/cpu-info.h
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@@ -49,6 +49,8 @@ struct cpuinfo_mips {
unsigned int udelay_val;
unsigned int processor_id;
unsigned int fpu_id;
unsigned int fpu_csr31;
unsigned int fpu_msk31;
unsigned int msa_id;
unsigned int cputype;
int isa_level;