Merge tag 'char-misc-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc driver updates from Greg KH: "Here is the large set of char/misc driver patches for 5.8-rc1 Included in here are: - habanalabs driver updates, loads - mhi bus driver updates - extcon driver updates - clk driver updates (approved by the clock maintainer) - firmware driver updates - fpga driver updates - gnss driver updates - coresight driver updates - interconnect driver updates - parport driver updates (it's still alive!) - nvmem driver updates - soundwire driver updates - visorbus driver updates - w1 driver updates - various misc driver updates In short, loads of different driver subsystem updates along with the drivers as well. All have been in linux-next for a while with no reported issues" * tag 'char-misc-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (233 commits) habanalabs: correctly cast u64 to void* habanalabs: initialize variable to default value extcon: arizona: Fix runtime PM imbalance on error extcon: max14577: Add proper dt-compatible strings extcon: adc-jack: Fix an error handling path in 'adc_jack_probe()' extcon: remove redundant assignment to variable idx w1: omap-hdq: print dev_err if irq flags are not cleared w1: omap-hdq: fix interrupt handling which did show spurious timeouts w1: omap-hdq: fix return value to be -1 if there is a timeout w1: omap-hdq: cleanup to add missing newline for some dev_dbg /dev/mem: Revoke mappings when a driver claims the region misc: xilinx-sdfec: convert get_user_pages() --> pin_user_pages() misc: xilinx-sdfec: cleanup return value in xsdfec_table_write() misc: xilinx-sdfec: improve get_user_pages_fast() error handling nvmem: qfprom: remove incorrect write support habanalabs: handle MMU cache invalidation timeout habanalabs: don't allow hard reset with open processes habanalabs: GAUDI does not support soft-reset habanalabs: add print for soft reset due to event habanalabs: improve MMU cache invalidation code ...
This commit is contained in:
Linus Torvalds
@@ -54,32 +54,25 @@
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* Secure monitor software doesn't recognize the request.
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*
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* INTEL_SIP_SMC_STATUS_OK:
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* FPGA configuration completed successfully,
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* In case of FPGA configuration write operation, it means secure monitor
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* software can accept the next chunk of FPGA configuration data.
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* Secure monitor software accepts the service client's request.
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*
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* INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY:
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* In case of FPGA configuration write operation, it means secure monitor
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* software is still processing previous data & can't accept the next chunk
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* of data. Service driver needs to issue
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* INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE call to query the
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* completed block(s).
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* INTEL_SIP_SMC_STATUS_BUSY:
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* Secure monitor software is still processing service client's request.
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*
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* INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR:
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* There is error during the FPGA configuration process.
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* INTEL_SIP_SMC_STATUS_REJECTED:
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* Secure monitor software reject the service client's request.
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*
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* INTEL_SIP_SMC_REG_ERROR:
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* There is error during a read or write operation of the protected registers.
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* INTEL_SIP_SMC_STATUS_ERROR:
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* There is error during the process of service request.
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*
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* INTEL_SIP_SMC_RSU_ERROR:
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* There is error during a remote status update.
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* There is error during the process of remote status update request.
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*/
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#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
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#define INTEL_SIP_SMC_STATUS_OK 0x0
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#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY 0x1
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#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED 0x2
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#define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 0x4
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#define INTEL_SIP_SMC_REG_ERROR 0x5
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#define INTEL_SIP_SMC_STATUS_BUSY 0x1
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#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
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#define INTEL_SIP_SMC_STATUS_ERROR 0x4
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#define INTEL_SIP_SMC_RSU_ERROR 0x7
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/**
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@@ -95,7 +88,7 @@
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* a2-7: not used.
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*
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* Return status:
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* a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
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* a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR.
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* a1-3: not used.
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*/
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#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
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@@ -115,8 +108,8 @@
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* a3-7: not used.
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*
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* Return status:
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* a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
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* INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
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* a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
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* INTEL_SIP_SMC_STATUS_ERROR.
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* a1: 64bit physical address of 1st completed memory block if any completed
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* block, otherwise zero value.
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* a2: 64bit physical address of 2nd completed memory block if any completed
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@@ -133,15 +126,15 @@
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*
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* Sync call used by service driver at EL1 to track the completed write
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* transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE
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* call returns INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY.
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* call returns INTEL_SIP_SMC_STATUS_BUSY.
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*
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* Call register usage:
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* a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
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* a1-7: not used.
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*
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* Return status:
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* a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
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* INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
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* a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_BUSY or
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* INTEL_SIP_SMC_STATUS_ERROR.
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* a1: 64bit physical address of 1st completed memory block.
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* a2: 64bit physical address of 2nd completed memory block if
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* any completed block, otherwise zero value.
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@@ -164,8 +157,8 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
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* a1-7: not used.
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*
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* Return status:
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* a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY or
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* INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
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* a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
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* INTEL_SIP_SMC_STATUS_ERROR.
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* a1-3: not used.
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*/
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#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
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@@ -183,7 +176,7 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
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* a1-7: not used.
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*
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* Return status:
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* a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
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* a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
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* a1: start of physical address of reserved memory block.
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* a2: size of reserved memory block.
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* a3: not used.
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@@ -203,7 +196,7 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
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* a1-7: not used.
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*
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* Return status:
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* a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR.
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* a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
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* a1-3: not used.
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*/
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#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6
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@@ -18,45 +18,37 @@
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/**
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* Status of the sent command, in bit number
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*
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* SVC_COMMAND_STATUS_RECONFIG_REQUEST_OK:
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* Secure firmware accepts the request of FPGA reconfiguration.
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* SVC_STATUS_OK:
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* Secure firmware accepts the request issued by one of service clients.
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*
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* SVC_STATUS_RECONFIG_BUFFER_SUBMITTED:
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* Service client successfully submits FPGA configuration
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* data buffer to secure firmware.
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* SVC_STATUS_BUFFER_SUBMITTED:
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* Service client successfully submits data buffer to secure firmware.
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*
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* SVC_COMMAND_STATUS_RECONFIG_BUFFER_DONE:
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* SVC_STATUS_BUFFER_DONE:
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* Secure firmware completes data process, ready to accept the
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* next WRITE transaction.
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*
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* SVC_COMMAND_STATUS_RECONFIG_COMPLETED:
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* Secure firmware completes FPGA configuration successfully, FPGA should
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* be in user mode.
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* SVC_STATUS_COMPLETED:
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* Secure firmware completes service request successfully. In case of
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* FPGA configuration, FPGA should be in user mode.
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*
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* SVC_COMMAND_STATUS_RECONFIG_BUSY:
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* FPGA configuration is still in process.
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* SVC_COMMAND_STATUS_BUSY:
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* Service request is still in process.
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*
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* SVC_COMMAND_STATUS_RECONFIG_ERROR:
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* Error encountered during FPGA configuration.
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* SVC_COMMAND_STATUS_ERROR:
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* Error encountered during the process of the service request.
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*
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* SVC_STATUS_RSU_OK:
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* Secure firmware accepts the request of remote status update (RSU).
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*
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* SVC_STATUS_RSU_ERROR:
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* Error encountered during remote system update.
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*
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* SVC_STATUS_RSU_NO_SUPPORT:
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* Secure firmware doesn't support RSU retry or notify feature.
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* SVC_STATUS_NO_SUPPORT:
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* Secure firmware doesn't support requested features such as RSU retry
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* or RSU notify.
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*/
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#define SVC_STATUS_RECONFIG_REQUEST_OK 0
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#define SVC_STATUS_RECONFIG_BUFFER_SUBMITTED 1
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#define SVC_STATUS_RECONFIG_BUFFER_DONE 2
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#define SVC_STATUS_RECONFIG_COMPLETED 3
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#define SVC_STATUS_RECONFIG_BUSY 4
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#define SVC_STATUS_RECONFIG_ERROR 5
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#define SVC_STATUS_RSU_OK 6
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#define SVC_STATUS_RSU_ERROR 7
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#define SVC_STATUS_RSU_NO_SUPPORT 8
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#define SVC_STATUS_OK 0
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#define SVC_STATUS_BUFFER_SUBMITTED 1
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#define SVC_STATUS_BUFFER_DONE 2
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#define SVC_STATUS_COMPLETED 3
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#define SVC_STATUS_BUSY 4
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#define SVC_STATUS_ERROR 5
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#define SVC_STATUS_NO_SUPPORT 6
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/**
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* Flag bit for COMMAND_RECONFIG
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@@ -84,32 +76,29 @@ struct stratix10_svc_chan;
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* @COMMAND_NOOP: do 'dummy' request for integration/debug/trouble-shooting
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*
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* @COMMAND_RECONFIG: ask for FPGA configuration preparation, return status
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* is SVC_STATUS_RECONFIG_REQUEST_OK
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* is SVC_STATUS_OK
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*
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* @COMMAND_RECONFIG_DATA_SUBMIT: submit buffer(s) of bit-stream data for the
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* FPGA configuration, return status is SVC_STATUS_RECONFIG_BUFFER_SUBMITTED,
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* or SVC_STATUS_RECONFIG_ERROR
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* FPGA configuration, return status is SVC_STATUS_SUBMITTED or SVC_STATUS_ERROR
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*
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* @COMMAND_RECONFIG_DATA_CLAIM: check the status of the configuration, return
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* status is SVC_STATUS_RECONFIG_COMPLETED, or SVC_STATUS_RECONFIG_BUSY, or
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* SVC_STATUS_RECONFIG_ERROR
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* status is SVC_STATUS_COMPLETED, or SVC_STATUS_BUSY, or SVC_STATUS_ERROR
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*
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* @COMMAND_RECONFIG_STATUS: check the status of the configuration, return
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* status is SVC_STATUS_RECONFIG_COMPLETED, or SVC_STATUS_RECONFIG_BUSY, or
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* SVC_STATUS_RECONFIG_ERROR
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* status is SVC_STATUS_COMPLETED, or SVC_STATUS_BUSY, or SVC_STATUS_ERROR
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*
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* @COMMAND_RSU_STATUS: request remote system update boot log, return status
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* is log data or SVC_STATUS_RSU_ERROR
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*
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* @COMMAND_RSU_UPDATE: set the offset of the bitstream to boot after reboot,
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* return status is SVC_STATUS_RSU_OK or SVC_STATUS_RSU_ERROR
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* return status is SVC_STATUS_OK or SVC_STATUS_ERROR
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*
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* @COMMAND_RSU_NOTIFY: report the status of hard processor system
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* software to firmware, return status is SVC_STATUS_RSU_OK or
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* SVC_STATUS_RSU_ERROR
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* software to firmware, return status is SVC_STATUS_OK or
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* SVC_STATUS_ERROR
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*
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* @COMMAND_RSU_RETRY: query firmware for the current image's retry counter,
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* return status is SVC_STATUS_RSU_OK or SVC_STATUS_RSU_ERROR
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* return status is SVC_STATUS_OK or SVC_STATUS_ERROR
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*/
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enum stratix10_svc_command_code {
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COMMAND_NOOP = 0,
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@@ -42,6 +42,8 @@
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#define ZYNQMP_PM_MAX_QOS 100U
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#define GSS_NUM_REGS (4)
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/* Node capabilities */
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#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
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#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
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@@ -62,6 +64,7 @@
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enum pm_api_id {
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PM_GET_API_VERSION = 1,
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PM_SYSTEM_SHUTDOWN = 12,
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PM_REQUEST_NODE = 13,
|
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PM_RELEASE_NODE,
|
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PM_SET_REQUIREMENT,
|
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@@ -107,6 +110,12 @@ enum pm_ioctl_id {
|
||||
IOCTL_GET_PLL_FRAC_MODE,
|
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IOCTL_SET_PLL_FRAC_DATA,
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IOCTL_GET_PLL_FRAC_DATA,
|
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IOCTL_WRITE_GGS = 12,
|
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IOCTL_READ_GGS = 13,
|
||||
IOCTL_WRITE_PGGS = 14,
|
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IOCTL_READ_PGGS = 15,
|
||||
/* Set healthy bit value */
|
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IOCTL_SET_BOOT_HEALTH_STATUS = 17,
|
||||
};
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||||
|
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enum pm_query_id {
|
||||
@@ -279,6 +288,18 @@ enum dll_reset_type {
|
||||
PM_DLL_RESET_PULSE,
|
||||
};
|
||||
|
||||
enum zynqmp_pm_shutdown_type {
|
||||
ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN,
|
||||
ZYNQMP_PM_SHUTDOWN_TYPE_RESET,
|
||||
ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY,
|
||||
};
|
||||
|
||||
enum zynqmp_pm_shutdown_subtype {
|
||||
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM,
|
||||
ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY,
|
||||
ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct zynqmp_pm_query_data - PM query data
|
||||
* @qid: query ID
|
||||
@@ -293,49 +314,199 @@ struct zynqmp_pm_query_data {
|
||||
u32 arg3;
|
||||
};
|
||||
|
||||
struct zynqmp_eemi_ops {
|
||||
int (*get_api_version)(u32 *version);
|
||||
int (*get_chipid)(u32 *idcode, u32 *version);
|
||||
int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
|
||||
int (*fpga_get_status)(u32 *value);
|
||||
int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
|
||||
int (*clock_enable)(u32 clock_id);
|
||||
int (*clock_disable)(u32 clock_id);
|
||||
int (*clock_getstate)(u32 clock_id, u32 *state);
|
||||
int (*clock_setdivider)(u32 clock_id, u32 divider);
|
||||
int (*clock_getdivider)(u32 clock_id, u32 *divider);
|
||||
int (*clock_setrate)(u32 clock_id, u64 rate);
|
||||
int (*clock_getrate)(u32 clock_id, u64 *rate);
|
||||
int (*clock_setparent)(u32 clock_id, u32 parent_id);
|
||||
int (*clock_getparent)(u32 clock_id, u32 *parent_id);
|
||||
int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
|
||||
int (*reset_assert)(const enum zynqmp_pm_reset reset,
|
||||
const enum zynqmp_pm_reset_action assert_flag);
|
||||
int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
|
||||
int (*init_finalize)(void);
|
||||
int (*set_suspend_mode)(u32 mode);
|
||||
int (*request_node)(const u32 node,
|
||||
const u32 capabilities,
|
||||
const u32 qos,
|
||||
const enum zynqmp_pm_request_ack ack);
|
||||
int (*release_node)(const u32 node);
|
||||
int (*set_requirement)(const u32 node,
|
||||
const u32 capabilities,
|
||||
const u32 qos,
|
||||
const enum zynqmp_pm_request_ack ack);
|
||||
int (*aes)(const u64 address, u32 *out);
|
||||
};
|
||||
|
||||
int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
|
||||
u32 arg2, u32 arg3, u32 *ret_payload);
|
||||
|
||||
#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
|
||||
const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
|
||||
int zynqmp_pm_get_api_version(u32 *version);
|
||||
int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
|
||||
int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
|
||||
int zynqmp_pm_clock_enable(u32 clock_id);
|
||||
int zynqmp_pm_clock_disable(u32 clock_id);
|
||||
int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
|
||||
int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
|
||||
int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
|
||||
int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
|
||||
int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
|
||||
int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
|
||||
int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
|
||||
int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
|
||||
int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
|
||||
int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
|
||||
int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
|
||||
int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
|
||||
int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
|
||||
int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
|
||||
const enum zynqmp_pm_reset_action assert_flag);
|
||||
int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
|
||||
int zynqmp_pm_init_finalize(void);
|
||||
int zynqmp_pm_set_suspend_mode(u32 mode);
|
||||
int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
|
||||
const u32 qos, const enum zynqmp_pm_request_ack ack);
|
||||
int zynqmp_pm_release_node(const u32 node);
|
||||
int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
|
||||
const u32 qos,
|
||||
const enum zynqmp_pm_request_ack ack);
|
||||
int zynqmp_pm_aes_engine(const u64 address, u32 *out);
|
||||
int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
|
||||
int zynqmp_pm_fpga_get_status(u32 *value);
|
||||
int zynqmp_pm_write_ggs(u32 index, u32 value);
|
||||
int zynqmp_pm_read_ggs(u32 index, u32 *value);
|
||||
int zynqmp_pm_write_pggs(u32 index, u32 value);
|
||||
int zynqmp_pm_read_pggs(u32 index, u32 *value);
|
||||
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
|
||||
int zynqmp_pm_set_boot_health_status(u32 value);
|
||||
#else
|
||||
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
|
||||
{
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
static inline int zynqmp_pm_get_api_version(u32 *version)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
|
||||
u32 *out)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_clock_enable(u32 clock_id)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_clock_disable(u32 clock_id)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
|
||||
const enum zynqmp_pm_reset_action assert_flag)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
|
||||
u32 *status)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_init_finalize(void)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_set_suspend_mode(u32 mode)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
|
||||
const u32 qos,
|
||||
const enum zynqmp_pm_request_ack ack)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_release_node(const u32 node)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_set_requirement(const u32 node,
|
||||
const u32 capabilities,
|
||||
const u32 qos,
|
||||
const enum zynqmp_pm_request_ack ack)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
|
||||
const u32 flags)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_fpga_get_status(u32 *value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
static inline int zynqmp_pm_set_boot_health_status(u32 value)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __FIRMWARE_ZYNQMP_H__ */
|
||||
|
||||
Reference in New Issue
Block a user