Merge branch 'devel-stable' into for-linus
Conflicts: arch/arm/Kconfig arch/arm/mach-ns9xxx/include/mach/uncompress.h
This commit is contained in:
Russell King
@@ -49,7 +49,7 @@ struct gic_chip_data {
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* Default make them NULL.
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*/
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struct irq_chip gic_arch_extn = {
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.irq_ack = NULL,
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.irq_eoi = NULL,
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.irq_mask = NULL,
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.irq_unmask = NULL,
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.irq_retrigger = NULL,
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@@ -84,21 +84,12 @@ static inline unsigned int gic_irq(struct irq_data *d)
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/*
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* Routines to acknowledge, disable and enable interrupts
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*/
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static void gic_ack_irq(struct irq_data *d)
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{
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spin_lock(&irq_controller_lock);
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if (gic_arch_extn.irq_ack)
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gic_arch_extn.irq_ack(d);
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writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
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spin_unlock(&irq_controller_lock);
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}
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static void gic_mask_irq(struct irq_data *d)
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{
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u32 mask = 1 << (d->irq % 32);
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spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
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writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
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if (gic_arch_extn.irq_mask)
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gic_arch_extn.irq_mask(d);
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spin_unlock(&irq_controller_lock);
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@@ -111,10 +102,21 @@ static void gic_unmask_irq(struct irq_data *d)
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spin_lock(&irq_controller_lock);
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if (gic_arch_extn.irq_unmask)
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gic_arch_extn.irq_unmask(d);
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writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
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writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
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spin_unlock(&irq_controller_lock);
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}
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static void gic_eoi_irq(struct irq_data *d)
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{
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if (gic_arch_extn.irq_eoi) {
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spin_lock(&irq_controller_lock);
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gic_arch_extn.irq_eoi(d);
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spin_unlock(&irq_controller_lock);
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}
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writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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void __iomem *base = gic_dist_base(d);
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@@ -138,7 +140,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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if (gic_arch_extn.irq_set_type)
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gic_arch_extn.irq_set_type(d, type);
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val = readl(base + GIC_DIST_CONFIG + confoff);
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val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
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if (type == IRQ_TYPE_LEVEL_HIGH)
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val &= ~confmask;
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else if (type == IRQ_TYPE_EDGE_RISING)
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@@ -148,15 +150,15 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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* As recommended by the spec, disable the interrupt before changing
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* the configuration
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*/
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if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
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writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
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if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
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enabled = true;
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}
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writel(val, base + GIC_DIST_CONFIG + confoff);
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writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
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if (enabled)
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writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
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writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
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spin_unlock(&irq_controller_lock);
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@@ -188,8 +190,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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spin_lock(&irq_controller_lock);
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d->node = cpu;
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val = readl(reg) & ~mask;
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writel(val | bit, reg);
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val = readl_relaxed(reg) & ~mask;
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writel_relaxed(val | bit, reg);
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spin_unlock(&irq_controller_lock);
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return 0;
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@@ -218,11 +220,10 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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unsigned int cascade_irq, gic_irq;
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unsigned long status;
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/* primary controller ack'ing */
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chip->irq_ack(&desc->irq_data);
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chained_irq_enter(chip, desc);
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spin_lock(&irq_controller_lock);
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status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
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status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
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spin_unlock(&irq_controller_lock);
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gic_irq = (status & 0x3ff);
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@@ -236,15 +237,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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generic_handle_irq(cascade_irq);
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out:
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/* primary controller unmasking */
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chip->irq_unmask(&desc->irq_data);
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chained_irq_exit(chip, desc);
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}
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static struct irq_chip gic_chip = {
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.name = "GIC",
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.irq_ack = gic_ack_irq,
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.irq_mask = gic_mask_irq,
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.irq_unmask = gic_unmask_irq,
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.irq_eoi = gic_eoi_irq,
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.irq_set_type = gic_set_type,
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.irq_retrigger = gic_retrigger,
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#ifdef CONFIG_SMP
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@@ -272,13 +272,13 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
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cpumask |= cpumask << 8;
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cpumask |= cpumask << 16;
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writel(0, base + GIC_DIST_CTRL);
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writel_relaxed(0, base + GIC_DIST_CTRL);
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/*
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* Find out how many interrupts are supported.
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* The GIC only supports up to 1020 interrupt sources.
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*/
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gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
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gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
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gic_irqs = (gic_irqs + 1) * 32;
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if (gic_irqs > 1020)
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gic_irqs = 1020;
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@@ -287,26 +287,26 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < gic_irqs; i += 16)
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writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
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writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
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/*
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* Set all global interrupts to this CPU only.
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*/
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for (i = 32; i < gic_irqs; i += 4)
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writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
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writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
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/*
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* Set priority on all global interrupts.
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*/
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for (i = 32; i < gic_irqs; i += 4)
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writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
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writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
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/*
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* Disable all interrupts. Leave the PPI and SGIs alone
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* as these enables are banked registers.
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*/
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for (i = 32; i < gic_irqs; i += 32)
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writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
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writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
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/*
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* Limit number of interrupts registered to the platform maximum
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@@ -319,12 +319,12 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
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* Setup the Linux IRQ subsystem.
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*/
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for (i = irq_start; i < irq_limit; i++) {
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irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
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irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
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irq_set_chip_data(i, gic);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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writel(1, base + GIC_DIST_CTRL);
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writel_relaxed(1, base + GIC_DIST_CTRL);
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}
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static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
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@@ -337,17 +337,17 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
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* Deal with the banked PPI and SGI interrupts - disable all
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* PPI interrupts, ensure all SGI interrupts are enabled.
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*/
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writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
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writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
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writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
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writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
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/*
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* Set priority on PPI and SGI interrupts
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*/
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for (i = 0; i < 32; i += 4)
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writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
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writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
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writel(0xf0, base + GIC_CPU_PRIMASK);
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writel(1, base + GIC_CPU_CTRL);
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writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
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writel_relaxed(1, base + GIC_CPU_CTRL);
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}
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void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
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@@ -391,7 +391,13 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
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{
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unsigned long map = *cpus_addr(*mask);
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/*
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* Ensure that stores to Normal memory are visible to the
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* other CPUs before issuing the IPI.
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*/
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dsb();
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/* this always happens on GIC0 */
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writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
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writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
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}
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#endif
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