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Merge tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull ARM SoC multiplatform updates from Olof Johansson:
 "More multiplatform enablement for ARM platforms.  The ones converted
  in this branch are:

   - bcm2835
   - cns3xxx
   - sirf
   - nomadik
   - msx
   - spear
   - tegra
   - ux500

  We're getting close to having most of them converted!

  One of the larger platforms remaining is Samsung Exynos, and there are
  a bunch of supporting patches in this merge window for it.  There was
  a patch in this branch to a early version of multiplatform conversion,
  but it ended up being reverted due to need of more bake time.  The
  revert commit is part of the branch since it would have required
  rebasing multiple dependent branches and they were stable by then"

* tag 'multiplatform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (70 commits)
  mmc: sdhci-s3c: Fix operation on non-single image Samsung platforms
  clocksource: nomadik-mtu: fix up clocksource/timer
  Revert "ARM: exynos: enable multiplatform support"
  ARM: SPEAr13xx: Fix typo "ARCH_HAVE_CPUFREQ"
  ARM: exynos: enable multiplatform support
  rtc: s3c: make header file local
  mtd: onenand/samsung: make regs-onenand.h file local
  thermal/exynos: remove unnecessary header inclusions
  mmc: sdhci-s3c: remove platform dependencies
  ARM: samsung: move mfc device definition to s5p-dev-mfc.c
  ARM: exynos: move debug-macro.S to include/debug/
  ARM: exynos: prepare for sparse IRQ
  ARM: exynos: introduce EXYNOS_ATAGS symbol
  ARM: tegra: build assembly files with -march=armv7-a
  ARM: Push selects for TWD/SCU into machine entries
  ARM: ux500: build hotplug.o for ARMv7-a
  ARM: ux500: move to multiplatform
  ARM: ux500: make remaining headers local
  ARM: ux500: make irqs.h local to platform
  ARM: ux500: get rid of <mach/[hardware|db8500-regs].h>
  ...
This commit is contained in:
Linus Torvalds
2013-05-02 09:38:16 -07:00
parent 97b1007a29 2fdfe1c26f
commit 99c6bcf46d
236 changed files with 1832 additions and 2885 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/mach-cns3xxx/Kconfig
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@@ -1,8 +1,20 @@
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
select ARM_GIC
select CPU_V6K
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_CACHE_L2X0
select MIGHT_HAVE_PCI
select PCI_DOMAINS if PCI
help
Support for Cavium Networks CNS3XXX platform.
menu "CNS3XXX platform type"
depends on ARCH_CNS3XXX
config MACH_CNS3420VB
bool "Support for CNS3420 Validation Board"
depends on ATAGS
help
Include support for the Cavium Networks CNS3420 MPCore Platform
Baseboard.

8
arch/arm/mach-cns3xxx/Makefile
View File

@@ -1,3 +1,5 @@
obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
obj-$(CONFIG_PCI) += pcie.o
obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
cns3xxx-y += core.o pm.o
cns3xxx-$(CONFIG_ATAGS) += devices.o
cns3xxx-$(CONFIG_PCI) += pcie.o
cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o

6
arch/arm/mach-cns3xxx/cns3420vb.c
View File

@@ -31,9 +31,8 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include <mach/pm.h>
#include "cns3xxx.h"
#include "pm.h"
#include "core.h"
#include "devices.h"
@@ -247,6 +246,7 @@ static void __init cns3420_map_io(void)
MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
.atag_offset = 0x100,
.nr_irqs = NR_IRQS_CNS3XXX,
.map_io = cns3420_map_io,
.init_irq = cns3xxx_init_irq,
.init_time = cns3xxx_timer_init,

7
arch/arm/mach-cns3xxx/include/mach/cns3xxx.h → arch/arm/mach-cns3xxx/cns3xxx.h
View File

@@ -526,6 +526,8 @@ int cns3xxx_cpu_clock(void);
/*
* ARM11 MPCore interrupt sources (primary GIC)
*/
#define IRQ_TC11MP_GIC_START 32
#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
@@ -597,9 +599,4 @@ int cns3xxx_cpu_clock(void);
#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
#undef NR_IRQS
#define NR_IRQS NR_IRQS_CNS3XXX
#endif
#endif /* __MACH_BOARD_CNS3XXX_H */

121
arch/arm/mach-cns3xxx/core.c
View File

@@ -13,12 +13,18 @@
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/usb/ehci_pdriver.h>
#include <linux/usb/ohci_pdriver.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/cns3xxx.h>
#include "cns3xxx.h"
#include "core.h"
#include "pm.h"
static struct map_desc cns3xxx_io_desc[] __initdata = {
{
@@ -256,3 +262,116 @@ void __init cns3xxx_l2x0_init(void)
}
#endif /* CONFIG_CACHE_L2X0 */
static int csn3xxx_usb_power_on(struct platform_device *pdev)
{
/*
* EHCI and OHCI share the same clock and power,
* resetting twice would cause the 1st controller been reset.
* Therefore only do power up at the first up device, and
* power down at the last down device.
*
* Set USB AHB INCR length to 16
*/
if (atomic_inc_return(&usb_pwr_ref) == 1) {
cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
MISC_CHIP_CONFIG_REG);
}
return 0;
}
static void csn3xxx_usb_power_off(struct platform_device *pdev)
{
/*
* EHCI and OHCI share the same clock and power,
* resetting twice would cause the 1st controller been reset.
* Therefore only do power up at the first up device, and
* power down at the last down device.
*/
if (atomic_dec_return(&usb_pwr_ref) == 0)
cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
}
static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
.power_on = csn3xxx_usb_power_on,
.power_off = csn3xxx_usb_power_off,
};
static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
.num_ports = 1,
.power_on = csn3xxx_usb_power_on,
.power_off = csn3xxx_usb_power_off,
};
static struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
{ "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL },
{},
};
static void __init cns3xxx_init(void)
{
struct device_node *dn;
cns3xxx_l2x0_init();
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci");
if (of_device_is_available(dn)) {
u32 tmp;
tmp = __raw_readl(MISC_SATA_POWER_MODE);
tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
__raw_writel(tmp, MISC_SATA_POWER_MODE);
/* Enable SATA PHY */
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
/* Enable SATA Clock */
cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
/* De-Asscer SATA Reset */
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
}
dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
if (of_device_is_available(dn)) {
u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
u32 gpioa_pins = __raw_readl(gpioa);
/* MMC/SD pins share with GPIOA */
gpioa_pins |= 0x1fff0004;
__raw_writel(gpioa_pins, gpioa);
cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
}
pm_power_off = cns3xxx_power_off;
of_platform_populate(NULL, of_default_bus_match_table,
cns3xxx_auxdata, NULL);
}
static const char *cns3xxx_dt_compat[] __initdata = {
"cavium,cns3410",
"cavium,cns3420",
NULL,
};
DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx")
.dt_compat = cns3xxx_dt_compat,
.nr_irqs = NR_IRQS_CNS3XXX,
.map_io = cns3xxx_map_io,
.init_irq = cns3xxx_init_irq,
.init_time = cns3xxx_timer_init,
.init_machine = cns3xxx_init,
.restart = cns3xxx_restart,
MACHINE_END

5
arch/arm/mach-cns3xxx/devices.c
View File

@@ -16,9 +16,8 @@
#include <linux/compiler.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include <mach/pm.h>
#include "cns3xxx.h"
#include "pm.h"
#include "core.h"
#include "devices.h"

19
arch/arm/mach-cns3xxx/include/mach/debug-macro.S
View File

@@ -1,19 +0,0 @@
/*
* Debugging macro include header
*
* Copyright 1994-1999 Russell King
* Copyright 2008 Cavium Networks
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
.macro addruart,rp,rv,tmp
mov \rp, #0x00009000
orr \rv, \rp, #0xf0000000 @ virtual base
orr \rp, \rp, #0x10000000
.endm
#include <asm/hardware/debug-pl01x.S>

24
arch/arm/mach-cns3xxx/include/mach/irqs.h
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@@ -1,24 +0,0 @@
/*
* Copyright 2000 Deep Blue Solutions Ltd.
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define IRQ_LOCALTIMER 29
#define IRQ_LOCALWDOG 30
#define IRQ_TC11MP_GIC_START 32
#include <mach/cns3xxx.h>
#ifndef NR_IRQS
#error "NR_IRQS not defined by the board-specific files"
#endif
#endif

12
arch/arm/mach-cns3xxx/include/mach/timex.h
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@@ -1,12 +0,0 @@
/*
* Cavium Networks architecture timex specifications
*
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#define CLOCK_TICK_RATE (50000000 / 16)

53
arch/arm/mach-cns3xxx/include/mach/uncompress.h
View File

@@ -1,53 +0,0 @@
/*
* Copyright 2003 ARM Limited
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#include <asm/mach-types.h>
#include <mach/cns3xxx.h>
#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
/*
* Return the UART base address
*/
static inline unsigned long get_uart_base(void)
{
if (machine_is_cns3420vb())
return CNS3XXX_UART0_BASE;
else
return 0;
}
/*
* This does not append a newline
*/
static inline void putc(int c)
{
unsigned long base = get_uart_base();
while (AMBA_UART_FR(base) & (1 << 5))
barrier();
AMBA_UART_DR(base) = c;
}
static inline void flush(void)
{
unsigned long base = get_uart_base();
while (AMBA_UART_FR(base) & (1 << 3))
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()

2
arch/arm/mach-cns3xxx/pcie.c
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@@ -20,7 +20,7 @@
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <asm/mach/map.h>
#include <mach/cns3xxx.h>
#include "cns3xxx.h"
#include "core.h"
enum cns3xxx_access_type {

4
arch/arm/mach-cns3xxx/pm.c
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@@ -11,8 +11,8 @@
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/atomic.h>
#include <mach/cns3xxx.h>
#include <mach/pm.h>
#include "cns3xxx.h"
#include "pm.h"
#include "core.h"
void cns3xxx_pwr_clk_en(unsigned int block)

0
arch/arm/mach-cns3xxx/include/mach/pm.h → arch/arm/mach-cns3xxx/pm.h
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