Merge remote-tracking branch 'asoc/topic/arizona' into asoc-next
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@@ -95,6 +95,8 @@ struct arizona {
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struct arizona_pdata pdata;
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unsigned int external_dcvdd:1;
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int irq;
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struct irq_domain *virq;
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struct regmap_irq_chip_data *aod_irq_chip;
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@@ -77,7 +77,7 @@ struct arizona_micbias {
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int mV; /** Regulated voltage */
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unsigned int ext_cap:1; /** External capacitor fitted */
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unsigned int discharge:1; /** Actively discharge */
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unsigned int fast_start:1; /** Enable aggressive startup ramp rate */
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unsigned int soft_start:1; /** Disable aggressive startup ramp rate */
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unsigned int bypass:1; /** Use bypass mode */
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};
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@@ -215,6 +215,9 @@
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#define ARIZONA_DAC_DIGITAL_VOLUME_6R 0x43D
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#define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E
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#define ARIZONA_NOISE_GATE_SELECT_6R 0x43F
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#define ARIZONA_DRE_ENABLE 0x440
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#define ARIZONA_DRE_CONTROL_2 0x442
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#define ARIZONA_DRE_CONTROL_3 0x443
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#define ARIZONA_DAC_AEC_CONTROL_1 0x450
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#define ARIZONA_NOISE_GATE_CONTROL 0x458
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#define ARIZONA_PDM_SPK1_CTRL_1 0x490
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@@ -1002,6 +1005,7 @@
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#define ARIZONA_DSP2_CLOCKING_1 0x1201
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#define ARIZONA_DSP2_STATUS_1 0x1204
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#define ARIZONA_DSP2_STATUS_2 0x1205
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#define ARIZONA_DSP2_STATUS_3 0x1206
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#define ARIZONA_DSP2_SCRATCH_0 0x1240
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#define ARIZONA_DSP2_SCRATCH_1 0x1241
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#define ARIZONA_DSP2_SCRATCH_2 0x1242
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@@ -1010,6 +1014,7 @@
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#define ARIZONA_DSP3_CLOCKING_1 0x1301
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#define ARIZONA_DSP3_STATUS_1 0x1304
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#define ARIZONA_DSP3_STATUS_2 0x1305
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#define ARIZONA_DSP3_STATUS_3 0x1306
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#define ARIZONA_DSP3_SCRATCH_0 0x1340
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#define ARIZONA_DSP3_SCRATCH_1 0x1341
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#define ARIZONA_DSP3_SCRATCH_2 0x1342
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@@ -1018,6 +1023,7 @@
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#define ARIZONA_DSP4_CLOCKING_1 0x1401
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#define ARIZONA_DSP4_STATUS_1 0x1404
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#define ARIZONA_DSP4_STATUS_2 0x1405
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#define ARIZONA_DSP4_STATUS_3 0x1406
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#define ARIZONA_DSP4_SCRATCH_0 0x1440
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#define ARIZONA_DSP4_SCRATCH_1 0x1441
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#define ARIZONA_DSP4_SCRATCH_2 0x1442
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@@ -3129,6 +3135,47 @@
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#define ARIZONA_OUT6R_NGATE_SRC_SHIFT 0 /* OUT6R_NGATE_SRC - [11:0] */
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#define ARIZONA_OUT6R_NGATE_SRC_WIDTH 12 /* OUT6R_NGATE_SRC - [11:0] */
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/*
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* R1088 (0x440) - DRE Enable
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*/
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#define ARIZONA_DRE3L_ENA 0x0010 /* DRE3L_ENA */
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#define ARIZONA_DRE3L_ENA_MASK 0x0010 /* DRE3L_ENA */
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#define ARIZONA_DRE3L_ENA_SHIFT 4 /* DRE3L_ENA */
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#define ARIZONA_DRE3L_ENA_WIDTH 1 /* DRE3L_ENA */
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#define ARIZONA_DRE2R_ENA 0x0008 /* DRE2R_ENA */
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#define ARIZONA_DRE2R_ENA_MASK 0x0008 /* DRE2R_ENA */
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#define ARIZONA_DRE2R_ENA_SHIFT 3 /* DRE2R_ENA */
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#define ARIZONA_DRE2R_ENA_WIDTH 1 /* DRE2R_ENA */
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#define ARIZONA_DRE2L_ENA 0x0004 /* DRE2L_ENA */
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#define ARIZONA_DRE2L_ENA_MASK 0x0004 /* DRE2L_ENA */
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#define ARIZONA_DRE2L_ENA_SHIFT 2 /* DRE2L_ENA */
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#define ARIZONA_DRE2L_ENA_WIDTH 1 /* DRE2L_ENA */
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#define ARIZONA_DRE1R_ENA 0x0002 /* DRE1R_ENA */
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#define ARIZONA_DRE1R_ENA_MASK 0x0002 /* DRE1R_ENA */
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#define ARIZONA_DRE1R_ENA_SHIFT 1 /* DRE1R_ENA */
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#define ARIZONA_DRE1R_ENA_WIDTH 1 /* DRE1R_ENA */
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#define ARIZONA_DRE1L_ENA 0x0001 /* DRE1L_ENA */
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#define ARIZONA_DRE1L_ENA_MASK 0x0001 /* DRE1L_ENA */
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#define ARIZONA_DRE1L_ENA_SHIFT 0 /* DRE1L_ENA */
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#define ARIZONA_DRE1L_ENA_WIDTH 1 /* DRE1L_ENA */
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/*
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* R1090 (0x442) - DRE Control 2
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*/
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#define ARIZONA_DRE_T_LOW_MASK 0x3F00 /* DRE_T_LOW - [13:8] */
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#define ARIZONA_DRE_T_LOW_SHIFT 8 /* DRE_T_LOW - [13:8] */
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#define ARIZONA_DRE_T_LOW_WIDTH 6 /* DRE_T_LOW - [13:8] */
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/*
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* R1091 (0x443) - DRE Control 3
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*/
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#define ARIZONA_DRE_GAIN_SHIFT_MASK 0xC000 /* DRE_GAIN_SHIFT - [15:14] */
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#define ARIZONA_DRE_GAIN_SHIFT_SHIFT 14 /* DRE_GAIN_SHIFT - [15:14] */
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#define ARIZONA_DRE_GAIN_SHIFT_WIDTH 2 /* DRE_GAIN_SHIFT - [15:14] */
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#define ARIZONA_DRE_LOW_LEVEL_ABS_MASK 0x000F /* LOW_LEVEL_ABS - [3:0] */
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#define ARIZONA_DRE_LOW_LEVEL_ABS_SHIFT 0 /* LOW_LEVEL_ABS - [3:0] */
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#define ARIZONA_DRE_LOW_LEVEL_ABS_WIDTH 4 /* LOW_LEVEL_ABS - [3:0] */
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/*
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* R1104 (0x450) - DAC AEC Control 1
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*/
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