Merge branch 'x86-irq-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-irq-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, acpi/irq: Define gsi_end when X86_IO_APIC is undefined x86, irq: Kill io_apic_renumber_irq x86, acpi/irq: Handle isa irqs that are not identity mapped to gsi's. x86, ioapic: Simplify probe_nr_irqs_gsi. x86, ioapic: Optimize pin_2_irq x86, ioapic: Move nr_ioapic_registers calculation to mp_register_ioapic. x86, ioapic: In mpparse use mp_register_ioapic x86, ioapic: Teach mp_register_ioapic to compute a global gsi_end x86, ioapic: Fix the types of gsi values x86, ioapic: Fix io_apic_redir_entries to return the number of entries. x86, ioapic: Only export mp_find_ioapic and mp_find_ioapic_pin in io_apic.h x86, acpi/irq: Generalize mp_config_acpi_legacy_irqs x86, acpi/irq: Fix acpi_sci_ioapic_setup so it has both bus_irq and gsi x86, acpi/irq: pci device dev->irq is an isa irq not a gsi x86, acpi/irq: Teach acpi_get_override_irq to take a gsi not an isa_irq x86, acpi/irq: Introduce apci_isa_irq_to_gsi
This commit is contained in:
Linus Torvalds
@@ -131,24 +131,6 @@ int es7000_plat;
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static unsigned int base;
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static int
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es7000_rename_gsi(int ioapic, int gsi)
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{
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if (es7000_plat == ES7000_ZORRO)
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return gsi;
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if (!base) {
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int i;
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for (i = 0; i < nr_ioapics; i++)
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base += nr_ioapic_registers[i];
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}
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if (!ioapic && (gsi < 16))
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gsi += base;
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return gsi;
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}
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static int __cpuinit wakeup_secondary_cpu_via_mip(int cpu, unsigned long eip)
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{
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unsigned long vect = 0, psaival = 0;
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@@ -190,7 +172,6 @@ static void setup_unisys(void)
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es7000_plat = ES7000_ZORRO;
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else
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es7000_plat = ES7000_CLASSIC;
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ioapic_renumber_irq = es7000_rename_gsi;
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}
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/*
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@@ -89,6 +89,9 @@ int nr_ioapics;
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/* IO APIC gsi routing info */
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struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
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/* The last gsi number used */
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u32 gsi_end;
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/* MP IRQ source entries */
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struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
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@@ -1013,10 +1016,9 @@ static inline int irq_trigger(int idx)
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return MPBIOS_trigger(idx);
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}
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int (*ioapic_renumber_irq)(int ioapic, int irq);
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static int pin_2_irq(int idx, int apic, int pin)
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{
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int irq, i;
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int irq;
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int bus = mp_irqs[idx].srcbus;
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/*
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@@ -1028,18 +1030,12 @@ static int pin_2_irq(int idx, int apic, int pin)
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if (test_bit(bus, mp_bus_not_pci)) {
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irq = mp_irqs[idx].srcbusirq;
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} else {
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/*
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* PCI IRQs are mapped in order
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*/
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i = irq = 0;
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while (i < apic)
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irq += nr_ioapic_registers[i++];
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irq += pin;
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/*
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* For MPS mode, so far only needed by ES7000 platform
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*/
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if (ioapic_renumber_irq)
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irq = ioapic_renumber_irq(apic, irq);
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u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
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if (gsi >= NR_IRQS_LEGACY)
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irq = gsi;
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else
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irq = gsi_end + 1 + gsi;
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}
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#ifdef CONFIG_X86_32
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@@ -1950,20 +1946,8 @@ static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
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void __init enable_IO_APIC(void)
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{
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union IO_APIC_reg_01 reg_01;
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int i8259_apic, i8259_pin;
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int apic;
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unsigned long flags;
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/*
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* The number of IO-APIC IRQ registers (== #pins):
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*/
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for (apic = 0; apic < nr_ioapics; apic++) {
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raw_spin_lock_irqsave(&ioapic_lock, flags);
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reg_01.raw = io_apic_read(apic, 1);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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nr_ioapic_registers[apic] = reg_01.bits.entries+1;
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}
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if (!legacy_pic->nr_legacy_irqs)
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return;
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@@ -3858,27 +3842,20 @@ int __init io_apic_get_redir_entries (int ioapic)
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reg_01.raw = io_apic_read(ioapic, 1);
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raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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return reg_01.bits.entries;
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/* The register returns the maximum index redir index
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* supported, which is one less than the total number of redir
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* entries.
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*/
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return reg_01.bits.entries + 1;
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}
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void __init probe_nr_irqs_gsi(void)
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{
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int nr = 0;
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int nr;
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nr = acpi_probe_gsi();
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if (nr > nr_irqs_gsi) {
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nr = gsi_end + 1 + NR_IRQS_LEGACY;
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if (nr > nr_irqs_gsi)
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nr_irqs_gsi = nr;
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} else {
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/* for acpi=off or acpi is not compiled in */
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int idx;
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nr = 0;
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for (idx = 0; idx < nr_ioapics; idx++)
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nr += io_apic_get_redir_entries(idx) + 1;
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if (nr > nr_irqs_gsi)
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nr_irqs_gsi = nr;
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}
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printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
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}
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@@ -4085,22 +4062,27 @@ int __init io_apic_get_version(int ioapic)
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return reg_01.bits.version;
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}
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int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
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int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
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{
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int i;
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int ioapic, pin, idx;
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if (skip_ioapic_setup)
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return -1;
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for (i = 0; i < mp_irq_entries; i++)
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if (mp_irqs[i].irqtype == mp_INT &&
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mp_irqs[i].srcbusirq == bus_irq)
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break;
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if (i >= mp_irq_entries)
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ioapic = mp_find_ioapic(gsi);
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if (ioapic < 0)
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return -1;
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*trigger = irq_trigger(i);
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*polarity = irq_polarity(i);
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pin = mp_find_ioapic_pin(ioapic, gsi);
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if (pin < 0)
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return -1;
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idx = find_irq_entry(ioapic, pin, mp_INT);
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if (idx < 0)
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return -1;
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*trigger = irq_trigger(idx);
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*polarity = irq_polarity(idx);
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return 0;
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}
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@@ -4241,7 +4223,7 @@ void __init ioapic_insert_resources(void)
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}
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}
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int mp_find_ioapic(int gsi)
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int mp_find_ioapic(u32 gsi)
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{
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int i = 0;
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@@ -4256,7 +4238,7 @@ int mp_find_ioapic(int gsi)
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return -1;
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}
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int mp_find_ioapic_pin(int ioapic, int gsi)
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int mp_find_ioapic_pin(int ioapic, u32 gsi)
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{
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if (WARN_ON(ioapic == -1))
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return -1;
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@@ -4284,6 +4266,7 @@ static int bad_ioapic(unsigned long address)
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void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
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{
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int idx = 0;
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int entries;
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if (bad_ioapic(address))
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return;
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@@ -4302,9 +4285,17 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
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* Build basic GSI lookup table to facilitate gsi->io_apic lookups
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* and to prevent reprogramming of IOAPIC pins (PCI GSIs).
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*/
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entries = io_apic_get_redir_entries(idx);
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mp_gsi_routing[idx].gsi_base = gsi_base;
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mp_gsi_routing[idx].gsi_end = gsi_base +
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io_apic_get_redir_entries(idx);
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mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
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/*
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* The number of IO-APIC IRQ registers (== #pins):
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*/
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nr_ioapic_registers[idx] = entries;
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if (mp_gsi_routing[idx].gsi_end > gsi_end)
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gsi_end = mp_gsi_routing[idx].gsi_end;
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printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
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"GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
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