Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Arnd Bergmann:
"We get support for three new 32-bit SoC platforms this time.
The amount of changes in arch/arm for any of them is miniscule, as all
the interesting code is in device driver subsystems (irqchip, clk,
pinctrl, ...) these days. I'm listing them here, as the addition of
the Kconfig statement is the main relevant milestone for a new
platform. In each case, some drivers are are shared with existing
platforms, while other drivers are added for v4.7 as well, or come in
a later release.
- The Aspeed platform is probably the most interesting one, this is
what most whitebox servers use as their baseboard management
controller. We get support for the very common ast2400 and ast2500
SoCs. The OpenBMC project focuses on this chip, and the LWN
article about their ELC 2016 presentation at
https://lwn.net/Articles/683320/
triggered the submission, but the code comes from IBM's OpenPOWER
team rather than the team at Facebook. There are still a lot more
drivers that need to get added over time, and I hope both teams can
work together on that.
- OXNAS is an old platform for Network Attached Storage devices from
Oxford Semiconductor. There are models with ARM10 (!) and
ARM11MPCore cores, but for now, we only support the original ARM9
based versions. The product lineup was subsequently part of PLX,
Avago and now the new Broadcom Ltd.
https://wiki.openwrt.org/doc/hardware/soc/soc.oxnas
has some more information.
- V2M-MPS2 is a prototyping platform from ARM for their Cortex-M
cores and is related to the existing Realview / Versatile Express
lineup, but without MMU.
We now support various NOMMU platforms, so adding a new one is
fairly straightforward.
http://infocenter.arm.com/help/topic/com.arm.doc.100112_0100_03_en/
has detailed information about the platform.
Other noteworthy updates:
- Work on LPC32xx has resumed, and Vladimir Zapolskiy and Sylvain
Lemieux are now maintaining the platform.
This is an older ARM9 based platform from NXP (not Freescale), but
it remains in use in embedded markets.
- Kevin Hilman is now co-maintaining the Amlogic Meson platform for
both 32-bit and 64-bit ARM, and started contributing some patches.
- As is often the case, work on the OMAP platforms makes up the bulk
of the actual SoC code changes in arch/arm, but there isn't a lot
of that either"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits)
MAINTAINERS: ARM/Amlogic: add co-maintainer, misc. updates
MAINTAINERS: add ARM/NXP LPC32XX SoC specific drivers to the section
MAINTAINERS: add new maintainers of NXP LPC32xx SoC
MAINTAINERS: move ARM/NXP LPC32xx record to ARM section
arm: Add Aspeed machine
ARM: lpc32xx: remove duplicate const on lpc32xx_auxdata_lookup
ARM: lpc32xx: remove leftovers of legacy clock source and provider drivers
ARM: lpc32xx: remove reboot header file
ARM: dove: Remove CLK_IS_ROOT
ARM: orion5x: Remove CLK_IS_ROOT
ARM: mv78xx0: Remove CLK_IS_ROOT
ARM: davinci: da850: use clk->set_parent for async3
ARM: davinci: Move clock init after ioremap.
MAINTAINERS: Update ARM Versatile Express platform entry
ARM: vexpress/mps2: introduce MPS2 platform
MAINTAINERS: add maintainer entry for ARM/OXNAS platform
ARM: Add new mach-oxnas
irqchip: versatile-fpga: add new compatible for OX810SE SoC
ARM: uniphier: correct the call order of of_node_put()
MAINTAINERS: fix stale TI DaVinci entries
...
此提交包含在：
Linus Torvalds
@@ -17,13 +17,6 @@
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/i2c-pnx.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <asm/system_info.h>
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@@ -43,19 +36,6 @@ void lpc32xx_get_uid(u32 devid[4])
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devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
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}
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/*
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* Returns SYSCLK source
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* 0 = PLL397, 1 = main oscillator
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*/
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int clk_is_sysclk_mainosc(void)
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{
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if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
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LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
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return 1;
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return 0;
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}
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/*
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* Detects and returns IRAM size for the device variation
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*/
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@@ -87,81 +67,6 @@ u32 lpc32xx_return_iram_size(void)
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}
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EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size);
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/*
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* Computes PLL rate from PLL register and input clock
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*/
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u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
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{
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u32 ilfreq, p, m, n, fcco, fref, cfreq;
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int mode;
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/*
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* PLL requirements
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* ifreq must be >= 1MHz and <= 20MHz
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* FCCO must be >= 156MHz and <= 320MHz
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* FREF must be >= 1MHz and <= 27MHz
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* Assume the passed input data is not valid
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*/
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ilfreq = ifreq;
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m = pllsetup->pll_m;
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n = pllsetup->pll_n;
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p = pllsetup->pll_p;
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mode = (pllsetup->cco_bypass_b15 << 2) |
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(pllsetup->direct_output_b14 << 1) |
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pllsetup->fdbk_div_ctrl_b13;
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switch (mode) {
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case 0x0: /* Non-integer mode */
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cfreq = (m * ilfreq) / (2 * p * n);
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fcco = (m * ilfreq) / n;
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fref = ilfreq / n;
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break;
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case 0x1: /* integer mode */
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cfreq = (m * ilfreq) / n;
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fcco = (m * ilfreq) / (n * 2 * p);
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fref = ilfreq / n;
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break;
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case 0x2:
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case 0x3: /* Direct mode */
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cfreq = (m * ilfreq) / n;
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fcco = cfreq;
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fref = ilfreq / n;
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break;
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case 0x4:
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case 0x5: /* Bypass mode */
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cfreq = ilfreq / (2 * p);
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fcco = 156000000;
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fref = 1000000;
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break;
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case 0x6:
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case 0x7: /* Direct bypass mode */
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default:
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cfreq = ilfreq;
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fcco = 156000000;
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fref = 1000000;
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break;
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}
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if (fcco < 156000000 || fcco > 320000000)
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cfreq = 0;
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if (fref < 1000000 || fref > 27000000)
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cfreq = 0;
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return (u32) cfreq;
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}
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u32 clk_get_pclk_div(void)
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{
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return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
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}
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static struct map_desc lpc32xx_io_desc[] __initdata = {
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{
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.virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
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@@ -19,37 +19,15 @@
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#ifndef __LPC32XX_COMMON_H
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#define __LPC32XX_COMMON_H
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#include <mach/board.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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/*
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* Other arch specific structures and functions
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*/
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extern void lpc32xx_timer_init(void);
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extern void __init lpc32xx_init_irq(void);
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extern void __init lpc32xx_map_io(void);
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extern void __init lpc32xx_serial_init(void);
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/*
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* Structure used for setting up and querying the PLLS
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*/
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struct clk_pll_setup {
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int analog_on;
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int cco_bypass_b15;
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int direct_output_b14;
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int fdbk_div_ctrl_b13;
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int pll_p;
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int pll_n;
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u32 pll_m;
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};
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extern int clk_is_sysclk_mainosc(void);
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extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup);
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extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
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extern u32 clk_get_pclk_div(void);
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/*
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* Returns the LPC32xx unique 128-bit chip ID
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*/
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@@ -159,7 +159,7 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
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.dma_filter = pl08x_filter_id,
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};
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static const struct of_dev_auxdata const lpc32xx_auxdata_lookup[] __initconst = {
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static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
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OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
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OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
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OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
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