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drm/i915/chv: Don't use PCS group access reads

Ver a proveniência 
All PCS groups access reads return 0xffffffff, so we can't use group
access for RMW cycles. Instead target each spline separately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
[danvet: Fight conflict with misplaced ; .... ARGH!]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Este cometimento está contido em:
Ville Syrjälä
2014-04-09 13:29:02 +03:00
cometido por Daniel Vetter
ascendente d2152b2524
cometimento 97fd4d5c81
3 ficheiros modificados com 62 adições e 16 eliminações
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32
drivers/gpu/drm/i915/intel_hdmi.c
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@@ -1259,13 +1259,21 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
mutex_lock(&dev_priv->dpio_lock);
/* Propagate soft reset to data lane reset */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
val |= CHV_PCS_REQ_SOFTRESET_EN;
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
val |= CHV_PCS_REQ_SOFTRESET_EN;
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
mutex_unlock(&dev_priv->dpio_lock);
}
@@ -1285,13 +1293,21 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
mutex_lock(&dev_priv->dpio_lock);
/* Deassert soft data lane reset*/
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
val |= CHV_PCS_REQ_SOFTRESET_EN;
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
val |= CHV_PCS_REQ_SOFTRESET_EN;
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
/* Program Tx latency optimal setting */
for (i = 0; i < 4; i++) {