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[PATCH] IB: sparse endianness cleanup

瀏覽代碼 
Fix sparse warnings.  Use __be* where appropriate.

Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
This commit is contained in:
Sean Hefty
2005-08-13 21:05:57 -07:00
committed by Roland Dreier
父節點 92a6b34bf4
當前提交 97f52eb438
共有 34 個文件被更改，包括 565 次插入 和 562 次删除
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24
drivers/infiniband/hw/mthca/mthca_av.c
查看文件

@@ -41,16 +41,16 @@
#include "mthca_dev.h"
struct mthca_av {
u32 port_pd;
u8 reserved1;
u8 g_slid;
u16 dlid;
u8 reserved2;
u8 gid_index;
u8 msg_sr;
u8 hop_limit;
u32 sl_tclass_flowlabel;
u32 dgid[4];
__be32 port_pd;
u8 reserved1;
u8 g_slid;
__be16 dlid;
u8 reserved2;
u8 gid_index;
u8 msg_sr;
u8 hop_limit;
__be32 sl_tclass_flowlabel;
__be32 dgid[4];
};
int mthca_create_ah(struct mthca_dev *dev,
@@ -128,7 +128,7 @@ on_hca_fail:
av, (unsigned long) ah->avdma);
for (j = 0; j < 8; ++j)
printk(KERN_DEBUG " [%2x] %08x\n",
j * 4, be32_to_cpu(((u32 *) av)[j]));
j * 4, be32_to_cpu(((__be32 *) av)[j]));
}
if (ah->type == MTHCA_AH_ON_HCA) {
@@ -169,7 +169,7 @@ int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
header->lrh.service_level = be32_to_cpu(ah->av->sl_tclass_flowlabel) >> 28;
header->lrh.destination_lid = ah->av->dlid;
header->lrh.source_lid = ah->av->g_slid & 0x7f;
header->lrh.source_lid = cpu_to_be16(ah->av->g_slid & 0x7f);
if (ah->av->g_slid & 0x80) {
header->grh_present = 1;
header->grh.traffic_class =

40
drivers/infiniband/hw/mthca/mthca_cmd.c
查看文件

@@ -220,20 +220,20 @@ static int mthca_cmd_post(struct mthca_dev *dev,
* (and some architectures such as ia64 implement memcpy_toio
* in terms of writeb).
*/
__raw_writel(cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
__raw_writel(cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
__raw_writel(cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
__raw_writel(cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
__raw_writel(cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
__raw_writel(cpu_to_be32(token << 16), dev->hcr + 5 * 4);
__raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
__raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
__raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
__raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
__raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
__raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
/* __raw_writel may not order writes. */
wmb();
__raw_writel(cpu_to_be32((1 << HCR_GO_BIT) |
(event ? (1 << HCA_E_BIT) : 0) |
(op_modifier << HCR_OPMOD_SHIFT) |
op), dev->hcr + 6 * 4);
__raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
(event ? (1 << HCA_E_BIT) : 0) |
(op_modifier << HCR_OPMOD_SHIFT) |
op), dev->hcr + 6 * 4);
out:
up(&dev->cmd.hcr_sem);
@@ -274,12 +274,14 @@ static int mthca_cmd_poll(struct mthca_dev *dev,
goto out;
}
if (out_is_imm) {
memcpy_fromio(out_param, dev->hcr + HCR_OUT_PARAM_OFFSET, sizeof (u64));
be64_to_cpus(out_param);
}
if (out_is_imm)
*out_param =
(u64) be32_to_cpu((__force __be32)
__raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
(u64) be32_to_cpu((__force __be32)
__raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
*status = be32_to_cpu(__raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
*status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
out:
up(&dev->cmd.poll_sem);
@@ -1122,7 +1124,7 @@ int mthca_INIT_HCA(struct mthca_dev *dev,
u8 *status)
{
struct mthca_mailbox *mailbox;
u32 *inbox;
__be32 *inbox;
int err;
#define INIT_HCA_IN_SIZE 0x200
@@ -1343,7 +1345,7 @@ int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *st
int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
{
struct mthca_mailbox *mailbox;
u64 *inbox;
__be64 *inbox;
int err;
mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
@@ -1514,7 +1516,7 @@ int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
if (i % 8 == 0)
printk(" [%02x] ", i * 4);
printk(" %08x",
be32_to_cpu(((u32 *) mailbox->buf)[i + 2]));
be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
if ((i + 1) % 8 == 0)
printk("\n");
}
@@ -1534,7 +1536,7 @@ int mthca_MODIFY_QP(struct mthca_dev *dev, int trans, u32 num,
if (i % 8 == 0)
printk("[%02x] ", i * 4);
printk(" %08x",
be32_to_cpu(((u32 *) mailbox->buf)[i + 2]));
be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
if ((i + 1) % 8 == 0)
printk("\n");
}

89
drivers/infiniband/hw/mthca/mthca_cq.c
查看文件

@@ -57,21 +57,21 @@ enum {
* Must be packed because start is 64 bits but only aligned to 32 bits.
*/
struct mthca_cq_context {
u32 flags;
u64 start;
u32 logsize_usrpage;
u32 error_eqn; /* Tavor only */
u32 comp_eqn;
u32 pd;
u32 lkey;
u32 last_notified_index;
u32 solicit_producer_index;
u32 consumer_index;
u32 producer_index;
u32 cqn;
u32 ci_db; /* Arbel only */
u32 state_db; /* Arbel only */
u32 reserved;
__be32 flags;
__be64 start;
__be32 logsize_usrpage;
__be32 error_eqn; /* Tavor only */
__be32 comp_eqn;
__be32 pd;
__be32 lkey;
__be32 last_notified_index;
__be32 solicit_producer_index;
__be32 consumer_index;
__be32 producer_index;
__be32 cqn;
__be32 ci_db; /* Arbel only */
__be32 state_db; /* Arbel only */
u32 reserved;
} __attribute__((packed));
#define MTHCA_CQ_STATUS_OK ( 0 << 28)
@@ -110,31 +110,31 @@ enum {
};
struct mthca_cqe {
u32 my_qpn;
u32 my_ee;
u32 rqpn;
u16 sl_g_mlpath;
u16 rlid;
u32 imm_etype_pkey_eec;
u32 byte_cnt;
u32 wqe;
u8 opcode;
u8 is_send;
u8 reserved;
u8 owner;
__be32 my_qpn;
__be32 my_ee;
__be32 rqpn;
__be16 sl_g_mlpath;
__be16 rlid;
__be32 imm_etype_pkey_eec;
__be32 byte_cnt;
__be32 wqe;
u8 opcode;
u8 is_send;
u8 reserved;
u8 owner;
};
struct mthca_err_cqe {
u32 my_qpn;
u32 reserved1[3];
u8 syndrome;
u8 reserved2;
u16 db_cnt;
u32 reserved3;
u32 wqe;
u8 opcode;
u8 reserved4[2];
u8 owner;
__be32 my_qpn;
u32 reserved1[3];
u8 syndrome;
u8 reserved2;
__be16 db_cnt;
u32 reserved3;
__be32 wqe;
u8 opcode;
u8 reserved4[2];
u8 owner;
};
#define MTHCA_CQ_ENTRY_OWNER_SW (0 << 7)
@@ -193,7 +193,7 @@ static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
int incr)
{
u32 doorbell[2];
__be32 doorbell[2];
if (mthca_is_memfree(dev)) {
*cq->set_ci_db = cpu_to_be32(cq->cons_index);
@@ -293,7 +293,7 @@ static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
{
int err;
int dbd;
u32 new_wqe;
__be32 new_wqe;
if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
mthca_dbg(dev, "local QP operation err "
@@ -586,13 +586,13 @@ int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
{
u32 doorbell[2];
__be32 doorbell[2];
doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
MTHCA_TAVOR_CQ_DB_REQ_NOT) |
to_mcq(cq)->cqn);
doorbell[1] = 0xffffffff;
doorbell[1] = (__force __be32) 0xffffffff;
mthca_write64(doorbell,
to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
@@ -604,9 +604,9 @@ int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
{
struct mthca_cq *cq = to_mcq(ibcq);
u32 doorbell[2];
__be32 doorbell[2];
u32 sn;
u32 ci;
__be32 ci;
sn = cq->arm_sn & 3;
ci = cpu_to_be32(cq->cons_index);
@@ -813,7 +813,6 @@ int mthca_init_cq(struct mthca_dev *dev, int nent,
cq_context->flags = cpu_to_be32(MTHCA_CQ_STATUS_OK |
MTHCA_CQ_STATE_DISARMED |
MTHCA_CQ_FLAG_TR);
cq_context->start = cpu_to_be64(0);
cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
if (ctx)
cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
@@ -906,7 +905,7 @@ void mthca_free_cq(struct mthca_dev *dev,
mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
if (0) {
u32 *ctx = mailbox->buf;
__be32 *ctx = mailbox->buf;
int j;
printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",

15
drivers/infiniband/hw/mthca/mthca_dev.h
查看文件

@@ -333,14 +333,13 @@ extern void __buggy_use_of_MTHCA_PUT(void);
#define MTHCA_PUT(dest, source, offset) \
do { \
__typeof__(source) *__p = \
(__typeof__(source) *) ((char *) (dest) + (offset)); \
void *__d = ((char *) (dest) + (offset)); \
switch (sizeof(source)) { \
case 1: *__p = (source); break; \
case 2: *__p = cpu_to_be16(source); break; \
case 4: *__p = cpu_to_be32(source); break; \
case 8: *__p = cpu_to_be64(source); break; \
default: __buggy_use_of_MTHCA_PUT(); \
case 1: *(u8 *) __d = (source); break; \
case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
default: __buggy_use_of_MTHCA_PUT(); \
} \
} while (0)
@@ -435,7 +434,7 @@ int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
struct ib_recv_wr **bad_wr);
int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
int index, int *dbd, u32 *new_wqe);
int index, int *dbd, __be32 *new_wqe);
int mthca_alloc_qp(struct mthca_dev *dev,
struct mthca_pd *pd,
struct mthca_cq *send_cq,

12
drivers/infiniband/hw/mthca/mthca_doorbell.h
查看文件

@@ -58,13 +58,13 @@ static inline void mthca_write64_raw(__be64 val, void __iomem *dest)
__raw_writeq((__force u64) val, dest);
}
static inline void mthca_write64(u32 val[2], void __iomem *dest,
static inline void mthca_write64(__be32 val[2], void __iomem *dest,
spinlock_t *doorbell_lock)
{
__raw_writeq(*(u64 *) val, dest);
}
static inline void mthca_write_db_rec(u32 val[2], u32 *db)
static inline void mthca_write_db_rec(__be32 val[2], __be32 *db)
{
*(u64 *) db = *(u64 *) val;
}
@@ -87,18 +87,18 @@ static inline void mthca_write64_raw(__be64 val, void __iomem *dest)
__raw_writel(((__force u32 *) &val)[1], dest + 4);
}
static inline void mthca_write64(u32 val[2], void __iomem *dest,
static inline void mthca_write64(__be32 val[2], void __iomem *dest,
spinlock_t *doorbell_lock)
{
unsigned long flags;
spin_lock_irqsave(doorbell_lock, flags);
__raw_writel(val[0], dest);
__raw_writel(val[1], dest + 4);
__raw_writel((__force u32) val[0], dest);
__raw_writel((__force u32) val[1], dest + 4);
spin_unlock_irqrestore(doorbell_lock, flags);
}
static inline void mthca_write_db_rec(u32 val[2], u32 *db)
static inline void mthca_write_db_rec(__be32 val[2], __be32 *db)
{
db[0] = val[0];
wmb();

62
drivers/infiniband/hw/mthca/mthca_eq.c
查看文件

@@ -52,18 +52,18 @@ enum {
* Must be packed because start is 64 bits but only aligned to 32 bits.
*/
struct mthca_eq_context {
u32 flags;
u64 start;
u32 logsize_usrpage;
u32 tavor_pd; /* reserved for Arbel */
u8 reserved1[3];
u8 intr;
u32 arbel_pd; /* lost_count for Tavor */
u32 lkey;
u32 reserved2[2];
u32 consumer_index;
u32 producer_index;
u32 reserved3[4];
__be32 flags;
__be64 start;
__be32 logsize_usrpage;
__be32 tavor_pd; /* reserved for Arbel */
u8 reserved1[3];
u8 intr;
__be32 arbel_pd; /* lost_count for Tavor */
__be32 lkey;
u32 reserved2[2];
__be32 consumer_index;
__be32 producer_index;
u32 reserved3[4];
} __attribute__((packed));
#define MTHCA_EQ_STATUS_OK ( 0 << 28)
@@ -128,28 +128,28 @@ struct mthca_eqe {
union {
u32 raw[6];
struct {
u32 cqn;
__be32 cqn;
} __attribute__((packed)) comp;
struct {
u16 reserved1;
u16 token;
u32 reserved2;
u8 reserved3[3];
u8 status;
u64 out_param;
u16 reserved1;
__be16 token;
u32 reserved2;
u8 reserved3[3];
u8 status;
__be64 out_param;
} __attribute__((packed)) cmd;
struct {
u32 qpn;
__be32 qpn;
} __attribute__((packed)) qp;
struct {
u32 cqn;
u32 reserved1;
u8 reserved2[3];
u8 syndrome;
__be32 cqn;
u32 reserved1;
u8 reserved2[3];
u8 syndrome;
} __attribute__((packed)) cq_err;
struct {
u32 reserved1[2];
u32 port;
u32 reserved1[2];
__be32 port;
} __attribute__((packed)) port_change;
} event;
u8 reserved3[3];
@@ -168,7 +168,7 @@ static inline u64 async_mask(struct mthca_dev *dev)
static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
{
u32 doorbell[2];
__be32 doorbell[2];
doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_SET_CI | eq->eqn);
doorbell[1] = cpu_to_be32(ci & (eq->nent - 1));
@@ -191,8 +191,8 @@ static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u
{
/* See comment in tavor_set_eq_ci() above. */
wmb();
__raw_writel(cpu_to_be32(ci), dev->eq_regs.arbel.eq_set_ci_base +
eq->eqn * 8);
__raw_writel((__force u32) cpu_to_be32(ci),
dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8);
/* We still want ordering, just not swabbing, so add a barrier */
mb();
}
@@ -207,7 +207,7 @@ static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci)
static inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn)
{
u32 doorbell[2];
__be32 doorbell[2];
doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_REQ_NOT | eqn);
doorbell[1] = 0;
@@ -225,7 +225,7 @@ static inline void arbel_eq_req_not(struct mthca_dev *dev, u32 eqn_mask)
static inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn)
{
if (!mthca_is_memfree(dev)) {
u32 doorbell[2];
__be32 doorbell[2];
doorbell[0] = cpu_to_be32(MTHCA_EQ_DB_DISARM_CQ | eqn);
doorbell[1] = cpu_to_be32(cqn);

2
drivers/infiniband/hw/mthca/mthca_mad.c
查看文件

@@ -194,7 +194,7 @@ int mthca_process_mad(struct ib_device *ibdev,
{
int err;
u8 status;
u16 slid = in_wc ? in_wc->slid : IB_LID_PERMISSIVE;
u16 slid = in_wc ? in_wc->slid : be16_to_cpu(IB_LID_PERMISSIVE);
/* Forward locally generated traps to the SM */
if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP &&

36
drivers/infiniband/hw/mthca/mthca_mcg.c
查看文件

@@ -42,10 +42,10 @@ enum {
};
struct mthca_mgm {
u32 next_gid_index;
u32 reserved[3];
u8 gid[16];
u32 qp[MTHCA_QP_PER_MGM];
__be32 next_gid_index;
u32 reserved[3];
u8 gid[16];
__be32 qp[MTHCA_QP_PER_MGM];
};
static const u8 zero_gid[16]; /* automatically initialized to 0 */
@@ -94,10 +94,14 @@ static int find_mgm(struct mthca_dev *dev,
if (0)
mthca_dbg(dev, "Hash for %04x:%04x:%04x:%04x:"
"%04x:%04x:%04x:%04x is %04x\n",
be16_to_cpu(((u16 *) gid)[0]), be16_to_cpu(((u16 *) gid)[1]),
be16_to_cpu(((u16 *) gid)[2]), be16_to_cpu(((u16 *) gid)[3]),
be16_to_cpu(((u16 *) gid)[4]), be16_to_cpu(((u16 *) gid)[5]),
be16_to_cpu(((u16 *) gid)[6]), be16_to_cpu(((u16 *) gid)[7]),
be16_to_cpu(((__be16 *) gid)[0]),
be16_to_cpu(((__be16 *) gid)[1]),
be16_to_cpu(((__be16 *) gid)[2]),
be16_to_cpu(((__be16 *) gid)[3]),
be16_to_cpu(((__be16 *) gid)[4]),
be16_to_cpu(((__be16 *) gid)[5]),
be16_to_cpu(((__be16 *) gid)[6]),
be16_to_cpu(((__be16 *) gid)[7]),
*hash);
*index = *hash;
@@ -258,14 +262,14 @@ int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
if (index == -1) {
mthca_err(dev, "MGID %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x "
"not found\n",
be16_to_cpu(((u16 *) gid->raw)[0]),
be16_to_cpu(((u16 *) gid->raw)[1]),
be16_to_cpu(((u16 *) gid->raw)[2]),
be16_to_cpu(((u16 *) gid->raw)[3]),
be16_to_cpu(((u16 *) gid->raw)[4]),
be16_to_cpu(((u16 *) gid->raw)[5]),
be16_to_cpu(((u16 *) gid->raw)[6]),
be16_to_cpu(((u16 *) gid->raw)[7]));
be16_to_cpu(((__be16 *) gid->raw)[0]),
be16_to_cpu(((__be16 *) gid->raw)[1]),
be16_to_cpu(((__be16 *) gid->raw)[2]),
be16_to_cpu(((__be16 *) gid->raw)[3]),
be16_to_cpu(((__be16 *) gid->raw)[4]),
be16_to_cpu(((__be16 *) gid->raw)[5]),
be16_to_cpu(((__be16 *) gid->raw)[6]),
be16_to_cpu(((__be16 *) gid->raw)[7]));
err = -EINVAL;
goto out;
}

4
drivers/infiniband/hw/mthca/mthca_memfree.c
查看文件

@@ -482,7 +482,7 @@ void mthca_cleanup_user_db_tab(struct mthca_dev *dev, struct mthca_uar *uar,
}
}
int mthca_alloc_db(struct mthca_dev *dev, int type, u32 qn, u32 **db)
int mthca_alloc_db(struct mthca_dev *dev, int type, u32 qn, __be32 **db)
{
int group;
int start, end, dir;
@@ -565,7 +565,7 @@ found:
page->db_rec[j] = cpu_to_be64((qn << 8) | (type << 5));
*db = (u32 *) &page->db_rec[j];
*db = (__be32 *) &page->db_rec[j];
out:
up(&dev->db_tab->mutex);

4
drivers/infiniband/hw/mthca/mthca_memfree.h
查看文件

@@ -138,7 +138,7 @@ enum {
struct mthca_db_page {
DECLARE_BITMAP(used, MTHCA_DB_REC_PER_PAGE);
u64 *db_rec;
__be64 *db_rec;
dma_addr_t mapping;
};
@@ -173,7 +173,7 @@ void mthca_cleanup_user_db_tab(struct mthca_dev *dev, struct mthca_uar *uar,
int mthca_init_db_tab(struct mthca_dev *dev);
void mthca_cleanup_db_tab(struct mthca_dev *dev);
int mthca_alloc_db(struct mthca_dev *dev, int type, u32 qn, u32 **db);
int mthca_alloc_db(struct mthca_dev *dev, int type, u32 qn, __be32 **db);
void mthca_free_db(struct mthca_dev *dev, int type, int db_index);
#endif /* MTHCA_MEMFREE_H */

32
drivers/infiniband/hw/mthca/mthca_mr.c
查看文件

@@ -51,18 +51,18 @@ struct mthca_mtt {
* Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
*/
struct mthca_mpt_entry {
u32 flags;
u32 page_size;
u32 key;
u32 pd;
u64 start;
u64 length;
u32 lkey;
u32 window_count;
u32 window_count_limit;
u64 mtt_seg;
u32 mtt_sz; /* Arbel only */
u32 reserved[2];
__be32 flags;
__be32 page_size;
__be32 key;
__be32 pd;
__be64 start;
__be64 length;
__be32 lkey;
__be32 window_count;
__be32 window_count_limit;
__be64 mtt_seg;
__be32 mtt_sz; /* Arbel only */
u32 reserved[2];
} __attribute__((packed));
#define MTHCA_MPT_FLAG_SW_OWNS (0xfUL << 28)
@@ -248,7 +248,7 @@ int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
int start_index, u64 *buffer_list, int list_len)
{
struct mthca_mailbox *mailbox;
u64 *mtt_entry;
__be64 *mtt_entry;
int err = 0;
u8 status;
int i;
@@ -390,7 +390,7 @@ int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
for (i = 0; i < sizeof (struct mthca_mpt_entry) / 4; ++i) {
if (i % 4 == 0)
printk("[%02x] ", i * 4);
printk(" %08x", be32_to_cpu(((u32 *) mpt_entry)[i]));
printk(" %08x", be32_to_cpu(((__be32 *) mpt_entry)[i]));
if ((i + 1) % 4 == 0)
printk("\n");
}
@@ -563,7 +563,7 @@ int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
for (i = 0; i < sizeof (struct mthca_mpt_entry) / 4; ++i) {
if (i % 4 == 0)
printk("[%02x] ", i * 4);
printk(" %08x", be32_to_cpu(((u32 *) mpt_entry)[i]));
printk(" %08x", be32_to_cpu(((__be32 *) mpt_entry)[i]));
if ((i + 1) % 4 == 0)
printk("\n");
}
@@ -670,7 +670,7 @@ int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
mpt_entry.length = cpu_to_be64(list_len * (1ull << fmr->attr.page_size));
mpt_entry.start = cpu_to_be64(iova);
writel(mpt_entry.lkey, &fmr->mem.tavor.mpt->key);
__raw_writel((__force u32) mpt_entry.lkey, &fmr->mem.tavor.mpt->key);
memcpy_toio(&fmr->mem.tavor.mpt->start, &mpt_entry.start,
offsetof(struct mthca_mpt_entry, window_count) -
offsetof(struct mthca_mpt_entry, start));

16
drivers/infiniband/hw/mthca/mthca_provider.c
查看文件

@@ -81,10 +81,10 @@ static int mthca_query_device(struct ib_device *ibdev,
}
props->device_cap_flags = mdev->device_cap_flags;
props->vendor_id = be32_to_cpup((u32 *) (out_mad->data + 36)) &
props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
0xffffff;
props->vendor_part_id = be16_to_cpup((u16 *) (out_mad->data + 30));
props->hw_ver = be16_to_cpup((u16 *) (out_mad->data + 32));
props->vendor_part_id = be16_to_cpup((__be16 *) (out_mad->data + 30));
props->hw_ver = be16_to_cpup((__be16 *) (out_mad->data + 32));
memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
memcpy(&props->node_guid, out_mad->data + 12, 8);
@@ -138,16 +138,16 @@ static int mthca_query_port(struct ib_device *ibdev,
goto out;
}
props->lid = be16_to_cpup((u16 *) (out_mad->data + 16));
props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
props->lmc = out_mad->data[34] & 0x7;
props->sm_lid = be16_to_cpup((u16 *) (out_mad->data + 18));
props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
props->sm_sl = out_mad->data[36] & 0xf;
props->state = out_mad->data[32] & 0xf;
props->phys_state = out_mad->data[33] >> 4;
props->port_cap_flags = be32_to_cpup((u32 *) (out_mad->data + 20));
props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
props->gid_tbl_len = to_mdev(ibdev)->limits.gid_table_len;
props->pkey_tbl_len = to_mdev(ibdev)->limits.pkey_table_len;
props->qkey_viol_cntr = be16_to_cpup((u16 *) (out_mad->data + 48));
props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
props->active_width = out_mad->data[31] & 0xf;
props->active_speed = out_mad->data[35] >> 4;
@@ -223,7 +223,7 @@ static int mthca_query_pkey(struct ib_device *ibdev,
goto out;
}
*pkey = be16_to_cpu(((u16 *) out_mad->data)[index % 32]);
*pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
out:
kfree(in_mad);

6
drivers/infiniband/hw/mthca/mthca_provider.h
查看文件

@@ -182,9 +182,9 @@ struct mthca_cq {
/* Next fields are Arbel only */
int set_ci_db_index;
u32 *set_ci_db;
__be32 *set_ci_db;
int arm_db_index;
u32 *arm_db;
__be32 *arm_db;
int arm_sn;
union {
@@ -207,7 +207,7 @@ struct mthca_wq {
int wqe_shift;
int db_index; /* Arbel only */
u32 *db;
__be32 *db;
};
struct mthca_qp {

187
drivers/infiniband/hw/mthca/mthca_qp.c
查看文件

@@ -97,62 +97,62 @@ enum {
};
struct mthca_qp_path {
u32 port_pkey;
u8 rnr_retry;
u8 g_mylmc;
u16 rlid;
u8 ackto;
u8 mgid_index;
u8 static_rate;
u8 hop_limit;
u32 sl_tclass_flowlabel;
u8 rgid[16];
__be32 port_pkey;
u8 rnr_retry;
u8 g_mylmc;
__be16 rlid;
u8 ackto;
u8 mgid_index;
u8 static_rate;
u8 hop_limit;
__be32 sl_tclass_flowlabel;
u8 rgid[16];
} __attribute__((packed));
struct mthca_qp_context {
u32 flags;
u32 tavor_sched_queue; /* Reserved on Arbel */
u8 mtu_msgmax;
u8 rq_size_stride; /* Reserved on Tavor */
u8 sq_size_stride; /* Reserved on Tavor */
u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
u32 usr_page;
u32 local_qpn;
u32 remote_qpn;
u32 reserved1[2];
__be32 flags;
__be32 tavor_sched_queue; /* Reserved on Arbel */
u8 mtu_msgmax;
u8 rq_size_stride; /* Reserved on Tavor */
u8 sq_size_stride; /* Reserved on Tavor */
u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
__be32 usr_page;
__be32 local_qpn;
__be32 remote_qpn;
u32 reserved1[2];
struct mthca_qp_path pri_path;
struct mthca_qp_path alt_path;
u32 rdd;
u32 pd;
u32 wqe_base;
u32 wqe_lkey;
u32 params1;
u32 reserved2;
u32 next_send_psn;
u32 cqn_snd;
u32 snd_wqe_base_l; /* Next send WQE on Tavor */
u32 snd_db_index; /* (debugging only entries) */
u32 last_acked_psn;
u32 ssn;
u32 params2;
u32 rnr_nextrecvpsn;
u32 ra_buff_indx;
u32 cqn_rcv;
u32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
u32 rcv_db_index; /* (debugging only entries) */
u32 qkey;
u32 srqn;
u32 rmsn;
u16 rq_wqe_counter; /* reserved on Tavor */
u16 sq_wqe_counter; /* reserved on Tavor */
u32 reserved3[18];
__be32 rdd;
__be32 pd;
__be32 wqe_base;
__be32 wqe_lkey;
__be32 params1;
__be32 reserved2;
__be32 next_send_psn;
__be32 cqn_snd;
__be32 snd_wqe_base_l; /* Next send WQE on Tavor */
__be32 snd_db_index; /* (debugging only entries) */
__be32 last_acked_psn;
__be32 ssn;
__be32 params2;
__be32 rnr_nextrecvpsn;
__be32 ra_buff_indx;
__be32 cqn_rcv;
__be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
__be32 rcv_db_index; /* (debugging only entries) */
__be32 qkey;
__be32 srqn;
__be32 rmsn;
__be16 rq_wqe_counter; /* reserved on Tavor */
__be16 sq_wqe_counter; /* reserved on Tavor */
u32 reserved3[18];
} __attribute__((packed));
struct mthca_qp_param {
u32 opt_param_mask;
u32 reserved1;
__be32 opt_param_mask;
u32 reserved1;
struct mthca_qp_context context;
u32 reserved2[62];
u32 reserved2[62];
} __attribute__((packed));
enum {
@@ -191,62 +191,62 @@ enum {
};
struct mthca_next_seg {
u32 nda_op; /* [31:6] next WQE [4:0] next opcode */
u32 ee_nds; /* [31:8] next EE [7] DBD [6] F [5:0] next WQE size */
u32 flags; /* [3] CQ [2] Event [1] Solicit */
u32 imm; /* immediate data */
__be32 nda_op; /* [31:6] next WQE [4:0] next opcode */
__be32 ee_nds; /* [31:8] next EE [7] DBD [6] F [5:0] next WQE size */
__be32 flags; /* [3] CQ [2] Event [1] Solicit */
__be32 imm; /* immediate data */
};
struct mthca_tavor_ud_seg {
u32 reserved1;
u32 lkey;
u64 av_addr;
u32 reserved2[4];
u32 dqpn;
u32 qkey;
u32 reserved3[2];
u32 reserved1;
__be32 lkey;
__be64 av_addr;
u32 reserved2[4];
__be32 dqpn;
__be32 qkey;
u32 reserved3[2];
};
struct mthca_arbel_ud_seg {
u32 av[8];
u32 dqpn;
u32 qkey;
u32 reserved[2];
__be32 av[8];
__be32 dqpn;
__be32 qkey;
u32 reserved[2];
};
struct mthca_bind_seg {
u32 flags; /* [31] Atomic [30] rem write [29] rem read */
u32 reserved;
u32 new_rkey;
u32 lkey;
u64 addr;
u64 length;
__be32 flags; /* [31] Atomic [30] rem write [29] rem read */
u32 reserved;
__be32 new_rkey;
__be32 lkey;
__be64 addr;
__be64 length;
};
struct mthca_raddr_seg {
u64 raddr;
u32 rkey;
u32 reserved;
__be64 raddr;
__be32 rkey;
u32 reserved;
};
struct mthca_atomic_seg {
u64 swap_add;
u64 compare;
__be64 swap_add;
__be64 compare;
};
struct mthca_data_seg {
u32 byte_count;
u32 lkey;
u64 addr;
__be32 byte_count;
__be32 lkey;
__be64 addr;
};
struct mthca_mlx_seg {
u32 nda_op;
u32 nds;
u32 flags; /* [17] VL15 [16] SLR [14:12] static rate
__be32 nda_op;
__be32 nds;
__be32 flags; /* [17] VL15 [16] SLR [14:12] static rate
[11:8] SL [3] C [2] E */
u16 rlid;
u16 vcrc;
__be16 rlid;
__be16 vcrc;
};
static const u8 mthca_opcode[] = {
@@ -1459,6 +1459,7 @@ static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
{
int header_size;
int err;
u16 pkey;
ib_ud_header_init(256, /* assume a MAD */
sqp->ud_header.grh_present,
@@ -1469,8 +1470,8 @@ static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
return err;
mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
(sqp->ud_header.lrh.destination_lid == 0xffff ?
MTHCA_MLX_SLR : 0) |
(sqp->ud_header.lrh.destination_lid ==
IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
(sqp->ud_header.lrh.service_level << 8));
mlx->rlid = sqp->ud_header.lrh.destination_lid;
mlx->vcrc = 0;
@@ -1490,18 +1491,16 @@ static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
}
sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
if (sqp->ud_header.lrh.destination_lid == 0xffff)
sqp->ud_header.lrh.source_lid = 0xffff;
if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
if (!sqp->qp.ibqp.qp_num)
ib_get_cached_pkey(&dev->ib_dev, sqp->port,
sqp->pkey_index,
&sqp->ud_header.bth.pkey);
sqp->pkey_index, &pkey);
else
ib_get_cached_pkey(&dev->ib_dev, sqp->port,
wr->wr.ud.pkey_index,
&sqp->ud_header.bth.pkey);
cpu_to_be16s(&sqp->ud_header.bth.pkey);
wr->wr.ud.pkey_index, &pkey);
sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
@@ -1744,7 +1743,7 @@ int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
out:
if (likely(nreq)) {
u32 doorbell[2];
__be32 doorbell[2];
doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
qp->send_wqe_offset) | f0 | op0);
@@ -1845,7 +1844,7 @@ int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
out:
if (likely(nreq)) {
u32 doorbell[2];
__be32 doorbell[2];
doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
@@ -2066,7 +2065,7 @@ int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
out:
if (likely(nreq)) {
u32 doorbell[2];
__be32 doorbell[2];
doorbell[0] = cpu_to_be32((nreq << 24) |
((qp->sq.head & 0xffff) << 8) |
@@ -2176,7 +2175,7 @@ out:
}
int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
int index, int *dbd, u32 *new_wqe)
int index, int *dbd, __be32 *new_wqe)
{
struct mthca_next_seg *next;