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[MIPS] Define MIPS_CPU_IRQ_BASE in generic header

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The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto
2007-01-08 02:14:29 +09:00
committed by Ralf Baechle
parent b6ec8f069b
commit 97dcb82de6
40 changed files with 128 additions and 98 deletions
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13
include/asm-mips/sgi/ip22.h
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@@ -21,15 +21,16 @@
* HAL2 driver). This will prevent many complications, trust me ;-)
*/
#include <irq.h>
#include <asm/sgi/ioc.h>
#define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */
#define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */
#define SGINT_LOCAL0 24 /* 8 local0 irq levels */
#define SGINT_LOCAL1 32 /* 8 local1 irq levels */
#define SGINT_LOCAL2 40 /* 8 local2 vectored irq levels */
#define SGINT_LOCAL3 48 /* 8 local3 vectored irq levels */
#define SGINT_END 56 /* End of 'spaces' */
#define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */
#define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */
#define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */
#define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */
#define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */
#define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */
/*
* Individual interrupt definitions for the Indy and Indigo2