Merge tag 'kvm-4.15-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM updates from Radim Krčmář: "First batch of KVM changes for 4.15 Common: - Python 3 support in kvm_stat - Accounting of slabs to kmemcg ARM: - Optimized arch timer handling for KVM/ARM - Improvements to the VGIC ITS code and introduction of an ITS reset ioctl - Unification of the 32-bit fault injection logic - More exact external abort matching logic PPC: - Support for running hashed page table (HPT) MMU mode on a host that is using the radix MMU mode; single threaded mode on POWER 9 is added as a pre-requisite - Resolution of merge conflicts with the last second 4.14 HPT fixes - Fixes and cleanups s390: - Some initial preparation patches for exitless interrupts and crypto - New capability for AIS migration - Fixes x86: - Improved emulation of LAPIC timer mode changes, MCi_STATUS MSRs, and after-reset state - Refined dependencies for VMX features - Fixes for nested SMI injection - A lot of cleanups" * tag 'kvm-4.15-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (89 commits) KVM: s390: provide a capability for AIS state migration KVM: s390: clear_io_irq() requests are not expected for adapter interrupts KVM: s390: abstract conversion between isc and enum irq_types KVM: s390: vsie: use common code functions for pinning KVM: s390: SIE considerations for AP Queue virtualization KVM: s390: document memory ordering for kvm_s390_vcpu_wakeup KVM: PPC: Book3S HV: Cosmetic post-merge cleanups KVM: arm/arm64: fix the incompatible matching for external abort KVM: arm/arm64: Unify 32bit fault injection KVM: arm/arm64: vgic-its: Implement KVM_DEV_ARM_ITS_CTRL_RESET KVM: arm/arm64: Document KVM_DEV_ARM_ITS_CTRL_RESET KVM: arm/arm64: vgic-its: Free caches when GITS_BASER Valid bit is cleared KVM: arm/arm64: vgic-its: New helper functions to free the caches KVM: arm/arm64: vgic-its: Remove kvm_its_unmap_device arm/arm64: KVM: Load the timer state when enabling the timer KVM: arm/arm64: Rework kvm_timer_should_fire KVM: arm/arm64: Get rid of kvm_timer_flush_hwstate KVM: arm/arm64: Avoid phys timer emulation in vcpu entry/exit KVM: arm/arm64: Move phys_timer_emulate function KVM: arm/arm64: Use kvm_arm_timer_set/get_reg for guest register traps ...
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@@ -68,6 +68,8 @@ extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
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extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
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extern void __kvm_tlb_flush_local_vmid(struct kvm_vcpu *vcpu);
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extern void __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high);
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extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
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extern void __init_stage2_translation(void);
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@@ -25,7 +25,22 @@
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#include <asm/kvm_arm.h>
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#include <asm/cputype.h>
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/* arm64 compatibility macros */
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#define COMPAT_PSR_MODE_ABT ABT_MODE
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#define COMPAT_PSR_MODE_UND UND_MODE
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#define COMPAT_PSR_T_BIT PSR_T_BIT
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#define COMPAT_PSR_I_BIT PSR_I_BIT
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#define COMPAT_PSR_A_BIT PSR_A_BIT
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#define COMPAT_PSR_E_BIT PSR_E_BIT
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#define COMPAT_PSR_IT_MASK PSR_IT_MASK
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unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
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static inline unsigned long *vcpu_reg32(struct kvm_vcpu *vcpu, u8 reg_num)
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{
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return vcpu_reg(vcpu, reg_num);
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}
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unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu);
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static inline unsigned long vcpu_get_reg(struct kvm_vcpu *vcpu,
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@@ -42,10 +57,25 @@ static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
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bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
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void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
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void kvm_inject_undefined(struct kvm_vcpu *vcpu);
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void kvm_inject_undef32(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_vabt(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
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static inline void kvm_inject_undefined(struct kvm_vcpu *vcpu)
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{
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kvm_inject_undef32(vcpu);
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}
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static inline void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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kvm_inject_dabt32(vcpu, addr);
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}
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static inline void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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kvm_inject_pabt32(vcpu, addr);
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}
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static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
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{
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@@ -203,7 +233,7 @@ static inline u8 kvm_vcpu_trap_get_fault_type(struct kvm_vcpu *vcpu)
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static inline bool kvm_vcpu_dabt_isextabt(struct kvm_vcpu *vcpu)
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{
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switch (kvm_vcpu_trap_get_fault_type(vcpu)) {
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switch (kvm_vcpu_trap_get_fault(vcpu)) {
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case FSC_SEA:
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case FSC_SEA_TTW0:
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case FSC_SEA_TTW1:
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@@ -98,8 +98,8 @@
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#define cntvoff_el2 CNTVOFF
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#define cnthctl_el2 CNTHCTL
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void __timer_save_state(struct kvm_vcpu *vcpu);
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void __timer_restore_state(struct kvm_vcpu *vcpu);
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void __timer_enable_traps(struct kvm_vcpu *vcpu);
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void __timer_disable_traps(struct kvm_vcpu *vcpu);
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void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
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void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
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@@ -152,6 +152,12 @@ struct kvm_arch_memory_slot {
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(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
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#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
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/* PL1 Physical Timer Registers */
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#define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1)
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#define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14)
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#define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14)
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/* Virtual Timer Registers */
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#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
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#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
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@@ -216,6 +222,7 @@ struct kvm_arch_memory_slot {
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#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
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#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
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#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
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#define KVM_DEV_ARM_ITS_CTRL_RESET 4
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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