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Merge tag 'usb-4.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Browse Source 
Pull USB/PHY updates from Greg KH:
 "Here is the big USB/PHY driver patches for 4.20-rc1

  Lots of USB changes in here, primarily in these areas:

   - typec updates and new drivers

   - new PHY drivers

   - dwc2 driver updates and additions (this old core keeps getting
     added to new devices.)

   - usbtmc major update based on the industry group coming together and
     working to add new features and performance to the driver.

   - USB gadget additions for new features

   - USB gadget configfs updates

   - chipidea driver updates

   - other USB gadget updates

   - USB serial driver updates

   - renesas driver updates

   - xhci driver updates

   - other tiny USB driver updates

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'usb-4.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (229 commits)
  usb: phy: ab8500: silence some uninitialized variable warnings
  usb: xhci: tegra: Add genpd support
  usb: xhci: tegra: Power-off power-domains on removal
  usbip:vudc: BUG kmalloc-2048 (Not tainted): Poison overwritten
  usbip: tools: fix atoi() on non-null terminated string
  USB: misc: appledisplay: fix backlight update_status return code
  phy: phy-pxa-usb: add a new driver
  usb: host: add DT bindings for faraday fotg2
  usb: host: ohci-at91: fix request of irq for optional gpio
  usb/early: remove set but not used variable 'remain_length'
  usb: typec: Fix copy/paste on typec_set_vconn_role() kerneldoc
  usb: typec: tcpm: Report back negotiated PPS voltage and current
  USB: core: remove set but not used variable 'udev'
  usb: core: fix memory leak on port_dev_path allocation
  USB: net2280: Remove ->disconnect() callback from net2280_pullup()
  usb: dwc2: disable power_down on rockchip devices
  usb: gadget: udc: renesas_usb3: add support for r8a77990
  dt-bindings: usb: renesas_usb3: add bindings for r8a77990
  usb: gadget: udc: renesas_usb3: Add r8a774a1 support
  USB: serial: cypress_m8: remove set but not used variable 'iflag'
  ...
This commit is contained in:
Linus Torvalds
2018-10-26 08:14:13 -07:00
parent da19a102ce b8d9ee2449
commit 9703fc8caf
181 changed files with 8807 additions and 2209 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/connector/usb-connector.txt
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@@ -29,15 +29,15 @@ Required properties for usb-c-connector with power delivery support:
in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.2
Source_Capabilities Message, the order of each entry(PDO) should follow
the PD spec chapter 6.4.1. Required for power source and power dual role.
User can specify the source PDO array via PDO_FIXED/BATT/VAR() defined in
dt-bindings/usb/pd.h.
User can specify the source PDO array via PDO_FIXED/BATT/VAR/PPS_APDO()
defined in dt-bindings/usb/pd.h.
- sink-pdos: An array of u32 with each entry providing supported power
sink data object(PDO), the detailed bit definitions of PDO can be found
in "Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
Sink Capabilities Message, the order of each entry(PDO) should follow
the PD spec chapter 6.4.1. Required for power sink and power dual role.
User can specify the sink PDO array via PDO_FIXED/BATT/VAR() defined in
dt-bindings/usb/pd.h.
User can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
in dt-bindings/usb/pd.h.
- op-sink-microwatt: Sink required operating power in microwatt, if source
can't offer the power, Capability Mismatch is set. Required for power
sink and power dual role.

1
Documentation/devicetree/bindings/phy/brcm-sata-phy.txt
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@@ -8,6 +8,7 @@ Required properties:
"brcm,iproc-nsp-sata-phy"
"brcm,phy-sata3"
"brcm,iproc-sr-sata-phy"
"brcm,bcm63138-sata-phy"
- address-cells: should be 1
- size-cells: should be 0
- reg: register ranges for the PHY PCB interface

30
Documentation/devicetree/bindings/phy/phy-cadence-dp.txt Normal file
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@@ -0,0 +1,30 @@
Cadence MHDP DisplayPort SD0801 PHY binding
===========================================
This binding describes the Cadence SD0801 PHY hardware included with
the Cadence MHDP DisplayPort controller.
-------------------------------------------------------------------------------
Required properties (controller (parent) node):
- compatible : Should be "cdns,dp-phy"
- reg : Defines the following sets of registers in the parent
mhdp device:
- Offset of the DPTX PHY configuration registers
- Offset of the SD0801 PHY configuration registers
- #phy-cells : from the generic PHY bindings, must be 0.
Optional properties:
- num_lanes : Number of DisplayPort lanes to use (1, 2 or 4)
- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
2430, 2700, 3240, 4320, 5400 or 8100)
-------------------------------------------------------------------------------
Example:
dp_phy: phy@f0fb030a00 {
compatible = "cdns,dp-phy";
reg = <0xf0 0xfb030a00 0x0 0x00000040>,
<0xf0 0xfb500000 0x0 0x00100000>;
num_lanes = <4>;
max_bit_rate = <8100>;
#phy-cells = <0>;
};

43
Documentation/devicetree/bindings/phy/phy-rockchip-inno-hdmi.txt Normal file
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@@ -0,0 +1,43 @@
ROCKCHIP HDMI PHY WITH INNO IP BLOCK
Required properties:
- compatible : should be one of the listed compatibles:
* "rockchip,rk3228-hdmi-phy",
* "rockchip,rk3328-hdmi-phy";
- reg : Address and length of the hdmi phy control register set
- clocks : phandle + clock specifier for the phy clocks
- clock-names : string, clock name, must contain "sysclk" for system
control and register configuration, "refoclk" for crystal-
oscillator reference PLL clock input and "refpclk" for pclk-
based refeference PLL clock input.
- #clock-cells: should be 0.
- clock-output-names : shall be the name for the output clock.
- interrupts : phandle + interrupt specified for the hdmiphy interrupt
- #phy-cells : must be 0. See ./phy-bindings.txt for details.
Optional properties for rk3328-hdmi-phy:
- nvmem-cells = phandle + nvmem specifier for the cpu-version efuse
- nvmem-cell-names : "cpu-version" to read the chip version, required
for adjustment to some frequency settings
Example:
hdmi_phy: hdmi-phy@12030000 {
compatible = "rockchip,rk3228-hdmi-phy";
reg = <0x12030000 0x10000>;
#phy-cells = <0>;
clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
clock-names = "sysclk", "refoclk", "refpclk";
#clock-cells = <0>;
clock-output-names = "hdmi_phy";
status = "disabled";
};
Then the PHY can be used in other nodes such as:
hdmi: hdmi@200a0000 {
compatible = "rockchip,rk3228-dw-hdmi";
...
phys = <&hdmi_phy>;
phy-names = "hdmi";
...
};

23
Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
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@@ -10,16 +10,20 @@ Required properties:
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.
"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
"qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
- reg:
- For "qcom,sdm845-qmp-usb3-phy":
- index 0: address and length of register set for PHY's common serdes
block.
- named register "dp_com" (using reg-names): address and length of the
DP_COM control block.
- For all others:
- offset and length of register set for PHY's common serdes block.
- reg:
- index 0: address and length of register set for PHY's common
serdes block.
- index 1: address and length of the DP_COM control block (for
"qcom,sdm845-qmp-usb3-phy" only).
- reg-names:
- For "qcom,sdm845-qmp-usb3-phy":
- Should be: "reg-base", "dp_com"
- For all others:
- The reg-names property shouldn't be defined.
- #clock-cells: must be 1
- Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
@@ -35,6 +39,7 @@ Required properties:
"aux" for phy aux clock,
"ref" for 19.2 MHz ref clk,
"com_aux" for phy common block aux clock,
"ref_aux" for phy reference aux clock,
For "qcom,msm8996-qmp-pcie-phy" must contain:
"aux", "cfg_ahb", "ref".
For "qcom,msm8996-qmp-usb3-phy" must contain:

11
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
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@@ -1,10 +1,12 @@
* Renesas R-Car generation 3 USB 2.0 PHY
This file provides information on what the device node for the R-Car generation
3 USB 2.0 PHY contains.
3 and RZ/G2 USB 2.0 PHY contain.
Required properties:
- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
- compatible: "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1
SoC.
"renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
SoC.
"renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796
SoC.
@@ -14,7 +16,8 @@ Required properties:
R8A77990 SoC.
"renesas,usb2-phy-r8a77995" if the device is a part of an
R8A77995 SoC.
"renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 compatible device.
"renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3 or RZ/G2
compatible device.
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first
@@ -31,6 +34,8 @@ channel as USB OTG:
- interrupts: interrupt specifier for the PHY.
- vbus-supply: Phandle to a regulator that provides power to the VBUS. This
regulator will be managed during the PHY power on/off sequence.
- renesas,no-otg-pins: boolean, specify when a board does not provide proper
otg pins.
Example (R-Car H3):

10
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
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@@ -1,20 +1,22 @@
* Renesas R-Car generation 3 USB 3.0 PHY
This file provides information on what the device node for the R-Car generation
3 USB 3.0 PHY contains.
3 and RZ/G2 USB 3.0 PHY contain.
If you want to enable spread spectrum clock (ssc), you should use USB_EXTAL
instead of USB3_CLK. However, if you don't want to these features, you don't
need this driver.
Required properties:
- compatible: "renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795
- compatible: "renesas,r8a774a1-usb3-phy" if the device is a part of an R8A774A1
SoC.
"renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795
SoC.
"renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796
SoC.
"renesas,r8a77965-usb3-phy" if the device is a part of an
R8A77965 SoC.
"renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 compatible
device.
"renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 or RZ/G2
compatible device.
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first

31
Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt Normal file
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@@ -0,0 +1,31 @@
Socionext UniPhier PCIe PHY bindings
This describes the devicetree bindings for PHY interface built into
PCIe controller implemented on Socionext UniPhier SoCs.
Required properties:
- compatible: Should contain one of the following:
"socionext,uniphier-ld20-pcie-phy" - for LD20 PHY
"socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY
- reg: Specifies offset and length of the register set for the device.
- #phy-cells: Must be zero.
- clocks: A phandle to the clock gate for PCIe glue layer including
this phy.
- resets: A phandle to the reset line for PCIe glue layer including
this phy.
Optional properties:
- socionext,syscon: A phandle to system control to set configurations
for phy.
Refer to phy/phy-bindings.txt for the generic PHY binding properties.
Example:
pcie_phy: phy@66038000 {
compatible = "socionext,uniphier-ld20-pcie-phy";
reg = <0x66038000 0x4000>;
#phy-cells = <0>;
clocks = <&sys_clk 24>;
resets = <&sys_rst 24>;
socionext,syscon = <&soc_glue>;
};

45
Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt Normal file
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@@ -0,0 +1,45 @@
Socionext UniPhier USB2 PHY
This describes the devicetree bindings for PHY interface built into
USB2 controller implemented on Socionext UniPhier SoCs.
Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3
controller doesn't include its own High-Speed PHY. This needs to specify
USB2 PHY instead of USB3 HS-PHY.
Required properties:
- compatible: Should contain one of the following:
"socionext,uniphier-pro4-usb2-phy" - for Pro4 SoC
"socionext,uniphier-ld11-usb2-phy" - for LD11 SoC
Sub-nodes:
Each PHY should be represented as a sub-node.
Sub-nodes required properties:
- #phy-cells: Should be 0.
- reg: The number of the PHY.
Sub-nodes optional properties:
- vbus-supply: A phandle to the regulator for USB VBUS.
Refer to phy/phy-bindings.txt for the generic PHY binding properties.
Example:
soc-glue@5f800000 {
...
usb-phy {
compatible = "socionext,uniphier-ld11-usb2-phy";
usb_phy0: phy@0 {
reg = <0>;
#phy-cells = <0>;
};
...
};
};
usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
...
phy-names = "usb";
phys = <&usb_phy0>;
};

69
Documentation/devicetree/bindings/phy/uniphier-usb3-hsphy.txt Normal file
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@@ -0,0 +1,69 @@
Socionext UniPhier USB3 High-Speed (HS) PHY
This describes the devicetree bindings for PHY interfaces built into
USB3 controller implemented on Socionext UniPhier SoCs.
Although the controller includes High-Speed PHY and Super-Speed PHY,
this describes about High-Speed PHY.
Required properties:
- compatible: Should contain one of the following:
"socionext,uniphier-pro4-usb3-hsphy" - for Pro4 SoC
"socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC
"socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC
"socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC
- reg: Specifies offset and length of the register set for the device.
- #phy-cells: Should be 0.
- clocks: A list of phandles to the clock gate for USB3 glue layer.
According to the clock-names, appropriate clocks are required.
- clock-names: Should contain the following:
"gio", "link" - for Pro4 SoC
"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
"phy", "link" - for others
- resets: A list of phandles to the reset control for USB3 glue layer.
According to the reset-names, appropriate resets are required.
- reset-names: Should contain the following:
"gio", "link" - for Pro4 SoC
"phy", "link" - for others
Optional properties:
- vbus-supply: A phandle to the regulator for USB VBUS.
- nvmem-cells: Phandles to nvmem cell that contains the trimming data.
Available only for HS-PHY implemented on LD20 and PXs3, and
if unspecified, default value is used.
- nvmem-cell-names: Should be the following names, which correspond to
each nvmem-cells.
All of the 3 parameters associated with the following names are
required for each port, if any one is omitted, the trimming data
of the port will not be set at all.
"rterm", "sel_t", "hs_i" - Each cell name for phy parameters
Refer to phy/phy-bindings.txt for the generic PHY binding properties.
Example:
usb-glue@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
usb_vbus0: regulator {
...
};
usb_hsphy0: hs-phy@200 {
compatible = "socionext,uniphier-ld20-usb3-hsphy";
reg = <0x200 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
nvmem-cell-names = "rterm", "sel_t", "hs_i";
nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
<&usb_hs_i0>;
};
...
};

57
Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt Normal file
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@@ -0,0 +1,57 @@
Socionext UniPhier USB3 Super-Speed (SS) PHY
This describes the devicetree bindings for PHY interfaces built into
USB3 controller implemented on Socionext UniPhier SoCs.
Although the controller includes High-Speed PHY and Super-Speed PHY,
this describes about Super-Speed PHY.
Required properties:
- compatible: Should contain one of the following:
"socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC
"socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC
"socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC
"socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC
- reg: Specifies offset and length of the register set for the device.
- #phy-cells: Should be 0.
- clocks: A list of phandles to the clock gate for USB3 glue layer.
According to the clock-names, appropriate clocks are required.
- clock-names:
"gio", "link" - for Pro4 SoC
"phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
"phy", "link" - for others
- resets: A list of phandles to the reset control for USB3 glue layer.
According to the reset-names, appropriate resets are required.
- reset-names:
"gio", "link" - for Pro4 SoC
"phy", "link" - for others
Optional properties:
- vbus-supply: A phandle to the regulator for USB VBUS.
Refer to phy/phy-bindings.txt for the generic PHY binding properties.
Example:
usb-glue@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
usb_vbus0: regulator {
...
};
usb_ssphy0: ss-phy@300 {
compatible = "socionext,uniphier-ld20-usb3-ssphy";
reg = <0x300 0x10>;
#phy-cells = <0>;
clock-names = "link", "phy";
clocks = <&sys_clk 14>, <&sys_clk 16>;
reset-names = "link", "phy";
resets = <&sys_rst 14>, <&sys_rst 16>;
vbus-supply = <&usb_vbus0>;
};
...
};

2
Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
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@@ -80,6 +80,8 @@ Optional properties:
controller. It's expected that a mux state of 0 indicates device mode and a
mux state of 1 indicates host mode.
- mux-control-names: Shall be "usb_switch" if mux-controls is specified.
- pinctrl-names: Names for optional pin modes in "default", "host", "device"
- pinctrl-n: alternate pin modes
i.mx specific properties
- fsl,usbmisc: phandler of non-core register device, with one

1
Documentation/devicetree/bindings/usb/dwc3.txt
View File

@@ -19,6 +19,7 @@ Exception for clocks:
"cavium,octeon-7130-usb-uctl"
"qcom,dwc3"
"samsung,exynos5250-dwusb3"
"samsung,exynos5433-dwusb3"
"samsung,exynos7-dwusb3"
"sprd,sc9860-dwc3"
"st,stih407-dwc3"

23
Documentation/devicetree/bindings/usb/ehci-mv.txt Normal file
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@@ -0,0 +1,23 @@
* Marvell PXA/MMP EHCI controller.
Required properties:
- compatible: must be "marvell,pxau2o-ehci"
- reg: physical base addresses of the controller and length of memory mapped region
- interrupts: one EHCI controller interrupt should be described here
- clocks: phandle list of usb clocks
- clock-names: should be "USBCLK"
- phys: phandle for the PHY device
- phy-names: should be "usb"
Example:
ehci0: usb-ehci@d4208000 {
compatible = "marvell,pxau2o-ehci";
reg = <0xd4208000 0x200>;
interrupts = <44>;
clocks = <&soc_clocks MMP2_CLK_USB>;
clock-names = "USBCLK";
phys = <&usb_otg_phy>;
phy-names = "usb";
};

2
Documentation/devicetree/bindings/usb/exynos-usb.txt
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@@ -83,6 +83,8 @@ Required properties:
- compatible: should be one of the following -
"samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on
Exynos5250/5420.
"samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on
Exynos5433.
"samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7.
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
with 'reg' property.

35
Documentation/devicetree/bindings/usb/faraday,fotg210.txt Normal file
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@@ -0,0 +1,35 @@
Faraday FOTG Host controller
This OTG-capable USB host controller is found in Cortina Systems
Gemini and other SoC products.
Required properties:
- compatible: should be one of:
"faraday,fotg210"
"cortina,gemini-usb", "faraday,fotg210"
- reg: should contain one register range i.e. start and length
- interrupts: description of the interrupt line
Optional properties:
- clocks: should contain the IP block clock
- clock-names: should be "PCLK" for the IP block clock
Required properties for "cortina,gemini-usb" compatible:
- syscon: a phandle to the system controller to access PHY registers
Optional properties for "cortina,gemini-usb" compatible:
- cortina,gemini-mini-b: boolean property that indicates that a Mini-B
OTG connector is in use
- wakeup-source: see power/wakeup-source.txt
Example for Gemini:
usb@68000000 {
compatible = "cortina,gemini-usb", "faraday,fotg210";
reg = <0x68000000 0x1000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cc 12>;
clock-names = "PCLK";
syscon = <&syscon>;
wakeup-source;
};

32
Documentation/devicetree/bindings/usb/fcs,fusb302.txt
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@@ -5,10 +5,19 @@ Required properties :
- reg : I2C slave address
- interrupts : Interrupt specifier
Optional properties :
- fcs,operating-sink-microwatt :
Minimum amount of power accepted from a sink
when negotiating
Required sub-node:
- connector : The "usb-c-connector" attached to the FUSB302 IC. The bindings
of the connector node are specified in:
Documentation/devicetree/bindings/connector/usb-connector.txt
Deprecated properties :
- fcs,max-sink-microvolt : Maximum sink voltage accepted by port controller
- fcs,max-sink-microamp : Maximum sink current accepted by port controller
- fcs,max-sink-microwatt : Maximum sink power accepted by port controller
- fcs,operating-sink-microwatt : Minimum amount of power accepted from a sink
when negotiating
Example:
@@ -17,7 +26,16 @@ fusb302: typec-portc@54 {
reg = <0x54>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
fcs,max-sink-microvolt = <12000000>;
fcs,max-sink-microamp = <3000000>;
fcs,max-sink-microwatt = <36000000>;
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(3000, 12000, 3000)
PDO_PPS_APDO(3000, 11000, 3000)>;
op-sink-microwatt = <10000000>;
};
};

6
Documentation/devicetree/bindings/usb/renesas_usb3.txt
View File

@@ -2,11 +2,13 @@ Renesas Electronics USB3.0 Peripheral driver
Required properties:
- compatible: Must contain one of the following:
- "renesas,r8a774a1-usb3-peri"
- "renesas,r8a7795-usb3-peri"
- "renesas,r8a7796-usb3-peri"
- "renesas,r8a77965-usb3-peri"
- "renesas,rcar-gen3-usb3-peri" for a generic R-Car Gen3 compatible
device
- "renesas,r8a77990-usb3-peri"
- "renesas,rcar-gen3-usb3-peri" for a generic R-Car Gen3 or RZ/G2
compatible device
When compatible with the generic version, nodes must list the
SoC-specific version corresponding to the platform first

11
Documentation/devicetree/bindings/usb/renesas_usbhs.txt
View File

@@ -4,7 +4,9 @@ Required properties:
- compatible: Must contain one or more of the following:
- "renesas,usbhs-r8a7743" for r8a7743 (RZ/G1M) compatible device
- "renesas,usbhs-r8a7744" for r8a7744 (RZ/G1N) compatible device
- "renesas,usbhs-r8a7745" for r8a7745 (RZ/G1E) compatible device
- "renesas,usbhs-r8a774a1" for r8a774a1 (RZ/G2M) compatible device
- "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device
- "renesas,usbhs-r8a7791" for r8a7791 (R-Car M2-W) compatible device
- "renesas,usbhs-r8a7792" for r8a7792 (R-Car V2H) compatible device
@@ -13,10 +15,11 @@ Required properties:
- "renesas,usbhs-r8a7795" for r8a7795 (R-Car H3) compatible device
- "renesas,usbhs-r8a7796" for r8a7796 (R-Car M3-W) compatible device
- "renesas,usbhs-r8a77965" for r8a77965 (R-Car M3-N) compatible device
- "renesas,usbhs-r8a77990" for r8a77990 (R-Car E3) compatible device
- "renesas,usbhs-r8a77995" for r8a77995 (R-Car D3) compatible device
- "renesas,usbhs-r7s72100" for r7s72100 (RZ/A1) compatible device
- "renesas,rcar-gen2-usbhs" for R-Car Gen2 or RZ/G1 compatible devices
- "renesas,rcar-gen3-usbhs" for R-Car Gen3 compatible device
- "renesas,rcar-gen3-usbhs" for R-Car Gen3 or RZ/G2 compatible devices
- "renesas,rza1-usbhs" for RZ/A1 compatible device
When compatible with the generic version, nodes must list the
@@ -25,7 +28,11 @@ Required properties:
- reg: Base address and length of the register for the USBHS
- interrupts: Interrupt specifier for the USBHS
- clocks: A list of phandle + clock specifier pairs
- clocks: A list of phandle + clock specifier pairs.
- In case of "renesas,rcar-gen3-usbhs", two clocks are required.
First clock should be peripheral and second one should be host.
- In case of except above, one clock is required. First clock
should be peripheral.
Optional properties:
- renesas,buswait: Integer to use BUSWAIT register

6
Documentation/devicetree/bindings/usb/usb-ehci.txt
View File

@@ -15,7 +15,11 @@ Optional properties:
- needs-reset-on-resume : boolean, set this to force EHCI reset after resume
- has-transaction-translator : boolean, set this if EHCI have a Transaction
Translator built into the root hub.
- clocks : a list of phandle + clock specifier pairs
- clocks : a list of phandle + clock specifier pairs. In case of Renesas
R-Car Gen3 SoCs:
- if a host only channel: first clock should be host.
- if a USB DRD channel: first clock should be host and second one
should be peripheral.
- phys : see usb-hcd.txt in the current directory
- resets : phandle + reset specifier pair

6
Documentation/devicetree/bindings/usb/usb-ohci.txt
View File

@@ -12,7 +12,11 @@ Optional properties:
- no-big-frame-no : boolean, set if frame_no lives in bits [15:0] of HCCA
- remote-wakeup-connected: remote wakeup is wired on the platform
- num-ports : u32, to override the detected port count
- clocks : a list of phandle + clock specifier pairs
- clocks : a list of phandle + clock specifier pairs. In case of Renesas
R-Car Gen3 SoCs:
- if a host only channel: first clock should be host.
- if a USB DRD channel: first clock should be host and second one
should be peripheral.
- phys : see usb-hcd.txt in the current directory
- resets : a list of phandle + reset specifier pairs

5
Documentation/devicetree/bindings/usb/usb-xhci.txt
View File

@@ -8,6 +8,8 @@ Required properties:
- "marvell,armada-375-xhci" for Armada 375 SoCs
- "marvell,armada-380-xhci" for Armada 38x SoCs
- "renesas,xhci-r8a7743" for r8a7743 SoC
- "renesas,xhci-r8a7744" for r8a7744 SoC
- "renesas,xhci-r8a774a1" for r8a774a1 SoC
- "renesas,xhci-r8a7790" for r8a7790 SoC
- "renesas,xhci-r8a7791" for r8a7791 SoC
- "renesas,xhci-r8a7793" for r8a7793 SoC
@@ -17,7 +19,8 @@ Required properties:
- "renesas,xhci-r8a77990" for r8a77990 SoC
- "renesas,rcar-gen2-xhci" for a generic R-Car Gen2 or RZ/G1 compatible
device
- "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 compatible device
- "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 or RZ/G2 compatible
device
- "xhci-platform" (deprecated)
When compatible with the generic version, nodes must list the