Merge tag 'media/v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab: - remove sensor drivers that got converted from soc_camera - remaining soc_camera drivers got moved to staging - some documentation cleanups and improvements - the imx staging driver now supports imx7 - the ov9640, mt9m001 and mt9m111 got converted from soc_camera - the vim2m driver now does what a m2m convert driver expects to do - epoll() fixes on media subsystems - several drivers fixes, typos, cleanups and improvements * tag 'media/v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (346 commits) media: dvb/earth-pt1: fix wrong initialization for demod blocks media: vim2m: Address some coding style issues media: vim2m: don't use BUG() media: vim2m: speedup passthrough copy media: vim2m: add an horizontal scaler media: vim2m: don't accept YUYV anymore as output format media: vim2m: add vertical linear scaler media: vim2m: better handle cap/out buffers with different sizes media: vim2m: use different framesizes for bayer formats media: vim2m: add support for VIDIOC_ENUM_FRAMESIZES media: vim2m: ensure that width is multiple of two media: vim2m: improve debug messages media: vim2m: add bayer capture formats media: a few more typos at staging, pci, platform, radio and usb media: Documentation: fix several typos media: staging: fix several typos media: include: fix several typos media: common: fix several typos media: v4l2-core: fix several typos media: usb: fix several typos ...
This commit is contained in:
@@ -48,7 +48,16 @@ are numbered as follows.
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TXA source 10
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TXB source 11
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The digital output port nodes must contain at least one endpoint.
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The digital output port nodes, when present, shall contain at least one
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endpoint. Each of those endpoints shall contain the data-lanes property as
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described in video-interfaces.txt.
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Required source endpoint properties:
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- data-lanes: an array of physical data lane indexes
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The accepted value(s) for this property depends on which of the two
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sources are described. For TXA 1, 2 or 4 data lanes can be described
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while for TXB only 1 data lane is valid. See video-interfaces.txt
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for detailed description.
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Ports are optional if they are not connected to anything at the hardware level.
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@@ -0,0 +1,20 @@
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* Melexis MLX90640 FIR Sensor
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Melexis MLX90640 FIR sensor support which allows recording of thermal data
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with 32x24 resolution excluding 2 lines of coefficient data that is used by
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userspace to render processed frames.
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Required Properties:
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- compatible : Must be "melexis,mlx90640"
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- reg : i2c address of the device
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Example:
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i2c0@1c22000 {
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...
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mlx90640@33 {
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compatible = "melexis,mlx90640";
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reg = <0x33>;
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};
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...
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};
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38
Documentation/devicetree/bindings/media/i2c/mt9m001.txt
Normal file
38
Documentation/devicetree/bindings/media/i2c/mt9m001.txt
Normal file
@@ -0,0 +1,38 @@
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MT9M001: 1/2-Inch Megapixel Digital Image Sensor
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The MT9M001 is an SXGA-format with a 1/2-inch CMOS active-pixel digital
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image sensor. It is programmable through I2C interface.
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Required Properties:
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- compatible: shall be "onnn,mt9m001".
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- clocks: reference to the master clock into sensor
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Optional Properties:
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- reset-gpios: GPIO handle which is connected to the reset pin of the chip.
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Active low.
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- standby-gpios: GPIO handle which is connected to the standby pin of the chip.
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Active high.
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The device node must contain one 'port' child node with one 'endpoint' child
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sub-node for its digital output video port, in accordance with the video
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interface bindings defined in:
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Documentation/devicetree/bindings/media/video-interfaces.txt
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Example:
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&i2c1 {
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camera-sensor@5d {
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compatible = "onnn,mt9m001";
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reg = <0x5d>;
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reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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standby-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
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clocks = <&camera_clk>;
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port {
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mt9m001_out: endpoint {
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remote-endpoint = <&vcap_in>;
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};
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};
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};
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};
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@@ -26,9 +26,9 @@ Example:
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&i2c1 {
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...
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ov5645: ov5645@78 {
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ov5645: ov5645@3c {
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compatible = "ovti,ov5645";
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reg = <0x78>;
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reg = <0x3c>;
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enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
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@@ -37,7 +37,7 @@ Example:
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clocks = <&clks 200>;
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clock-names = "xclk";
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clock-frequency = <23880000>;
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clock-frequency = <24000000>;
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vdddo-supply = <&camera_dovdd_1v8>;
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vdda-supply = <&camera_avdd_2v8>;
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45
Documentation/devicetree/bindings/media/imx7-csi.txt
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45
Documentation/devicetree/bindings/media/imx7-csi.txt
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@@ -0,0 +1,45 @@
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Freescale i.MX7 CMOS Sensor Interface
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=====================================
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csi node
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--------
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This is device node for the CMOS Sensor Interface (CSI) which enables the chip
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to connect directly to external CMOS image sensors.
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Required properties:
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- compatible : "fsl,imx7-csi";
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- reg : base address and length of the register set for the device;
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- interrupts : should contain CSI interrupt;
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- clocks : list of clock specifiers, see
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Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
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- clock-names : must contain "axi", "mclk" and "dcic" entries, matching
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entries in the clock property;
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The device node shall contain one 'port' child node with one child 'endpoint'
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node, according to the bindings defined in:
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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In the following example a remote endpoint is a video multiplexer.
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example:
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csi: csi@30710000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7-csi";
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reg = <0x30710000 0x10000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_CLK_DUMMY>,
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<&clks IMX7D_CSI_MCLK_ROOT_CLK>,
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<&clks IMX7D_CLK_DUMMY>;
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clock-names = "axi", "mclk", "dcic";
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port {
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csi_from_csi_mux: endpoint {
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remote-endpoint = <&csi_mux_to_csi>;
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};
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};
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};
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90
Documentation/devicetree/bindings/media/imx7-mipi-csi2.txt
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90
Documentation/devicetree/bindings/media/imx7-mipi-csi2.txt
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@@ -0,0 +1,90 @@
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Freescale i.MX7 Mipi CSI2
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=========================
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mipi_csi2 node
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--------------
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This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
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compatible with previous version of Samsung D-phy.
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Required properties:
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- compatible : "fsl,imx7-mipi-csi2";
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- reg : base address and length of the register set for the device;
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- interrupts : should contain MIPI CSIS interrupt;
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- clocks : list of clock specifiers, see
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Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
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- clock-names : must contain "pclk", "wrap" and "phy" entries, matching
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entries in the clock property;
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- power-domains : a phandle to the power domain, see
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Documentation/devicetree/bindings/power/power_domain.txt for details.
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- reset-names : should include following entry "mrst";
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- resets : a list of phandle, should contain reset entry of
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reset-names;
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- phy-supply : from the generic phy bindings, a phandle to a regulator that
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provides power to MIPI CSIS core;
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Optional properties:
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- clock-frequency : The IP's main (system bus) clock frequency in Hz, default
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value when this property is not specified is 166 MHz;
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- fsl,csis-hs-settle : differential receiver (HS-RX) settle time;
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The device node should contain two 'port' child nodes with one child 'endpoint'
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node, according to the bindings defined in:
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Documentation/devicetree/bindings/ media/video-interfaces.txt.
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The following are properties specific to those nodes.
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port node
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---------
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- reg : (required) can take the values 0 or 1, where 0 shall be
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related to the sink port and port 1 shall be the source
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one;
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endpoint node
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-------------
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- data-lanes : (required) an array specifying active physical MIPI-CSI2
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data input lanes and their mapping to logical lanes; this
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shall only be applied to port 0 (sink port), the array's
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content is unused only its length is meaningful,
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in this case the maximum length supported is 2;
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example:
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mipi_csi: mipi-csi@30750000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7-mipi-csi2";
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reg = <0x30750000 0x10000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_IPG_ROOT_CLK>,
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<&clks IMX7D_MIPI_CSI_ROOT_CLK>,
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<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
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clock-names = "pclk", "wrap", "phy";
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clock-frequency = <166000000>;
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power-domains = <&pgc_mipi_phy>;
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phy-supply = <®_1p0d>;
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resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
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reset-names = "mrst";
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fsl,csis-hs-settle = <3>;
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port@0 {
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reg = <0>;
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mipi_from_sensor: endpoint {
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remote-endpoint = <&ov2680_to_mipi>;
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data-lanes = <1>;
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};
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};
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port@1 {
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reg = <1>;
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mipi_vc0_to_csi_mux: endpoint {
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remote-endpoint = <&csi_mux_from_mipi_vc0>;
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};
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};
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};
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@@ -66,6 +66,15 @@ vcodec_dec: vcodec@16000000 {
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"vencpll",
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"venc_lt_sel",
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"vdec_bus_clk_src";
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assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
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<&topckgen CLK_TOP_CCI400_SEL>,
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<&topckgen CLK_TOP_VDEC_SEL>,
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<&apmixedsys CLK_APMIXED_VCODECPLL>,
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<&apmixedsys CLK_APMIXED_VENCPLL>;
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assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
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<&topckgen CLK_TOP_UNIVPLL_D2>,
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<&topckgen CLK_TOP_VCODECPLL>;
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assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
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};
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vcodec_enc: vcodec@18002000 {
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@@ -105,4 +114,8 @@ vcodec_dec: vcodec@16000000 {
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"venc_sel",
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"venc_lt_sel_src",
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"venc_lt_sel";
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assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
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<&topckgen CLK_TOP_UNIVPLL1_D2>;
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};
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@@ -7,12 +7,13 @@ family of devices.
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Each VIN instance has a single parallel input that supports RGB and YUV video,
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with both external synchronization and BT.656 synchronization for the latter.
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Depending on the instance the VIN input is connected to external SoC pins, or
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on Gen3 platforms to a CSI-2 receiver.
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on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
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- compatible: Must be one or more of the following
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- "renesas,vin-r8a7743" for the R8A7743 device
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- "renesas,vin-r8a7744" for the R8A7744 device
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- "renesas,vin-r8a7745" for the R8A7745 device
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- "renesas,vin-r8a774c0" for the R8A774C0 device
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- "renesas,vin-r8a7778" for the R8A7778 device
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- "renesas,vin-r8a7779" for the R8A7779 device
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- "renesas,vin-r8a7790" for the R8A7790 device
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@@ -61,10 +62,10 @@ The per-board settings Gen2 platforms:
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- data-enable-active: polarity of CLKENB signal, see [1] for
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description. Default is active high.
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The per-board settings Gen3 platforms:
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The per-board settings Gen3 and RZ/G2 platforms:
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Gen3 platforms can support both a single connected parallel input source
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from external SoC pins (port@0) and/or multiple parallel input sources
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Gen3 and RZ/G2 platforms can support both a single connected parallel input
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source from external SoC pins (port@0) and/or multiple parallel input sources
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from local SoC CSI-2 receivers (port@1) depending on SoC.
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- renesas,id - ID number of the VIN, VINx in the documentation.
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@@ -2,8 +2,9 @@ Renesas R-Car Frame Compression Processor (FCP)
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-----------------------------------------------
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The FCP is a companion module of video processing modules in the Renesas R-Car
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Gen3 SoCs. It provides data compression and decompression, data caching, and
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conversion of AXI transactions in order to reduce the memory bandwidth.
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Gen3 and RZ/G2 SoCs. It provides data compression and decompression, data
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caching, and conversion of AXI transactions in order to reduce the memory
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bandwidth.
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There are three types of FCP: FCP for Codec (FCPC), FCP for VSP (FCPV) and FCP
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for FDP (FCPF). Their configuration and behaviour depend on the module they
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@@ -2,12 +2,13 @@ Renesas R-Car MIPI CSI-2
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------------------------
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The R-Car CSI-2 receiver device provides MIPI CSI-2 capabilities for the
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Renesas R-Car family of devices. It is used in conjunction with the
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Renesas R-Car and RZ/G2 family of devices. It is used in conjunction with the
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R-Car VIN module, which provides the video capture capabilities.
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Mandatory properties
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--------------------
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- compatible: Must be one or more of the following
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- "renesas,r8a774c0-csi2" for the R8A774C0 device.
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- "renesas,r8a7795-csi2" for the R8A7795 device.
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- "renesas,r8a7796-csi2" for the R8A7796 device.
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- "renesas,r8a77965-csi2" for the R8A77965 device.
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|
@@ -2,13 +2,13 @@
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The VSP is a video processing engine that supports up-/down-scaling, alpha
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blending, color space conversion and various other image processing features.
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It can be found in the Renesas R-Car second generation SoCs.
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It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
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Required properties:
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- compatible: Must contain one of the following values
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- "renesas,vsp1" for the R-Car Gen2 VSP1
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- "renesas,vsp2" for the R-Car Gen3 VSP2
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- "renesas,vsp1" for the R-Car Gen2 and RZ/G1 VSP1
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- "renesas,vsp2" for the R-Car Gen3 and RZ/G2 VSP2
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- reg: Base address and length of the registers block for the VSP.
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- interrupts: VSP interrupt specifier.
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|
26
Documentation/devicetree/bindings/media/si470x.txt
Normal file
26
Documentation/devicetree/bindings/media/si470x.txt
Normal file
@@ -0,0 +1,26 @@
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* Silicon Labs FM Radio receiver
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The Silicon Labs Si470x is family of FM radio receivers with receive power scan
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supporting 76-108 MHz, programmable through an I2C interface.
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Some of them includes an RDS encoder.
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Required Properties:
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- compatible: Should contain "silabs,si470x"
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- reg: the I2C address of the device
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Optional Properties:
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- interrupts : The interrupt number
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- reset-gpios: GPIO specifier for the chips reset line
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|
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Example:
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&i2c2 {
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si470x@63 {
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compatible = "silabs,si470x";
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reg = <0x63>;
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interrupt-parent = <&gpj2>;
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interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
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reset-gpios = <&gpj2 5 GPIO_ACTIVE_HIGH>;
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};
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};
|
@@ -6,8 +6,9 @@ Allwinner V3s SoC features a CSI module(CSI1) with parallel interface.
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Required properties:
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- compatible: value must be one of:
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* "allwinner,sun6i-a31-csi"
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* "allwinner,sun8i-h3-csi", "allwinner,sun6i-a31-csi"
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* "allwinner,sun8i-h3-csi"
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* "allwinner,sun8i-v3s-csi"
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* "allwinner,sun50i-a64-csi"
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
|
||||
- clocks: phandles to the clocks feeding the CSI
|
||||
|
Reference in New Issue
Block a user