Merge branch 'pci/resource' into next
* pci/resource: PCI: Allocate 64-bit BARs above 4G when possible PCI: Enforce bus address limits in resource allocation PCI: Split out bridge window override of minimum allocation address agp/ati: Use PCI_COMMAND instead of hard-coded 4 agp/intel: Use CPU physical address, not bus address, for ioremap() agp/intel: Use pci_bus_address() to get GTTADR bus address agp/intel: Use pci_bus_address() to get MMADR bus address agp/intel: Support 64-bit GMADR agp/intel: Rename gtt_bus_addr to gtt_phys_addr drm/i915: Rename gtt_bus_addr to gtt_phys_addr agp: Use pci_resource_start() to get CPU physical address for BAR agp: Support 64-bit APBASE PCI: Add pci_bus_address() to get bus address of a BAR PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev PCI: Change pci_bus_region addresses to dma_addr_t
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@@ -83,7 +83,7 @@ static int pci_mmap_resource(struct kobject *kobj,
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if (iomem_is_exclusive(res->start))
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return -EINVAL;
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pcibios_resource_to_bus(pdev, &bar, res);
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pcibios_resource_to_bus(pdev->bus, &bar, res);
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vma->vm_pgoff += bar.start >> (PAGE_SHIFT - (sparse ? 5 : 0));
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mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
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@@ -139,7 +139,7 @@ static int sparse_mem_mmap_fits(struct pci_dev *pdev, int num)
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long dense_offset;
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unsigned long sparse_size;
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pcibios_resource_to_bus(pdev, &bar, &pdev->resource[num]);
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pcibios_resource_to_bus(pdev->bus, &bar, &pdev->resource[num]);
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/* All core logic chips have 4G sparse address space, except
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CIA which has 16G (see xxx_SPARSE_MEM and xxx_DENSE_MEM
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