Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for ARM SoCs. Some for SoC-family code under
drivers/soc, but also some other driver updates that don't belong
anywhere else. We also bring in the drivers/reset code through
arm-soc.
Some of the larger updates:
- Qualcomm support for SMEM, SMSM, SMP2P. All used to communicate
with other parts of the chip/board on these platforms, all
proprietary protocols that don't fit into other subsystems and live
in drivers/soc for now.
- System bus driver for UniPhier
- Driver for the TI Wakeup M3 IPC device
- Power management for Raspberry PI
+ Again a bunch of other smaller updates and patches"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
bus: uniphier: allow only built-in driver
ARM: bcm2835: clarify RASPBERRYPI_FIRMWARE dependency
MAINTAINERS: Drop Kumar Gala from QCOM
bus: uniphier-system-bus: add UniPhier System Bus driver
ARM: bcm2835: add rpi power domain driver
dt-bindings: add rpi power domain driver bindings
ARM: bcm2835: Define two new packets from the latest firmware.
drivers/soc: make mediatek/mtk-scpsys.c explicitly non-modular
soc: mediatek: SCPSYS: Add regulator support
MAINTAINERS: Change QCOM entries
soc: qcom: smd-rpm: Add existing platform support
memory/tegra: Add number of TLB lines for Tegra124
reset: hi6220: fix modular build
soc: qcom: Introduce WCNSS_CTRL SMD client
ARM: qcom: select ARM_CPU_SUSPEND for power management
MAINTAINERS: Add rules for Qualcomm dts files
soc: qcom: enable smsm/smp2p modular build
serial: msm_serial: Make config tristate
soc: qcom: smp2p: Qualcomm Shared Memory Point to Point
soc: qcom: smsm: Add driver for Qualcomm SMSM
...
This commit is contained in:
Linus Torvalds
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UniPhier System Bus
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The UniPhier System Bus is an external bus that connects on-board devices to
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the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
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some control signals. It supports up to 8 banks (chip selects).
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Before any access to the bus, the bus controller must be configured; the bus
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controller registers provide the control for the translation from the offset
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within each bank to the CPU-viewed address. The needed setup includes the base
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address, the size of each bank. Optionally, some timing parameters can be
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optimized for faster bus access.
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Required properties:
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- compatible: should be "socionext,uniphier-system-bus".
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- reg: offset and length of the register set for the bus controller device.
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- #address-cells: should be 2. The first cell is the bank number (chip select).
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The second cell is the address offset within the bank.
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- #size-cells: should be 1.
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- ranges: should provide a proper address translation from the System Bus to
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the parent bus.
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Note:
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The address region(s) that can be assigned for the System Bus is implementation
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defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff,
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while other SoCs can only use 0x40000000-0x4fffffff. There might be additional
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limitations depending on SoCs and the boot mode. The address translation is
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arbitrary as long as the banks are assigned in the supported address space with
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the required alignment and they do not overlap one another.
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For example, it is possible to map:
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bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
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It is also possible to map:
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bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
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There is no reason to stick to a particular translation mapping, but the
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"ranges" property should provide a "reasonable" default that is known to work.
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The software should initialize the bus controller according to it.
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Example:
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system-bus {
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compatible = "socionext,uniphier-system-bus";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <1 0x00000000 0x42000000 0x02000000
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5 0x00000000 0x46000000 0x01000000>;
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ethernet@1,01f00000 {
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compatible = "smsc,lan9115";
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reg = <1 0x01f00000 0x1000>;
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interrupts = <0 48 4>
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phy-mode = "mii";
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};
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uart@5,00200000 {
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compatible = "ns16550a";
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reg = <5 0x00200000 0x20>;
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interrupts = <0 49 4>
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clock-frequency = <12288000>;
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};
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};
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In this example,
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- the Ethernet device is connected at the offset 0x01f00000 of CS1 and
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mapped to 0x43f00000 of the parent bus.
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- the UART device is connected at the offset 0x00200000 of CS5 and
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mapped to 0x46200000 of the parent bus.
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@@ -0,0 +1,34 @@
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Hisilicon System Reset Controller
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======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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The reset controller registers are part of the system-ctl block on
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hi6220 SoC.
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Required properties:
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- compatible: may be "hisilicon,hi6220-sysctrl"
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- reg: should be register base and length as documented in the
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datasheet
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- #reset-cells: 1, see below
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Example:
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sys_ctrl: sys_ctrl@f7030000 {
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compatible = "hisilicon,hi6220-sysctrl", "syscon";
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reg = <0x0 0xf7030000 0x0 0x2000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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example:
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uart1: serial@..... {
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...
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resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
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...
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};
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The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>.
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@@ -0,0 +1,47 @@
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Raspberry Pi power domain driver
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Required properties:
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- compatible: Should be "raspberrypi,bcm2835-power".
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- firmware: Reference to the RPi firmware device node.
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- #power-domain-cells: Should be <1>, we providing multiple power domains.
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The valid defines for power domain are:
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RPI_POWER_DOMAIN_I2C0
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RPI_POWER_DOMAIN_I2C1
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RPI_POWER_DOMAIN_I2C2
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RPI_POWER_DOMAIN_VIDEO_SCALER
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RPI_POWER_DOMAIN_VPU1
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RPI_POWER_DOMAIN_HDMI
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RPI_POWER_DOMAIN_USB
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RPI_POWER_DOMAIN_VEC
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RPI_POWER_DOMAIN_JPEG
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RPI_POWER_DOMAIN_H264
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RPI_POWER_DOMAIN_V3D
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RPI_POWER_DOMAIN_ISP
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RPI_POWER_DOMAIN_UNICAM0
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RPI_POWER_DOMAIN_UNICAM1
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RPI_POWER_DOMAIN_CCP2RX
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RPI_POWER_DOMAIN_CSI2
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RPI_POWER_DOMAIN_CPI
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RPI_POWER_DOMAIN_DSI0
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RPI_POWER_DOMAIN_DSI1
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RPI_POWER_DOMAIN_TRANSPOSER
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RPI_POWER_DOMAIN_CCP2TX
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RPI_POWER_DOMAIN_CDP
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RPI_POWER_DOMAIN_ARM
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Example:
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power: power {
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compatible = "raspberrypi,bcm2835-power";
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firmware = <&firmware>;
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#power-domain-cells = <1>;
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};
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Example for using power domain:
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&usb {
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power-domains = <&power RPI_POWER_DOMAIN_USB>;
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};
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57
Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt
Normal file
57
Documentation/devicetree/bindings/soc/ti/wkup_m3_ipc.txt
Normal file
@@ -0,0 +1,57 @@
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Wakeup M3 IPC Driver
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=====================
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The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
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(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
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that cannot be controlled from the MPU, like suspend/resume and certain deep
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C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
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to boot the wkup_m3, it handles communication with the CM3 using IPC registers
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present in the SoC's control module and a mailbox. The wkup_m3_ipc exposes an
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API to allow the SoC PM code to execute specific PM tasks.
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Wkup M3 Device Node:
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====================
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A wkup_m3_ipc device node is used to represent the IPC registers within an
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SoC.
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Required properties:
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--------------------
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- compatible: Should be,
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"ti,am3352-wkup-m3-ipc" for AM33xx SoCs
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"ti,am4372-wkup-m3-ipc" for AM43xx SoCs
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- reg: Contains the IPC register address space to communicate
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with the Wakeup M3 processor
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- interrupts: Contains the interrupt information for the wkup_m3
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interrupt that signals the MPU.
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- ti,rproc: phandle to the wkup_m3 rproc node so the IPC driver
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can boot it.
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- mboxes: phandles used by IPC framework to get correct mbox
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channel for communication. Must point to appropriate
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mbox_wkupm3 child node.
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Example:
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--------
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/* AM33xx */
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l4_wkup: l4_wkup@44c00000 {
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...
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scm: scm@210000 {
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compatible = "ti,am3-scm", "simple-bus";
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reg = <0x210000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x210000 0x2000>;
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...
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wkup_m3_ipc: wkup_m3_ipc@1324 {
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compatible = "ti,am3352-wkup-m3-ipc";
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reg = <0x1324 0x24>;
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interrupts = <78>;
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ti,rproc = <&wkup_m3>;
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mboxes = <&mailbox &mbox_wkupm3>;
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};
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...
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};
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};
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