xiaomi-sm8450/android_kernel_xiaomi_sm8450
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Kods Problēmas Izmaiņu pieprasījumi Darbības Pakotnes Projekti Laidieni Vikivietne Aktivitāte

Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux into drm-next

Pārlūkot izejas kodu 
Main changes for 4.18.  I'd like to do a separate pull for vega20 later
this week or next.  Highlights:
- Reserve pre-OS scanout buffer during init for seemless transition from
  console to driver
- VEGAM support
- Improved GPU scheduler documentation
- Initial gfxoff support for raven
- SR-IOV fixes
- Default to non-AGP on PowerPC for radeon
- Fine grained clock voltage control for vega10
- Power profiles for vega10
- Further clean up of powerplay/driver interface
- Underlay fixes
- Display link bw updates
- Gamma fixes
- Scatter/Gather display support on CZ/ST
- Misc bug fixes and clean ups

[airlied: fixup v3d vs scheduler API change]

Link: https://patchwork.freedesktop.org/patch/msgid/20180515185450.1113-1-alexander.deucher@amd.com
Signed-off-by: Dave Airlie <airlied@redhat.com>
Šī revīzija ir iekļauta:
Dave Airlie
2018-05-16 08:21:51 +10:00
vecāks b8a71080ad 8344c53f57
revīzija 95d2c3e15d
259 mainīti faili ar 14421 papildinājumiem un 4591 dzēšanām
Lejupielādēt ielāpa failu Lejupielādēt izmaiņu failu Izvērst visus failus Savērst visus failus

158
drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
Parādīt failu

@@ -26,13 +26,13 @@
#include "dm_services.h"
#include "include/fixed31_32.h"
static inline uint64_t abs_i64(
int64_t arg)
static inline unsigned long long abs_i64(
long long arg)
{
if (arg > 0)
return (uint64_t)arg;
return (unsigned long long)arg;
else
return (uint64_t)(-arg);
return (unsigned long long)(-arg);
}
/*
@@ -40,12 +40,12 @@ static inline uint64_t abs_i64(
* result = dividend / divisor
* *remainder = dividend % divisor
*/
static inline uint64_t complete_integer_division_u64(
uint64_t dividend,
uint64_t divisor,
uint64_t *remainder)
static inline unsigned long long complete_integer_division_u64(
unsigned long long dividend,
unsigned long long divisor,
unsigned long long *remainder)
{
uint64_t result;
unsigned long long result;
ASSERT(divisor);
@@ -65,29 +65,29 @@ static inline uint64_t complete_integer_division_u64(
(FRACTIONAL_PART_MASK & (x))
struct fixed31_32 dal_fixed31_32_from_fraction(
int64_t numerator,
int64_t denominator)
long long numerator,
long long denominator)
{
struct fixed31_32 res;
bool arg1_negative = numerator < 0;
bool arg2_negative = denominator < 0;
uint64_t arg1_value = arg1_negative ? -numerator : numerator;
uint64_t arg2_value = arg2_negative ? -denominator : denominator;
unsigned long long arg1_value = arg1_negative ? -numerator : numerator;
unsigned long long arg2_value = arg2_negative ? -denominator : denominator;
uint64_t remainder;
unsigned long long remainder;
/* determine integer part */
uint64_t res_value = complete_integer_division_u64(
unsigned long long res_value = complete_integer_division_u64(
arg1_value, arg2_value, &remainder);
ASSERT(res_value <= LONG_MAX);
/* determine fractional part */
{
uint32_t i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
unsigned int i = FIXED31_32_BITS_PER_FRACTIONAL_PART;
do {
remainder <<= 1;
@@ -103,14 +103,14 @@ struct fixed31_32 dal_fixed31_32_from_fraction(
/* round up LSB */
{
uint64_t summand = (remainder << 1) >= arg2_value;
unsigned long long summand = (remainder << 1) >= arg2_value;
ASSERT(res_value <= LLONG_MAX - summand);
res_value += summand;
}
res.value = (int64_t)res_value;
res.value = (long long)res_value;
if (arg1_negative ^ arg2_negative)
res.value = -res.value;
@@ -119,7 +119,7 @@ struct fixed31_32 dal_fixed31_32_from_fraction(
}
struct fixed31_32 dal_fixed31_32_from_int_nonconst(
int64_t arg)
long long arg)
{
struct fixed31_32 res;
@@ -132,7 +132,7 @@ struct fixed31_32 dal_fixed31_32_from_int_nonconst(
struct fixed31_32 dal_fixed31_32_shl(
struct fixed31_32 arg,
uint8_t shift)
unsigned char shift)
{
struct fixed31_32 res;
@@ -181,16 +181,16 @@ struct fixed31_32 dal_fixed31_32_mul(
bool arg1_negative = arg1.value < 0;
bool arg2_negative = arg2.value < 0;
uint64_t arg1_value = arg1_negative ? -arg1.value : arg1.value;
uint64_t arg2_value = arg2_negative ? -arg2.value : arg2.value;
unsigned long long arg1_value = arg1_negative ? -arg1.value : arg1.value;
unsigned long long arg2_value = arg2_negative ? -arg2.value : arg2.value;
uint64_t arg1_int = GET_INTEGER_PART(arg1_value);
uint64_t arg2_int = GET_INTEGER_PART(arg2_value);
unsigned long long arg1_int = GET_INTEGER_PART(arg1_value);
unsigned long long arg2_int = GET_INTEGER_PART(arg2_value);
uint64_t arg1_fra = GET_FRACTIONAL_PART(arg1_value);
uint64_t arg2_fra = GET_FRACTIONAL_PART(arg2_value);
unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value);
unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value);
uint64_t tmp;
unsigned long long tmp;
res.value = arg1_int * arg2_int;
@@ -200,22 +200,22 @@ struct fixed31_32 dal_fixed31_32_mul(
tmp = arg1_int * arg2_fra;
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
tmp = arg2_int * arg1_fra;
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
tmp = arg1_fra * arg2_fra;
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
(tmp >= (uint64_t)dal_fixed31_32_half.value);
(tmp >= (unsigned long long)dal_fixed31_32_half.value);
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
@@ -230,13 +230,13 @@ struct fixed31_32 dal_fixed31_32_sqr(
{
struct fixed31_32 res;
uint64_t arg_value = abs_i64(arg.value);
unsigned long long arg_value = abs_i64(arg.value);
uint64_t arg_int = GET_INTEGER_PART(arg_value);
unsigned long long arg_int = GET_INTEGER_PART(arg_value);
uint64_t arg_fra = GET_FRACTIONAL_PART(arg_value);
unsigned long long arg_fra = GET_FRACTIONAL_PART(arg_value);
uint64_t tmp;
unsigned long long tmp;
res.value = arg_int * arg_int;
@@ -246,20 +246,20 @@ struct fixed31_32 dal_fixed31_32_sqr(
tmp = arg_int * arg_fra;
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
tmp = arg_fra * arg_fra;
tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) +
(tmp >= (uint64_t)dal_fixed31_32_half.value);
(tmp >= (unsigned long long)dal_fixed31_32_half.value);
ASSERT(tmp <= (uint64_t)(LLONG_MAX - res.value));
ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));
res.value += tmp;
@@ -288,7 +288,7 @@ struct fixed31_32 dal_fixed31_32_sinc(
struct fixed31_32 res = dal_fixed31_32_one;
int32_t n = 27;
int n = 27;
struct fixed31_32 arg_norm = arg;
@@ -299,7 +299,7 @@ struct fixed31_32 dal_fixed31_32_sinc(
arg_norm,
dal_fixed31_32_mul_int(
dal_fixed31_32_two_pi,
(int32_t)div64_s64(
(int)div64_s64(
arg_norm.value,
dal_fixed31_32_two_pi.value)));
}
@@ -343,7 +343,7 @@ struct fixed31_32 dal_fixed31_32_cos(
struct fixed31_32 res = dal_fixed31_32_one;
int32_t n = 26;
int n = 26;
do {
res = dal_fixed31_32_sub(
@@ -370,7 +370,7 @@ struct fixed31_32 dal_fixed31_32_cos(
static struct fixed31_32 fixed31_32_exp_from_taylor_series(
struct fixed31_32 arg)
{
uint32_t n = 9;
unsigned int n = 9;
struct fixed31_32 res = dal_fixed31_32_from_fraction(
n + 2,
@@ -409,7 +409,7 @@ struct fixed31_32 dal_fixed31_32_exp(
if (dal_fixed31_32_le(
dal_fixed31_32_ln2_div_2,
dal_fixed31_32_abs(arg))) {
int32_t m = dal_fixed31_32_round(
int m = dal_fixed31_32_round(
dal_fixed31_32_div(
arg,
dal_fixed31_32_ln2));
@@ -429,7 +429,7 @@ struct fixed31_32 dal_fixed31_32_exp(
if (m > 0)
return dal_fixed31_32_shl(
fixed31_32_exp_from_taylor_series(r),
(uint8_t)m);
(unsigned char)m);
else
return dal_fixed31_32_div_int(
fixed31_32_exp_from_taylor_series(r),
@@ -482,50 +482,50 @@ struct fixed31_32 dal_fixed31_32_pow(
arg2));
}
int32_t dal_fixed31_32_floor(
int dal_fixed31_32_floor(
struct fixed31_32 arg)
{
uint64_t arg_value = abs_i64(arg.value);
unsigned long long arg_value = abs_i64(arg.value);
if (arg.value >= 0)
return (int32_t)GET_INTEGER_PART(arg_value);
return (int)GET_INTEGER_PART(arg_value);
else
return -(int32_t)GET_INTEGER_PART(arg_value);
return -(int)GET_INTEGER_PART(arg_value);
}
int32_t dal_fixed31_32_round(
int dal_fixed31_32_round(
struct fixed31_32 arg)
{
uint64_t arg_value = abs_i64(arg.value);
unsigned long long arg_value = abs_i64(arg.value);
const int64_t summand = dal_fixed31_32_half.value;
const long long summand = dal_fixed31_32_half.value;
ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
ASSERT(LLONG_MAX - (long long)arg_value >= summand);
arg_value += summand;
if (arg.value >= 0)
return (int32_t)GET_INTEGER_PART(arg_value);
return (int)GET_INTEGER_PART(arg_value);
else
return -(int32_t)GET_INTEGER_PART(arg_value);
return -(int)GET_INTEGER_PART(arg_value);
}
int32_t dal_fixed31_32_ceil(
int dal_fixed31_32_ceil(
struct fixed31_32 arg)
{
uint64_t arg_value = abs_i64(arg.value);
unsigned long long arg_value = abs_i64(arg.value);
const int64_t summand = dal_fixed31_32_one.value -
const long long summand = dal_fixed31_32_one.value -
dal_fixed31_32_epsilon.value;
ASSERT(LLONG_MAX - (int64_t)arg_value >= summand);
ASSERT(LLONG_MAX - (long long)arg_value >= summand);
arg_value += summand;
if (arg.value >= 0)
return (int32_t)GET_INTEGER_PART(arg_value);
return (int)GET_INTEGER_PART(arg_value);
else
return -(int32_t)GET_INTEGER_PART(arg_value);
return -(int)GET_INTEGER_PART(arg_value);
}
/* this function is a generic helper to translate fixed point value to
@@ -535,15 +535,15 @@ int32_t dal_fixed31_32_ceil(
* part in 32 bits. It is used in hw programming (scaler)
*/
static inline uint32_t ux_dy(
int64_t value,
uint32_t integer_bits,
uint32_t fractional_bits)
static inline unsigned int ux_dy(
long long value,
unsigned int integer_bits,
unsigned int fractional_bits)
{
/* 1. create mask of integer part */
uint32_t result = (1 << integer_bits) - 1;
unsigned int result = (1 << integer_bits) - 1;
/* 2. mask out fractional part */
uint32_t fractional_part = FRACTIONAL_PART_MASK & value;
unsigned int fractional_part = FRACTIONAL_PART_MASK & value;
/* 3. shrink fixed point integer part to be of integer_bits width*/
result &= GET_INTEGER_PART(value);
/* 4. make space for fractional part to be filled in after integer */
@@ -554,13 +554,13 @@ static inline uint32_t ux_dy(
return result | fractional_part;
}
static inline uint32_t clamp_ux_dy(
int64_t value,
uint32_t integer_bits,
uint32_t fractional_bits,
uint32_t min_clamp)
static inline unsigned int clamp_ux_dy(
long long value,
unsigned int integer_bits,
unsigned int fractional_bits,
unsigned int min_clamp)
{
uint32_t truncated_val = ux_dy(value, integer_bits, fractional_bits);
unsigned int truncated_val = ux_dy(value, integer_bits, fractional_bits);
if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART)))
return (1 << (integer_bits + fractional_bits)) - 1;
@@ -570,35 +570,35 @@ static inline uint32_t clamp_ux_dy(
return min_clamp;
}
uint32_t dal_fixed31_32_u2d19(
unsigned int dal_fixed31_32_u2d19(
struct fixed31_32 arg)
{
return ux_dy(arg.value, 2, 19);
}
uint32_t dal_fixed31_32_u0d19(
unsigned int dal_fixed31_32_u0d19(
struct fixed31_32 arg)
{
return ux_dy(arg.value, 0, 19);
}
uint32_t dal_fixed31_32_clamp_u0d14(
unsigned int dal_fixed31_32_clamp_u0d14(
struct fixed31_32 arg)
{
return clamp_ux_dy(arg.value, 0, 14, 1);
}
uint32_t dal_fixed31_32_clamp_u0d10(
unsigned int dal_fixed31_32_clamp_u0d10(
struct fixed31_32 arg)
{
return clamp_ux_dy(arg.value, 0, 10, 1);
}
int32_t dal_fixed31_32_s4d19(
int dal_fixed31_32_s4d19(
struct fixed31_32 arg)
{
if (arg.value < 0)
return -(int32_t)ux_dy(dal_fixed31_32_abs(arg).value, 4, 19);
return -(int)ux_dy(dal_fixed31_32_abs(arg).value, 4, 19);
else
return ux_dy(arg.value, 4, 19);
}

86
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
Parādīt failu

@@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1(
struct bios_parser *bp,
struct dc_firmware_info *info);
static enum bp_result get_firmware_info_v3_2(
struct bios_parser *bp,
struct dc_firmware_info *info);
static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
struct atom_display_object_path_v2 *object);
@@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info(
case 3:
switch (revision.minor) {
case 1:
case 2:
result = get_firmware_info_v3_1(bp, info);
break;
case 2:
result = get_firmware_info_v3_2(bp, info);
break;
default:
break;
}
@@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1(
return BP_RESULT_OK;
}
static enum bp_result get_firmware_info_v3_2(
struct bios_parser *bp,
struct dc_firmware_info *info)
{
struct atom_firmware_info_v3_2 *firmware_info;
struct atom_display_controller_info_v4_1 *dce_info = NULL;
struct atom_common_table_header *header;
struct atom_data_revision revision;
struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
if (!info)
return BP_RESULT_BADINPUT;
firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
DATA_TABLES(firmwareinfo));
dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
DATA_TABLES(dce_info));
if (!firmware_info || !dce_info)
return BP_RESULT_BADBIOSTABLE;
memset(info, 0, sizeof(*info));
header = GET_IMAGE(struct atom_common_table_header,
DATA_TABLES(smu_info));
get_atom_data_table_revision(header, &revision);
if (revision.minor == 2) {
/* Vega12 */
smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
DATA_TABLES(smu_info));
if (!smu_info_v3_2)
return BP_RESULT_BADBIOSTABLE;
info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
} else if (revision.minor == 3) {
/* Vega20 */
smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
DATA_TABLES(smu_info));
if (!smu_info_v3_3)
return BP_RESULT_BADBIOSTABLE;
info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
}
// We need to convert from 10KHz units into KHz units.
info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
/* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
/* Hardcode frequency if BIOS gives no DCE Ref Clk */
if (info->pll_info.crystal_frequency == 0) {
if (revision.minor == 2)
info->pll_info.crystal_frequency = 27000;
else if (revision.minor == 3)
info->pll_info.crystal_frequency = 100000;
}
/*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
/* Get GPU PLL VCO Clock */
if (bp->cmd_tbl.get_smu_clock_info != NULL) {
if (revision.minor == 2)
info->smu_gpu_pll_output_freq =
bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
else if (revision.minor == 3)
info->smu_gpu_pll_output_freq =
bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
}
return BP_RESULT_OK;
}
static enum bp_result bios_parser_get_encoder_cap_info(
struct dc_bios *dcb,
struct graphics_object_id object_id,

22
drivers/gpu/drm/amd/display/dc/bios/command_table.c
Parādīt failu

@@ -24,7 +24,7 @@
*/
#include "dm_services.h"
#include "amdgpu.h"
#include "atom.h"
#include "include/bios_parser_interface.h"
@@ -35,16 +35,16 @@
#include "bios_parser_types_internal.h"
#define EXEC_BIOS_CMD_TABLE(command, params)\
(cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \
(amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
GetIndexIntoMasterTable(COMMAND, command), \
&params) == 0)
(uint32_t *)&params) == 0)
#define BIOS_CMD_TABLE_REVISION(command, frev, crev)\
cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \
amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
GetIndexIntoMasterTable(COMMAND, command), &frev, &crev)
#define BIOS_CMD_TABLE_PARA_REVISION(command)\
bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \
bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
GetIndexIntoMasterTable(COMMAND, command))
static void init_dig_encoder_control(struct bios_parser *bp);
@@ -82,16 +82,18 @@ void dal_bios_parser_init_cmd_tbl(struct bios_parser *bp)
init_set_dce_clock(bp);
}
static uint32_t bios_cmd_table_para_revision(void *cgs_device,
static uint32_t bios_cmd_table_para_revision(void *dev,
uint32_t index)
{
struct amdgpu_device *adev = dev;
uint8_t frev, crev;
if (cgs_atom_get_cmd_table_revs(cgs_device,
if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context,
index,
&frev, &crev) != 0)
&frev, &crev))
return crev;
else
return 0;
return crev;
}
/*******************************************************************************
@@ -368,7 +370,7 @@ static void init_transmitter_control(struct bios_parser *bp)
uint8_t crev;
if (BIOS_CMD_TABLE_REVISION(UNIPHYTransmitterControl,
frev, crev) != 0)
frev, crev) == false)
BREAK_TO_DEBUGGER();
switch (crev) {
case 2:

26
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
Parādīt failu

@@ -26,14 +26,18 @@
#include "dm_services.h"
#include "ObjectID.h"
#include "atomfirmware.h"
#include "atomfirmware.h"
#include "atom.h"
#include "include/bios_parser_interface.h"
#include "command_table2.h"
#include "command_table_helper2.h"
#include "bios_parser_helper.h"
#include "bios_parser_types_internal2.h"
#include "amdgpu.h"
#define DC_LOGGER \
bp->base.ctx->logger
@@ -43,16 +47,16 @@
->FieldName)-(char *)0)/sizeof(uint16_t))
#define EXEC_BIOS_CMD_TABLE(fname, params)\
(cgs_atom_exec_cmd_table(bp->base.ctx->cgs_device, \
(amdgpu_atom_execute_table(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
GET_INDEX_INTO_MASTER_TABLE(command, fname), \
&params) == 0)
(uint32_t *)&params) == 0)
#define BIOS_CMD_TABLE_REVISION(fname, frev, crev)\
cgs_atom_get_cmd_table_revs(bp->base.ctx->cgs_device, \
amdgpu_atom_parse_cmd_header(((struct amdgpu_device *)bp->base.ctx->driver_context)->mode_info.atom_context, \
GET_INDEX_INTO_MASTER_TABLE(command, fname), &frev, &crev)
#define BIOS_CMD_TABLE_PARA_REVISION(fname)\
bios_cmd_table_para_revision(bp->base.ctx->cgs_device, \
bios_cmd_table_para_revision(bp->base.ctx->driver_context, \
GET_INDEX_INTO_MASTER_TABLE(command, fname))
static void init_dig_encoder_control(struct bios_parser *bp);
@@ -86,16 +90,18 @@ void dal_firmware_parser_init_cmd_tbl(struct bios_parser *bp)
init_get_smu_clock_info(bp);
}
static uint32_t bios_cmd_table_para_revision(void *cgs_device,
static uint32_t bios_cmd_table_para_revision(void *dev,
uint32_t index)
{
struct amdgpu_device *adev = dev;
uint8_t frev, crev;
if (cgs_atom_get_cmd_table_revs(cgs_device,
if (amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context,
index,
&frev, &crev) != 0)
&frev, &crev))
return crev;
else
return 0;
return crev;
}
/******************************************************************************
@@ -201,7 +207,7 @@ static void init_transmitter_control(struct bios_parser *bp)
uint8_t frev;
uint8_t crev;
if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) != 0)
if (BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) == false)
BREAK_TO_DEBUGGER();
switch (crev) {
case 6:

3
drivers/gpu/drm/amd/display/dc/bios/command_table_helper.c
Parādīt failu

@@ -51,6 +51,9 @@ bool dal_bios_parser_init_cmd_tbl_helper(
return true;
case DCE_VERSION_11_2:
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
#endif
*h = dal_cmd_tbl_helper_dce112_get_table();
return true;

3
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
Parādīt failu

@@ -52,6 +52,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
return true;
case DCE_VERSION_11_2:
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
#endif
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

579
drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h Parasts fails
Parādīt failu

@@ -0,0 +1,579 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef _CALCS_CALCS_LOGGER_H_
#define _CALCS_CALCS_LOGGER_H_
#define DC_LOGGER \
logger
static void print_bw_calcs_dceip(struct dal_logger *logger, const struct bw_calcs_dceip *dceip)
{
DC_LOG_BANDWIDTH_CALCS("#####################################################################");
DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_dceip");
DC_LOG_BANDWIDTH_CALCS("#####################################################################");
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_calcs_version version %d", dceip->version);
DC_LOG_BANDWIDTH_CALCS(" [bool] large_cursor: %d", dceip->large_cursor);
DC_LOG_BANDWIDTH_CALCS(" [bool] dmif_pipe_en_fbc_chunk_tracker: %d", dceip->dmif_pipe_en_fbc_chunk_tracker);
DC_LOG_BANDWIDTH_CALCS(" [bool] display_write_back_supported: %d", dceip->display_write_back_supported);
DC_LOG_BANDWIDTH_CALCS(" [bool] argb_compression_support: %d", dceip->argb_compression_support);
DC_LOG_BANDWIDTH_CALCS(" [bool] pre_downscaler_enabled: %d", dceip->pre_downscaler_enabled);
DC_LOG_BANDWIDTH_CALCS(" [bool] underlay_downscale_prefetch_enabled: %d",
dceip->underlay_downscale_prefetch_enabled);
DC_LOG_BANDWIDTH_CALCS(" [bool] graphics_lb_nodownscaling_multi_line_prefetching: %d",
dceip->graphics_lb_nodownscaling_multi_line_prefetching);
DC_LOG_BANDWIDTH_CALCS(" [bool] limit_excessive_outstanding_dmif_requests: %d",
dceip->limit_excessive_outstanding_dmif_requests);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] cursor_max_outstanding_group_num: %d",
dceip->cursor_max_outstanding_group_num);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] lines_interleaved_into_lb: %d", dceip->lines_interleaved_into_lb);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] low_power_tiling_mode: %d", dceip->low_power_tiling_mode);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] chunk_width: %d", dceip->chunk_width);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_graphics_pipes: %d", dceip->number_of_graphics_pipes);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_underlay_pipes: %d", dceip->number_of_underlay_pipes);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] max_dmif_buffer_allocated: %d", dceip->max_dmif_buffer_allocated);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] graphics_dmif_size: %d", dceip->graphics_dmif_size);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] underlay_luma_dmif_size: %d", dceip->underlay_luma_dmif_size);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] underlay_chroma_dmif_size: %d", dceip->underlay_chroma_dmif_size);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] scatter_gather_lines_of_pte_prefetching_in_linear_mode: %d",
dceip->scatter_gather_lines_of_pte_prefetching_in_linear_mode);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] display_write_back420_luma_mcifwr_buffer_size: %d",
dceip->display_write_back420_luma_mcifwr_buffer_size);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] display_write_back420_chroma_mcifwr_buffer_size: %d",
dceip->display_write_back420_chroma_mcifwr_buffer_size);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] scatter_gather_pte_request_rows_in_tiling_mode: %d",
dceip->scatter_gather_pte_request_rows_in_tiling_mode);
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_vscaler_efficiency10_bit_per_component: %d",
bw_fixed_to_int(dceip->underlay_vscaler_efficiency10_bit_per_component));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_vscaler_efficiency12_bit_per_component: %d",
bw_fixed_to_int(dceip->underlay_vscaler_efficiency12_bit_per_component));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency6_bit_per_component: %d",
bw_fixed_to_int(dceip->graphics_vscaler_efficiency6_bit_per_component));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency8_bit_per_component: %d",
bw_fixed_to_int(dceip->graphics_vscaler_efficiency8_bit_per_component));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency10_bit_per_component: %d",
bw_fixed_to_int(dceip->graphics_vscaler_efficiency10_bit_per_component));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] graphics_vscaler_efficiency12_bit_per_component: %d",
bw_fixed_to_int(dceip->graphics_vscaler_efficiency12_bit_per_component));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] alpha_vscaler_efficiency: %d",
bw_fixed_to_int(dceip->alpha_vscaler_efficiency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_write_pixels_per_dispclk: %d",
bw_fixed_to_int(dceip->lb_write_pixels_per_dispclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_size_per_component444: %d",
bw_fixed_to_int(dceip->lb_size_per_component444));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_and_dram_clock_state_change_gated_before_cursor: %d",
bw_fixed_to_int(dceip->stutter_and_dram_clock_state_change_gated_before_cursor));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay420_luma_lb_size_per_component: %d",
bw_fixed_to_int(dceip->underlay420_luma_lb_size_per_component));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay420_chroma_lb_size_per_component: %d",
bw_fixed_to_int(dceip->underlay420_chroma_lb_size_per_component));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay422_lb_size_per_component: %d",
bw_fixed_to_int(dceip->underlay422_lb_size_per_component));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_chunk_width: %d", bw_fixed_to_int(dceip->cursor_chunk_width));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_dcp_buffer_lines: %d",
bw_fixed_to_int(dceip->cursor_dcp_buffer_lines));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_width_efficient_for_tiling: %d",
bw_fixed_to_int(dceip->underlay_maximum_width_efficient_for_tiling));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_height_efficient_for_tiling: %d",
bw_fixed_to_int(dceip->underlay_maximum_height_efficient_for_tiling));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display: %d",
bw_fixed_to_int(dceip->peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation: %d",
bw_fixed_to_int(dceip->peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] minimum_outstanding_pte_request_limit: %d",
bw_fixed_to_int(dceip->minimum_outstanding_pte_request_limit));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_total_outstanding_pte_requests_allowed_by_saw: %d",
bw_fixed_to_int(dceip->maximum_total_outstanding_pte_requests_allowed_by_saw));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] linear_mode_line_request_alternation_slice: %d",
bw_fixed_to_int(dceip->linear_mode_line_request_alternation_slice));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] request_efficiency: %d", bw_fixed_to_int(dceip->request_efficiency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_per_request: %d", bw_fixed_to_int(dceip->dispclk_per_request));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_ramping_factor: %d",
bw_fixed_to_int(dceip->dispclk_ramping_factor));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_pipe_throughput_factor: %d",
bw_fixed_to_int(dceip->display_pipe_throughput_factor));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_all_surfaces_burst_time: %d",
bw_fixed_to_int(dceip->mcifwr_all_surfaces_burst_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_request_buffer_size: %d",
bw_fixed_to_int(dceip->dmif_request_buffer_size));
}
static void print_bw_calcs_vbios(struct dal_logger *logger, const struct bw_calcs_vbios *vbios)
{
DC_LOG_BANDWIDTH_CALCS("#####################################################################");
DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_vbios vbios");
DC_LOG_BANDWIDTH_CALCS("#####################################################################");
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines memory_type: %d", vbios->memory_type);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines memory_type: %d", vbios->memory_type);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] dram_channel_width_in_bits: %d", vbios->dram_channel_width_in_bits);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_channels: %d", vbios->number_of_dram_channels);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_banks: %d", vbios->number_of_dram_banks);
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_yclk: %d", bw_fixed_to_int(vbios->low_yclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid_yclk: %d", bw_fixed_to_int(vbios->mid_yclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_yclk: %d", bw_fixed_to_int(vbios->high_yclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_sclk: %d", bw_fixed_to_int(vbios->low_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid1_sclk: %d", bw_fixed_to_int(vbios->mid1_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid2_sclk: %d", bw_fixed_to_int(vbios->mid2_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid3_sclk: %d", bw_fixed_to_int(vbios->mid3_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid4_sclk: %d", bw_fixed_to_int(vbios->mid4_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid5_sclk: %d", bw_fixed_to_int(vbios->mid5_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid6_sclk: %d", bw_fixed_to_int(vbios->mid6_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_sclk: %d", bw_fixed_to_int(vbios->high_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_voltage_max_dispclk: %d",
bw_fixed_to_int(vbios->low_voltage_max_dispclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid_voltage_max_dispclk;: %d",
bw_fixed_to_int(vbios->mid_voltage_max_dispclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_voltage_max_dispclk;: %d",
bw_fixed_to_int(vbios->high_voltage_max_dispclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] low_voltage_max_phyclk: %d",
bw_fixed_to_int(vbios->low_voltage_max_phyclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mid_voltage_max_phyclk: %d",
bw_fixed_to_int(vbios->mid_voltage_max_phyclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] high_voltage_max_phyclk: %d",
bw_fixed_to_int(vbios->high_voltage_max_phyclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] data_return_bus_width: %d", bw_fixed_to_int(vbios->data_return_bus_width));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] trc: %d", bw_fixed_to_int(vbios->trc));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmifmc_urgent_latency: %d", bw_fixed_to_int(vbios->dmifmc_urgent_latency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_self_refresh_exit_latency: %d",
bw_fixed_to_int(vbios->stutter_self_refresh_exit_latency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_self_refresh_entry_latency: %d",
bw_fixed_to_int(vbios->stutter_self_refresh_entry_latency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_change_latency: %d",
bw_fixed_to_int(vbios->nbp_state_change_latency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwrmc_urgent_latency: %d",
bw_fixed_to_int(vbios->mcifwrmc_urgent_latency));
DC_LOG_BANDWIDTH_CALCS(" [bool] scatter_gather_enable: %d", vbios->scatter_gather_enable);
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] down_spread_percentage: %d",
bw_fixed_to_int(vbios->down_spread_percentage));
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] cursor_width: %d", vbios->cursor_width);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] average_compression_rate: %d", vbios->average_compression_rate);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_request_slots_gmc_reserves_for_dmif_per_channel: %d",
vbios->number_of_request_slots_gmc_reserves_for_dmif_per_channel);
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] blackout_duration: %d", bw_fixed_to_int(vbios->blackout_duration));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_blackout_recovery_time: %d",
bw_fixed_to_int(vbios->maximum_blackout_recovery_time));
}
static void print_bw_calcs_data(struct dal_logger *logger, struct bw_calcs_data *data)
{
int i, j, k;
DC_LOG_BANDWIDTH_CALCS("#####################################################################");
DC_LOG_BANDWIDTH_CALCS("struct bw_calcs_data data");
DC_LOG_BANDWIDTH_CALCS("#####################################################################");
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_displays: %d", data->number_of_displays);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines underlay_surface_type: %d", data->underlay_surface_type);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines panning_and_bezel_adjustment: %d",
data->panning_and_bezel_adjustment);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines graphics_tiling_mode: %d", data->graphics_tiling_mode);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] graphics_lb_bpc: %d", data->graphics_lb_bpc);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] underlay_lb_bpc: %d", data->underlay_lb_bpc);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines underlay_tiling_mode: %d", data->underlay_tiling_mode);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines d0_underlay_mode: %d", data->d0_underlay_mode);
DC_LOG_BANDWIDTH_CALCS(" [bool] d1_display_write_back_dwb_enable: %d", data->d1_display_write_back_dwb_enable);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines d1_underlay_mode: %d", data->d1_underlay_mode);
DC_LOG_BANDWIDTH_CALCS(" [bool] cpup_state_change_enable: %d", data->cpup_state_change_enable);
DC_LOG_BANDWIDTH_CALCS(" [bool] cpuc_state_change_enable: %d", data->cpuc_state_change_enable);
DC_LOG_BANDWIDTH_CALCS(" [bool] nbp_state_change_enable: %d", data->nbp_state_change_enable);
DC_LOG_BANDWIDTH_CALCS(" [bool] stutter_mode_enable: %d", data->stutter_mode_enable);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] y_clk_level: %d", data->y_clk_level);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] sclk_level: %d", data->sclk_level);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_underlay_surfaces: %d", data->number_of_underlay_surfaces);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_wrchannels: %d", data->number_of_dram_wrchannels);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] chunk_request_delay: %d", data->chunk_request_delay);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] number_of_dram_channels: %d", data->number_of_dram_channels);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines underlay_micro_tile_mode: %d", data->underlay_micro_tile_mode);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines graphics_micro_tile_mode: %d", data->graphics_micro_tile_mode);
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] max_phyclk: %d", bw_fixed_to_int(data->max_phyclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_efficiency: %d", bw_fixed_to_int(data->dram_efficiency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width_after_surface_type: %d",
bw_fixed_to_int(data->src_width_after_surface_type));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height_after_surface_type: %d",
bw_fixed_to_int(data->src_height_after_surface_type));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr_after_surface_type: %d",
bw_fixed_to_int(data->hsr_after_surface_type));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr_after_surface_type: %d", bw_fixed_to_int(data->vsr_after_surface_type));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width_after_rotation: %d",
bw_fixed_to_int(data->src_width_after_rotation));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height_after_rotation: %d",
bw_fixed_to_int(data->src_height_after_rotation));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr_after_rotation: %d", bw_fixed_to_int(data->hsr_after_rotation));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr_after_rotation: %d", bw_fixed_to_int(data->vsr_after_rotation));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_height_pixels: %d", bw_fixed_to_int(data->source_height_pixels));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr_after_stereo: %d", bw_fixed_to_int(data->hsr_after_stereo));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr_after_stereo: %d", bw_fixed_to_int(data->vsr_after_stereo));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_width_in_lb: %d", bw_fixed_to_int(data->source_width_in_lb));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_line_pitch: %d", bw_fixed_to_int(data->lb_line_pitch));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] underlay_maximum_source_efficient_for_tiling: %d",
bw_fixed_to_int(data->underlay_maximum_source_efficient_for_tiling));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] num_lines_at_frame_start: %d",
bw_fixed_to_int(data->num_lines_at_frame_start));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_dmif_size_in_time: %d", bw_fixed_to_int(data->min_dmif_size_in_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_mcifwr_size_in_time: %d",
bw_fixed_to_int(data->min_mcifwr_size_in_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_requests_for_dmif_size: %d",
bw_fixed_to_int(data->total_requests_for_dmif_size));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] peak_pte_request_to_eviction_ratio_limiting: %d",
bw_fixed_to_int(data->peak_pte_request_to_eviction_ratio_limiting));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] useful_pte_per_pte_request: %d",
bw_fixed_to_int(data->useful_pte_per_pte_request));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_request_rows: %d",
bw_fixed_to_int(data->scatter_gather_pte_request_rows));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_row_height: %d",
bw_fixed_to_int(data->scatter_gather_row_height));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_requests_in_vblank: %d",
bw_fixed_to_int(data->scatter_gather_pte_requests_in_vblank));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] inefficient_linear_pitch_in_bytes: %d",
bw_fixed_to_int(data->inefficient_linear_pitch_in_bytes));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_total_data: %d", bw_fixed_to_int(data->cursor_total_data));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_total_request_groups: %d",
bw_fixed_to_int(data->cursor_total_request_groups));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_total_pte_requests: %d",
bw_fixed_to_int(data->scatter_gather_total_pte_requests));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_total_pte_request_groups: %d",
bw_fixed_to_int(data->scatter_gather_total_pte_request_groups));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] tile_width_in_pixels: %d", bw_fixed_to_int(data->tile_width_in_pixels));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_total_number_of_data_request_page_close_open: %d",
bw_fixed_to_int(data->dmif_total_number_of_data_request_page_close_open));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_total_number_of_data_request_page_close_open: %d",
bw_fixed_to_int(data->mcifwr_total_number_of_data_request_page_close_open));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] bytes_per_page_close_open: %d",
bw_fixed_to_int(data->bytes_per_page_close_open));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_total_page_close_open_time: %d",
bw_fixed_to_int(data->mcifwr_total_page_close_open_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_requests_for_adjusted_dmif_size: %d",
bw_fixed_to_int(data->total_requests_for_adjusted_dmif_size));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dmifmc_urgent_trips: %d",
bw_fixed_to_int(data->total_dmifmc_urgent_trips));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dmifmc_urgent_latency: %d",
bw_fixed_to_int(data->total_dmifmc_urgent_latency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_reads_required_data: %d",
bw_fixed_to_int(data->total_display_reads_required_data));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_reads_required_dram_access_data: %d",
bw_fixed_to_int(data->total_display_reads_required_dram_access_data));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_writes_required_data: %d",
bw_fixed_to_int(data->total_display_writes_required_data));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_display_writes_required_dram_access_data: %d",
bw_fixed_to_int(data->total_display_writes_required_dram_access_data));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_required_data: %d",
bw_fixed_to_int(data->display_reads_required_data));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_required_dram_access_data: %d",
bw_fixed_to_int(data->display_reads_required_dram_access_data));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_total_page_close_open_time: %d",
bw_fixed_to_int(data->dmif_total_page_close_open_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_cursor_memory_interface_buffer_size_in_time: %d",
bw_fixed_to_int(data->min_cursor_memory_interface_buffer_size_in_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_read_buffer_size_in_time: %d",
bw_fixed_to_int(data->min_read_buffer_size_in_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_time_for_data_transfer: %d",
bw_fixed_to_int(data->display_reads_time_for_data_transfer));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_writes_time_for_data_transfer: %d",
bw_fixed_to_int(data->display_writes_time_for_data_transfer));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_required_dram_bandwidth: %d",
bw_fixed_to_int(data->dmif_required_dram_bandwidth));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_required_dram_bandwidth: %d",
bw_fixed_to_int(data->mcifwr_required_dram_bandwidth));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_dmifmc_urgent_latency_for_page_close_open: %d",
bw_fixed_to_int(data->required_dmifmc_urgent_latency_for_page_close_open));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_mcifmcwr_urgent_latency: %d",
bw_fixed_to_int(data->required_mcifmcwr_urgent_latency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_dram_bandwidth_gbyte_per_second: %d",
bw_fixed_to_int(data->required_dram_bandwidth_gbyte_per_second));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_bandwidth: %d", bw_fixed_to_int(data->dram_bandwidth));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_required_sclk: %d", bw_fixed_to_int(data->dmif_required_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_required_sclk: %d", bw_fixed_to_int(data->mcifwr_required_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] required_sclk: %d", bw_fixed_to_int(data->required_sclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] downspread_factor: %d", bw_fixed_to_int(data->downspread_factor));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_scaler_efficiency: %d", bw_fixed_to_int(data->v_scaler_efficiency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scaler_limits_factor: %d", bw_fixed_to_int(data->scaler_limits_factor));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_pipe_pixel_throughput: %d",
bw_fixed_to_int(data->display_pipe_pixel_throughput));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_with_ramping: %d",
bw_fixed_to_int(data->total_dispclk_required_with_ramping));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_without_ramping: %d",
bw_fixed_to_int(data->total_dispclk_required_without_ramping));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_read_request_bandwidth: %d",
bw_fixed_to_int(data->total_read_request_bandwidth));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_write_request_bandwidth: %d",
bw_fixed_to_int(data->total_write_request_bandwidth));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_total_read_request_bandwidth: %d",
bw_fixed_to_int(data->dispclk_required_for_total_read_request_bandwidth));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_with_ramping_with_request_bandwidth: %d",
bw_fixed_to_int(data->total_dispclk_required_with_ramping_with_request_bandwidth));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_dispclk_required_without_ramping_with_request_bandwidth: %d",
bw_fixed_to_int(data->total_dispclk_required_without_ramping_with_request_bandwidth));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk: %d", bw_fixed_to_int(data->dispclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] blackout_recovery_time: %d", bw_fixed_to_int(data->blackout_recovery_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_pixels_per_data_fifo_entry: %d",
bw_fixed_to_int(data->min_pixels_per_data_fifo_entry));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] sclk_deep_sleep: %d", bw_fixed_to_int(data->sclk_deep_sleep));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] chunk_request_time: %d", bw_fixed_to_int(data->chunk_request_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_request_time: %d", bw_fixed_to_int(data->cursor_request_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] line_source_pixels_transfer_time: %d",
bw_fixed_to_int(data->line_source_pixels_transfer_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmifdram_access_efficiency: %d",
bw_fixed_to_int(data->dmifdram_access_efficiency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwrdram_access_efficiency: %d",
bw_fixed_to_int(data->mcifwrdram_access_efficiency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_average_bandwidth_no_compression: %d",
bw_fixed_to_int(data->total_average_bandwidth_no_compression));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_average_bandwidth: %d",
bw_fixed_to_int(data->total_average_bandwidth));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] total_stutter_cycle_duration: %d",
bw_fixed_to_int(data->total_stutter_cycle_duration));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_burst_time: %d", bw_fixed_to_int(data->stutter_burst_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] time_in_self_refresh: %d", bw_fixed_to_int(data->time_in_self_refresh));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_efficiency: %d", bw_fixed_to_int(data->stutter_efficiency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] worst_number_of_trips_to_memory: %d",
bw_fixed_to_int(data->worst_number_of_trips_to_memory));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] immediate_flip_time: %d", bw_fixed_to_int(data->immediate_flip_time));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] latency_for_non_dmif_clients: %d",
bw_fixed_to_int(data->latency_for_non_dmif_clients));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] latency_for_non_mcifwr_clients: %d",
bw_fixed_to_int(data->latency_for_non_mcifwr_clients));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmifmc_urgent_latency_supported_in_high_sclk_and_yclk: %d",
bw_fixed_to_int(data->dmifmc_urgent_latency_supported_in_high_sclk_and_yclk));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_dram_speed_change_margin: %d",
bw_fixed_to_int(data->nbp_state_dram_speed_change_margin));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_reads_time_for_data_transfer_and_urgent_latency: %d",
bw_fixed_to_int(data->display_reads_time_for_data_transfer_and_urgent_latency));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_speed_change_margin: %d",
bw_fixed_to_int(data->dram_speed_change_margin));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_vblank_dram_speed_change_margin: %d",
bw_fixed_to_int(data->min_vblank_dram_speed_change_margin));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_stutter_refresh_duration: %d",
bw_fixed_to_int(data->min_stutter_refresh_duration));
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] total_stutter_dmif_buffer_size: %d", data->total_stutter_dmif_buffer_size);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] total_bytes_requested: %d", data->total_bytes_requested);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] min_stutter_dmif_buffer_size: %d", data->min_stutter_dmif_buffer_size);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] num_stutter_bursts: %d", data->num_stutter_bursts);
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_blank_nbp_state_dram_speed_change_latency_supported: %d",
bw_fixed_to_int(data->v_blank_nbp_state_dram_speed_change_latency_supported));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_dram_speed_change_latency_supported: %d",
bw_fixed_to_int(data->nbp_state_dram_speed_change_latency_supported));
for (i = 0; i < maximum_number_of_surfaces; i++) {
DC_LOG_BANDWIDTH_CALCS(" [bool] fbc_en[%d]:%d\n", i, data->fbc_en[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] lpt_en[%d]:%d", i, data->lpt_en[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] displays_match_flag[%d]:%d", i, data->displays_match_flag[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] use_alpha[%d]:%d", i, data->use_alpha[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] orthogonal_rotation[%d]:%d", i, data->orthogonal_rotation[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] enable[%d]:%d", i, data->enable[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] access_one_channel_only[%d]:%d", i, data->access_one_channel_only[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] scatter_gather_enable_for_pipe[%d]:%d",
i, data->scatter_gather_enable_for_pipe[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] interlace_mode[%d]:%d",
i, data->interlace_mode[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] display_pstate_change_enable[%d]:%d",
i, data->display_pstate_change_enable[i]);
DC_LOG_BANDWIDTH_CALCS(" [bool] line_buffer_prefetch[%d]:%d", i, data->line_buffer_prefetch[i]);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] bytes_per_pixel[%d]:%d", i, data->bytes_per_pixel[i]);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] max_chunks_non_fbc_mode[%d]:%d",
i, data->max_chunks_non_fbc_mode[i]);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] lb_bpc[%d]:%d", i, data->lb_bpc[i]);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bpphdmi[%d]:%d", i, data->output_bpphdmi[i]);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bppdp4_lane_hbr[%d]:%d", i, data->output_bppdp4_lane_hbr[i]);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bppdp4_lane_hbr2[%d]:%d",
i, data->output_bppdp4_lane_hbr2[i]);
DC_LOG_BANDWIDTH_CALCS(" [uint32_t] output_bppdp4_lane_hbr3[%d]:%d",
i, data->output_bppdp4_lane_hbr3[i]);
DC_LOG_BANDWIDTH_CALCS(" [enum] bw_defines stereo_mode[%d]:%d", i, data->stereo_mode[i]);
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_buffer_transfer_time[%d]:%d",
i, bw_fixed_to_int(data->dmif_buffer_transfer_time[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] displays_with_same_mode[%d]:%d",
i, bw_fixed_to_int(data->displays_with_same_mode[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_dmif_buffer_size[%d]:%d",
i, bw_fixed_to_int(data->stutter_dmif_buffer_size[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_refresh_duration[%d]:%d",
i, bw_fixed_to_int(data->stutter_refresh_duration[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_exit_watermark[%d]:%d",
i, bw_fixed_to_int(data->stutter_exit_watermark[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_entry_watermark[%d]:%d",
i, bw_fixed_to_int(data->stutter_entry_watermark[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_total[%d]:%d", i, bw_fixed_to_int(data->h_total[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_total[%d]:%d", i, bw_fixed_to_int(data->v_total[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pixel_rate[%d]:%d", i, bw_fixed_to_int(data->pixel_rate[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_width[%d]:%d", i, bw_fixed_to_int(data->src_width[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pitch_in_pixels[%d]:%d",
i, bw_fixed_to_int(data->pitch_in_pixels[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pitch_in_pixels_after_surface_type[%d]:%d",
i, bw_fixed_to_int(data->pitch_in_pixels_after_surface_type[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_height[%d]:%d", i, bw_fixed_to_int(data->src_height[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scale_ratio[%d]:%d", i, bw_fixed_to_int(data->scale_ratio[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_taps[%d]:%d", i, bw_fixed_to_int(data->v_taps[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_scale_ratio[%d]:%d", i, bw_fixed_to_int(data->h_scale_ratio[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_scale_ratio[%d]:%d", i, bw_fixed_to_int(data->v_scale_ratio[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] rotation_angle[%d]:%d",
i, bw_fixed_to_int(data->rotation_angle[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] compression_rate[%d]:%d",
i, bw_fixed_to_int(data->compression_rate[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] hsr[%d]:%d", i, bw_fixed_to_int(data->hsr[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] vsr[%d]:%d", i, bw_fixed_to_int(data->vsr[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_width_rounded_up_to_chunks[%d]:%d",
i, bw_fixed_to_int(data->source_width_rounded_up_to_chunks[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_width_pixels[%d]:%d",
i, bw_fixed_to_int(data->source_width_pixels[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] source_height_rounded_up_to_chunks[%d]:%d",
i, bw_fixed_to_int(data->source_height_rounded_up_to_chunks[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] display_bandwidth[%d]:%d",
i, bw_fixed_to_int(data->display_bandwidth[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] request_bandwidth[%d]:%d",
i, bw_fixed_to_int(data->request_bandwidth[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] bytes_per_request[%d]:%d",
i, bw_fixed_to_int(data->bytes_per_request[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] useful_bytes_per_request[%d]:%d",
i, bw_fixed_to_int(data->useful_bytes_per_request[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lines_interleaved_in_mem_access[%d]:%d",
i, bw_fixed_to_int(data->lines_interleaved_in_mem_access[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] latency_hiding_lines[%d]:%d",
i, bw_fixed_to_int(data->latency_hiding_lines[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_partitions[%d]:%d",
i, bw_fixed_to_int(data->lb_partitions[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_partitions_max[%d]:%d",
i, bw_fixed_to_int(data->lb_partitions_max[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_with_ramping[%d]:%d",
i, bw_fixed_to_int(data->dispclk_required_with_ramping[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_without_ramping[%d]:%d",
i, bw_fixed_to_int(data->dispclk_required_without_ramping[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] data_buffer_size[%d]:%d",
i, bw_fixed_to_int(data->data_buffer_size[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] outstanding_chunk_request_limit[%d]:%d",
i, bw_fixed_to_int(data->outstanding_chunk_request_limit[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] urgent_watermark[%d]:%d",
i, bw_fixed_to_int(data->urgent_watermark[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] nbp_state_change_watermark[%d]:%d",
i, bw_fixed_to_int(data->nbp_state_change_watermark[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_filter_init[%d]:%d", i, bw_fixed_to_int(data->v_filter_init[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] stutter_cycle_duration[%d]:%d",
i, bw_fixed_to_int(data->stutter_cycle_duration[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] average_bandwidth[%d]:%d",
i, bw_fixed_to_int(data->average_bandwidth[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] average_bandwidth_no_compression[%d]:%d",
i, bw_fixed_to_int(data->average_bandwidth_no_compression[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_request_limit[%d]:%d",
i, bw_fixed_to_int(data->scatter_gather_pte_request_limit[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_size_per_component[%d]:%d",
i, bw_fixed_to_int(data->lb_size_per_component[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] memory_chunk_size_in_bytes[%d]:%d",
i, bw_fixed_to_int(data->memory_chunk_size_in_bytes[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pipe_chunk_size_in_bytes[%d]:%d",
i, bw_fixed_to_int(data->pipe_chunk_size_in_bytes[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] number_of_trips_to_memory_for_getting_apte_row[%d]:%d",
i, bw_fixed_to_int(data->number_of_trips_to_memory_for_getting_apte_row[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] adjusted_data_buffer_size[%d]:%d",
i, bw_fixed_to_int(data->adjusted_data_buffer_size[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] adjusted_data_buffer_size_in_memory[%d]:%d",
i, bw_fixed_to_int(data->adjusted_data_buffer_size_in_memory[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pixels_per_data_fifo_entry[%d]:%d",
i, bw_fixed_to_int(data->pixels_per_data_fifo_entry[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_pte_requests_in_row[%d]:%d",
i, bw_fixed_to_int(data->scatter_gather_pte_requests_in_row[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] pte_request_per_chunk[%d]:%d",
i, bw_fixed_to_int(data->pte_request_per_chunk[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_page_width[%d]:%d",
i, bw_fixed_to_int(data->scatter_gather_page_width[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] scatter_gather_page_height[%d]:%d",
i, bw_fixed_to_int(data->scatter_gather_page_height[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_lines_in_per_line_out_in_beginning_of_frame[%d]:%d",
i, bw_fixed_to_int(data->lb_lines_in_per_line_out_in_beginning_of_frame[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] lb_lines_in_per_line_out_in_middle_of_frame[%d]:%d",
i, bw_fixed_to_int(data->lb_lines_in_per_line_out_in_middle_of_frame[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_width_pixels[%d]:%d",
i, bw_fixed_to_int(data->cursor_width_pixels[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] minimum_latency_hiding[%d]:%d",
i, bw_fixed_to_int(data->minimum_latency_hiding[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_latency_hiding[%d]:%d",
i, bw_fixed_to_int(data->maximum_latency_hiding[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] minimum_latency_hiding_with_cursor[%d]:%d",
i, bw_fixed_to_int(data->minimum_latency_hiding_with_cursor[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] maximum_latency_hiding_with_cursor[%d]:%d",
i, bw_fixed_to_int(data->maximum_latency_hiding_with_cursor[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_pixels_for_first_output_pixel[%d]:%d",
i, bw_fixed_to_int(data->src_pixels_for_first_output_pixel[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_pixels_for_last_output_pixel[%d]:%d",
i, bw_fixed_to_int(data->src_pixels_for_last_output_pixel[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_data_for_first_output_pixel[%d]:%d",
i, bw_fixed_to_int(data->src_data_for_first_output_pixel[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] src_data_for_last_output_pixel[%d]:%d",
i, bw_fixed_to_int(data->src_data_for_last_output_pixel[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] active_time[%d]:%d", i, bw_fixed_to_int(data->active_time[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] horizontal_blank_and_chunk_granularity_factor[%d]:%d",
i, bw_fixed_to_int(data->horizontal_blank_and_chunk_granularity_factor[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] cursor_latency_hiding[%d]:%d",
i, bw_fixed_to_int(data->cursor_latency_hiding[i]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] v_blank_dram_speed_change_margin[%d]:%d",
i, bw_fixed_to_int(data->v_blank_dram_speed_change_margin[i]));
}
for (i = 0; i < maximum_number_of_surfaces; i++) {
for (j = 0; j < 3; j++) {
for (k = 0; k < 8; k++) {
DC_LOG_BANDWIDTH_CALCS("\n [bw_fixed] line_source_transfer_time[%d][%d][%d]:%d",
i, j, k, bw_fixed_to_int(data->line_source_transfer_time[i][j][k]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dram_speed_change_line_source_transfer_time[%d][%d][%d]:%d",
i, j, k,
bw_fixed_to_int(data->dram_speed_change_line_source_transfer_time[i][j][k]));
}
}
}
for (i = 0; i < 3; i++) {
for (j = 0; j < 8; j++) {
DC_LOG_BANDWIDTH_CALCS("\n [uint32_t] num_displays_with_margin[%d][%d]:%d",
i, j, data->num_displays_with_margin[i][j]);
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_burst_time[%d][%d]:%d",
i, j, bw_fixed_to_int(data->dmif_burst_time[i][j]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] mcifwr_burst_time[%d][%d]:%d",
i, j, bw_fixed_to_int(data->mcifwr_burst_time[i][j]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] min_dram_speed_change_margin[%d][%d]:%d",
i, j, bw_fixed_to_int(data->min_dram_speed_change_margin[i][j]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_dram_speed_change[%d][%d]:%d",
i, j, bw_fixed_to_int(data->dispclk_required_for_dram_speed_change[i][j]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] blackout_duration_margin[%d][%d]:%d",
i, j, bw_fixed_to_int(data->blackout_duration_margin[i][j]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_blackout_duration[%d][%d]:%d",
i, j, bw_fixed_to_int(data->dispclk_required_for_blackout_duration[i][j]));
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dispclk_required_for_blackout_recovery[%d][%d]:%d",
i, j, bw_fixed_to_int(data->dispclk_required_for_blackout_recovery[i][j]));
}
}
for (i = 0; i < 6; i++) {
DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] dmif_required_sclk_for_urgent_latency[%d]:%d",
i, bw_fixed_to_int(data->dmif_required_sclk_for_urgent_latency[i]));
}
}
;
#endif /* _CALCS_CALCS_LOGGER_H_ */

260
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
Parādīt failu

@@ -28,6 +28,7 @@
#include "dc.h"
#include "core_types.h"
#include "dal_asic_id.h"
#include "calcs_logger.h"
/*
* NOTE:
@@ -52,11 +53,16 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi
return BW_CALCS_VERSION_CARRIZO;
case FAMILY_VI:
if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_POLARIS12;
if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_POLARIS10;
if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_POLARIS11;
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
return BW_CALCS_VERSION_VEGAM;
#endif
return BW_CALCS_VERSION_INVALID;
case FAMILY_AI:
@@ -2145,6 +2151,11 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); /* todo: this is a bug*/
break;
case BW_CALCS_VERSION_POLARIS10:
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
/* TODO: Treat VEGAM the same as P10 for now
* Need to tune the para for VEGAM if needed */
case BW_CALCS_VERSION_VEGAM:
#endif
vbios.memory_type = bw_def_gddr5;
vbios.dram_channel_width_in_bits = 32;
vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
@@ -2373,6 +2384,122 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
break;
case BW_CALCS_VERSION_POLARIS12:
vbios.memory_type = bw_def_gddr5;
vbios.dram_channel_width_in_bits = 32;
vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
vbios.number_of_dram_banks = 8;
vbios.high_yclk = bw_int_to_fixed(6000);
vbios.mid_yclk = bw_int_to_fixed(3200);
vbios.low_yclk = bw_int_to_fixed(1000);
vbios.low_sclk = bw_int_to_fixed(678);
vbios.mid1_sclk = bw_int_to_fixed(864);
vbios.mid2_sclk = bw_int_to_fixed(900);
vbios.mid3_sclk = bw_int_to_fixed(920);
vbios.mid4_sclk = bw_int_to_fixed(940);
vbios.mid5_sclk = bw_int_to_fixed(960);
vbios.mid6_sclk = bw_int_to_fixed(980);
vbios.high_sclk = bw_int_to_fixed(1049);
vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
vbios.data_return_bus_width = bw_int_to_fixed(32);
vbios.trc = bw_int_to_fixed(48);
if (vbios.number_of_dram_channels == 2) // 64-bit
vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
else
vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
vbios.nbp_state_change_latency = bw_int_to_fixed(250);
vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
vbios.scatter_gather_enable = false;
vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
vbios.cursor_width = 32;
vbios.average_compression_rate = 4;
vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
vbios.blackout_duration = bw_int_to_fixed(0); /* us */
vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
dceip.large_cursor = false;
dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
dceip.dmif_pipe_en_fbc_chunk_tracker = false;
dceip.cursor_max_outstanding_group_num = 1;
dceip.lines_interleaved_into_lb = 2;
dceip.chunk_width = 256;
dceip.number_of_graphics_pipes = 5;
dceip.number_of_underlay_pipes = 0;
dceip.low_power_tiling_mode = 0;
dceip.display_write_back_supported = true;
dceip.argb_compression_support = true;
dceip.underlay_vscaler_efficiency6_bit_per_component =
bw_frc_to_fixed(35556, 10000);
dceip.underlay_vscaler_efficiency8_bit_per_component =
bw_frc_to_fixed(34286, 10000);
dceip.underlay_vscaler_efficiency10_bit_per_component =
bw_frc_to_fixed(32, 10);
dceip.underlay_vscaler_efficiency12_bit_per_component =
bw_int_to_fixed(3);
dceip.graphics_vscaler_efficiency6_bit_per_component =
bw_frc_to_fixed(35, 10);
dceip.graphics_vscaler_efficiency8_bit_per_component =
bw_frc_to_fixed(34286, 10000);
dceip.graphics_vscaler_efficiency10_bit_per_component =
bw_frc_to_fixed(32, 10);
dceip.graphics_vscaler_efficiency12_bit_per_component =
bw_int_to_fixed(3);
dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
dceip.max_dmif_buffer_allocated = 4;
dceip.graphics_dmif_size = 12288;
dceip.underlay_luma_dmif_size = 19456;
dceip.underlay_chroma_dmif_size = 23552;
dceip.pre_downscaler_enabled = true;
dceip.underlay_downscale_prefetch_enabled = true;
dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
bw_int_to_fixed(1);
dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
82176);
dceip.underlay420_chroma_lb_size_per_component =
bw_int_to_fixed(164352);
dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
82176);
dceip.cursor_chunk_width = bw_int_to_fixed(64);
dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
dceip.underlay_maximum_width_efficient_for_tiling =
bw_int_to_fixed(1920);
dceip.underlay_maximum_height_efficient_for_tiling =
bw_int_to_fixed(1080);
dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
bw_frc_to_fixed(3, 10);
dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
bw_int_to_fixed(25);
dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
2);
dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
bw_int_to_fixed(128);
dceip.limit_excessive_outstanding_dmif_requests = true;
dceip.linear_mode_line_request_alternation_slice =
bw_int_to_fixed(64);
dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
32;
dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
dceip.request_efficiency = bw_frc_to_fixed(8, 10);
dceip.dispclk_per_request = bw_int_to_fixed(2);
dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
break;
case BW_CALCS_VERSION_STONEY:
vbios.memory_type = bw_def_gddr5;
vbios.dram_channel_width_in_bits = 64;
@@ -2815,6 +2942,19 @@ static void populate_initial_data(
data->bytes_per_pixel[num_displays + 4] = 4;
break;
}
} else if (pipe[i].stream->dst.width != 0 &&
pipe[i].stream->dst.height != 0 &&
pipe[i].stream->src.width != 0 &&
pipe[i].stream->src.height != 0) {
data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.width);
data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->src.height);
data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
data->v_taps[num_displays + 4] = pipe[i].stream->src.height == pipe[i].stream->dst.height ? bw_int_to_fixed(1) : bw_int_to_fixed(2);
data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);
data->v_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.height, pipe[i].stream->dst.height);
data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0);
data->bytes_per_pixel[num_displays + 4] = 4;
} else {
data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
@@ -2873,6 +3013,11 @@ bool bw_calcs(struct dc_context *ctx,
struct bw_fixed mid_yclk = vbios->mid_yclk;
struct bw_fixed low_yclk = vbios->low_yclk;
if (ctx->dc->debug.bandwidth_calcs_trace) {
print_bw_calcs_dceip(ctx->logger, dceip);
print_bw_calcs_vbios(ctx->logger, vbios);
print_bw_calcs_data(ctx->logger, data);
}
calculate_bandwidth(dceip, vbios, data);
yclk_lvl = data->y_clk_level;
@@ -2968,7 +3113,33 @@ bool bw_calcs(struct dc_context *ctx,
bw_fixed_to_int(bw_mul(data->
stutter_exit_watermark[9], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[0].a_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[4], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[1].a_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[5], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[2].a_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[6], bw_int_to_fixed(1000)));
if (ctx->dc->caps.max_slave_planes) {
calcs_output->stutter_entry_wm_ns[3].a_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[0], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[4].a_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[1], bw_int_to_fixed(1000)));
} else {
calcs_output->stutter_entry_wm_ns[3].a_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[7], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[4].a_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[8], bw_int_to_fixed(1000)));
}
calcs_output->stutter_entry_wm_ns[5].a_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[9], bw_int_to_fixed(1000)));
calcs_output->urgent_wm_ns[0].a_mark =
bw_fixed_to_int(bw_mul(data->
@@ -3063,7 +3234,33 @@ bool bw_calcs(struct dc_context *ctx,
bw_fixed_to_int(bw_mul(data->
stutter_exit_watermark[9], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[0].b_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[4], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[1].b_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[5], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[2].b_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[6], bw_int_to_fixed(1000)));
if (ctx->dc->caps.max_slave_planes) {
calcs_output->stutter_entry_wm_ns[3].b_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[0], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[4].b_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[1], bw_int_to_fixed(1000)));
} else {
calcs_output->stutter_entry_wm_ns[3].b_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[7], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[4].b_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[8], bw_int_to_fixed(1000)));
}
calcs_output->stutter_entry_wm_ns[5].b_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[9], bw_int_to_fixed(1000)));
calcs_output->urgent_wm_ns[0].b_mark =
bw_fixed_to_int(bw_mul(data->
@@ -3156,6 +3353,34 @@ bool bw_calcs(struct dc_context *ctx,
bw_fixed_to_int(bw_mul(data->
stutter_exit_watermark[9], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[0].c_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[4], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[1].c_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[5], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[2].c_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[6], bw_int_to_fixed(1000)));
if (ctx->dc->caps.max_slave_planes) {
calcs_output->stutter_entry_wm_ns[3].c_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[0], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[4].c_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[1], bw_int_to_fixed(1000)));
} else {
calcs_output->stutter_entry_wm_ns[3].c_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[7], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[4].c_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[8], bw_int_to_fixed(1000)));
}
calcs_output->stutter_entry_wm_ns[5].c_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[9], bw_int_to_fixed(1000)));
calcs_output->urgent_wm_ns[0].c_mark =
bw_fixed_to_int(bw_mul(data->
urgent_watermark[4], bw_int_to_fixed(1000)));
@@ -3260,6 +3485,33 @@ bool bw_calcs(struct dc_context *ctx,
bw_fixed_to_int(bw_mul(data->
stutter_exit_watermark[9], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[0].d_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[4], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[1].d_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[5], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[2].d_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[6], bw_int_to_fixed(1000)));
if (ctx->dc->caps.max_slave_planes) {
calcs_output->stutter_entry_wm_ns[3].d_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[0], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[4].d_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[1], bw_int_to_fixed(1000)));
} else {
calcs_output->stutter_entry_wm_ns[3].d_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[7], bw_int_to_fixed(1000)));
calcs_output->stutter_entry_wm_ns[4].d_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[8], bw_int_to_fixed(1000)));
}
calcs_output->stutter_entry_wm_ns[5].d_mark =
bw_fixed_to_int(bw_mul(data->
stutter_entry_watermark[9], bw_int_to_fixed(1000)));
calcs_output->urgent_wm_ns[0].d_mark =
bw_fixed_to_int(bw_mul(data->

74
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
Parādīt failu

@@ -1459,39 +1459,39 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
void dcn_bw_sync_calcs_and_dml(struct dc *dc)
{
kernel_fpu_begin();
DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %d ns\n"
"sr_enter_plus_exit_time: %d ns\n"
"urgent_latency: %d ns\n"
"write_back_latency: %d ns\n"
"percent_of_ideal_drambw_received_after_urg_latency: %d %\n"
DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
"sr_enter_plus_exit_time: %f ns\n"
"urgent_latency: %f ns\n"
"write_back_latency: %f ns\n"
"percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
"max_request_size: %d bytes\n"
"dcfclkv_max0p9: %d kHz\n"
"dcfclkv_nom0p8: %d kHz\n"
"dcfclkv_mid0p72: %d kHz\n"
"dcfclkv_min0p65: %d kHz\n"
"max_dispclk_vmax0p9: %d kHz\n"
"max_dispclk_vnom0p8: %d kHz\n"
"max_dispclk_vmid0p72: %d kHz\n"
"max_dispclk_vmin0p65: %d kHz\n"
"max_dppclk_vmax0p9: %d kHz\n"
"max_dppclk_vnom0p8: %d kHz\n"
"max_dppclk_vmid0p72: %d kHz\n"
"max_dppclk_vmin0p65: %d kHz\n"
"socclk: %d kHz\n"
"fabric_and_dram_bandwidth_vmax0p9: %d MB/s\n"
"fabric_and_dram_bandwidth_vnom0p8: %d MB/s\n"
"fabric_and_dram_bandwidth_vmid0p72: %d MB/s\n"
"fabric_and_dram_bandwidth_vmin0p65: %d MB/s\n"
"phyclkv_max0p9: %d kHz\n"
"phyclkv_nom0p8: %d kHz\n"
"phyclkv_mid0p72: %d kHz\n"
"phyclkv_min0p65: %d kHz\n"
"downspreading: %d %\n"
"dcfclkv_max0p9: %f kHz\n"
"dcfclkv_nom0p8: %f kHz\n"
"dcfclkv_mid0p72: %f kHz\n"
"dcfclkv_min0p65: %f kHz\n"
"max_dispclk_vmax0p9: %f kHz\n"
"max_dispclk_vnom0p8: %f kHz\n"
"max_dispclk_vmid0p72: %f kHz\n"
"max_dispclk_vmin0p65: %f kHz\n"
"max_dppclk_vmax0p9: %f kHz\n"
"max_dppclk_vnom0p8: %f kHz\n"
"max_dppclk_vmid0p72: %f kHz\n"
"max_dppclk_vmin0p65: %f kHz\n"
"socclk: %f kHz\n"
"fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
"fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
"fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
"fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
"phyclkv_max0p9: %f kHz\n"
"phyclkv_nom0p8: %f kHz\n"
"phyclkv_mid0p72: %f kHz\n"
"phyclkv_min0p65: %f kHz\n"
"downspreading: %f %%\n"
"round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
"urgent_out_of_order_return_per_channel: %d Bytes\n"
"number_of_channels: %d\n"
"vmm_page_size: %d Bytes\n"
"dram_clock_change_latency: %d ns\n"
"dram_clock_change_latency: %f ns\n"
"return_bus_width: %d Bytes\n",
dc->dcn_soc->sr_exit_time * 1000,
dc->dcn_soc->sr_enter_plus_exit_time * 1000,
@@ -1527,11 +1527,11 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
dc->dcn_soc->vmm_page_size,
dc->dcn_soc->dram_clock_change_latency * 1000,
dc->dcn_soc->return_bus_width);
DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %d\n"
"det_buffer_size_in_kbyte: %d\n"
"dpp_output_buffer_pixels: %d\n"
"opp_output_buffer_lines: %d\n"
"pixel_chunk_size_in_kbyte: %d\n"
DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
"det_buffer_size_in_kbyte: %f\n"
"dpp_output_buffer_pixels: %f\n"
"opp_output_buffer_lines: %f\n"
"pixel_chunk_size_in_kbyte: %f\n"
"pte_enable: %d\n"
"pte_chunk_size: %d kbytes\n"
"meta_chunk_size: %d kbytes\n"
@@ -1550,13 +1550,13 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
"max_pscl_tolb_throughput: %d pixels/dppclk\n"
"max_lb_tovscl_throughput: %d pixels/dppclk\n"
"max_vscl_tohscl_throughput: %d pixels/dppclk\n"
"max_hscl_ratio: %d\n"
"max_vscl_ratio: %d\n"
"max_hscl_ratio: %f\n"
"max_vscl_ratio: %f\n"
"max_hscl_taps: %d\n"
"max_vscl_taps: %d\n"
"pte_buffer_size_in_requests: %d\n"
"dispclk_ramping_margin: %d %\n"
"under_scan_factor: %d %\n"
"dispclk_ramping_margin: %f %%\n"
"under_scan_factor: %f %%\n"
"max_inter_dcn_tile_repeaters: %d\n"
"can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
"bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"

112
drivers/gpu/drm/amd/display/dc/core/dc.c
Parādīt failu

@@ -936,95 +936,6 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
return true;
}
/*
* TODO this whole function needs to go
*
* dc_surface_update is needlessly complex. See if we can just replace this
* with a dc_plane_state and follow the atomic model a bit more closely here.
*/
bool dc_commit_planes_to_stream(
struct dc *dc,
struct dc_plane_state **plane_states,
uint8_t new_plane_count,
struct dc_stream_state *dc_stream,
struct dc_state *state)
{
/* no need to dynamically allocate this. it's pretty small */
struct dc_surface_update updates[MAX_SURFACES];
struct dc_flip_addrs *flip_addr;
struct dc_plane_info *plane_info;
struct dc_scaling_info *scaling_info;
int i;
struct dc_stream_update *stream_update =
kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL);
if (!stream_update) {
BREAK_TO_DEBUGGER();
return false;
}
flip_addr = kcalloc(MAX_SURFACES, sizeof(struct dc_flip_addrs),
GFP_KERNEL);
plane_info = kcalloc(MAX_SURFACES, sizeof(struct dc_plane_info),
GFP_KERNEL);
scaling_info = kcalloc(MAX_SURFACES, sizeof(struct dc_scaling_info),
GFP_KERNEL);
if (!flip_addr || !plane_info || !scaling_info) {
kfree(flip_addr);
kfree(plane_info);
kfree(scaling_info);
kfree(stream_update);
return false;
}
memset(updates, 0, sizeof(updates));
stream_update->src = dc_stream->src;
stream_update->dst = dc_stream->dst;
stream_update->out_transfer_func = dc_stream->out_transfer_func;
for (i = 0; i < new_plane_count; i++) {
updates[i].surface = plane_states[i];
updates[i].gamma =
(struct dc_gamma *)plane_states[i]->gamma_correction;
updates[i].in_transfer_func = plane_states[i]->in_transfer_func;
flip_addr[i].address = plane_states[i]->address;
flip_addr[i].flip_immediate = plane_states[i]->flip_immediate;
plane_info[i].color_space = plane_states[i]->color_space;
plane_info[i].input_tf = plane_states[i]->input_tf;
plane_info[i].format = plane_states[i]->format;
plane_info[i].plane_size = plane_states[i]->plane_size;
plane_info[i].rotation = plane_states[i]->rotation;
plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror;
plane_info[i].stereo_format = plane_states[i]->stereo_format;
plane_info[i].tiling_info = plane_states[i]->tiling_info;
plane_info[i].visible = plane_states[i]->visible;
plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha;
plane_info[i].dcc = plane_states[i]->dcc;
scaling_info[i].scaling_quality = plane_states[i]->scaling_quality;
scaling_info[i].src_rect = plane_states[i]->src_rect;
scaling_info[i].dst_rect = plane_states[i]->dst_rect;
scaling_info[i].clip_rect = plane_states[i]->clip_rect;
updates[i].flip_addr = &flip_addr[i];
updates[i].plane_info = &plane_info[i];
updates[i].scaling_info = &scaling_info[i];
}
dc_commit_updates_for_stream(
dc,
updates,
new_plane_count,
dc_stream, stream_update, plane_states, state);
kfree(flip_addr);
kfree(plane_info);
kfree(scaling_info);
kfree(stream_update);
return true;
}
struct dc_state *dc_create_state(void)
{
struct dc_state *context = kzalloc(sizeof(struct dc_state),
@@ -1107,9 +1018,6 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
if (u->plane_info->color_space != u->surface->color_space)
update_flags->bits.color_space_change = 1;
if (u->plane_info->input_tf != u->surface->input_tf)
update_flags->bits.input_tf_change = 1;
if (u->plane_info->horizontal_mirror != u->surface->horizontal_mirror)
update_flags->bits.horizontal_mirror_change = 1;
@@ -1243,12 +1151,20 @@ static enum surface_update_type det_surface_update(const struct dc *dc,
if (u->input_csc_color_matrix)
update_flags->bits.input_csc_change = 1;
if (update_flags->bits.in_transfer_func_change
|| update_flags->bits.input_csc_change) {
if (u->coeff_reduction_factor)
update_flags->bits.coeff_reduction_change = 1;
if (update_flags->bits.in_transfer_func_change) {
type = UPDATE_TYPE_MED;
elevate_update_type(&overall_type, type);
}
if (update_flags->bits.input_csc_change
|| update_flags->bits.coeff_reduction_change) {
type = UPDATE_TYPE_FULL;
elevate_update_type(&overall_type, type);
}
return overall_type;
}
@@ -1297,7 +1213,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream(
type = check_update_surfaces_for_stream(dc, updates, surface_count, stream_update, stream_status);
if (type == UPDATE_TYPE_FULL)
for (i = 0; i < surface_count; i++)
updates[i].surface->update_flags.bits.full_update = 1;
updates[i].surface->update_flags.raw = 0xFFFFFFFF;
return type;
}
@@ -1375,6 +1291,12 @@ static void commit_planes_for_stream(struct dc *dc,
pipe_ctx->stream_res.abm->funcs->set_abm_level(
pipe_ctx->stream_res.abm, stream->abm_level);
}
if (stream_update && stream_update->periodic_fn_vsync_delta &&
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing,
pipe_ctx->stream->periodic_fn_vsync_delta);
}
}

38
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
Parādīt failu

@@ -36,8 +36,9 @@
#include "hw_sequencer.h"
#include "resource.h"
#define DC_LOGGER \
logger
#define DC_LOGGER_INIT(logger)
#define SURFACE_TRACE(...) do {\
if (dc->debug.surface_trace) \
@@ -60,8 +61,7 @@ void pre_surface_trace(
int surface_count)
{
int i;
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
DC_LOGGER_INIT(dc->ctx->logger);
for (i = 0; i < surface_count; i++) {
const struct dc_plane_state *plane_state = plane_states[i];
@@ -72,8 +72,8 @@ void pre_surface_trace(
"plane_state->visible = %d;\n"
"plane_state->flip_immediate = %d;\n"
"plane_state->address.type = %d;\n"
"plane_state->address.grph.addr.quad_part = 0x%X;\n"
"plane_state->address.grph.meta_addr.quad_part = 0x%X;\n"
"plane_state->address.grph.addr.quad_part = 0x%llX;\n"
"plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n"
"plane_state->scaling_quality.h_taps = %d;\n"
"plane_state->scaling_quality.v_taps = %d;\n"
"plane_state->scaling_quality.h_taps_c = %d;\n"
@@ -155,7 +155,6 @@ void pre_surface_trace(
"plane_state->tiling_info.gfx8.pipe_config = %d;\n"
"plane_state->tiling_info.gfx8.array_mode = %d;\n"
"plane_state->color_space = %d;\n"
"plane_state->input_tf = %d;\n"
"plane_state->dcc.enable = %d;\n"
"plane_state->format = %d;\n"
"plane_state->rotation = %d;\n"
@@ -163,7 +162,6 @@ void pre_surface_trace(
plane_state->tiling_info.gfx8.pipe_config,
plane_state->tiling_info.gfx8.array_mode,
plane_state->color_space,
plane_state->input_tf,
plane_state->dcc.enable,
plane_state->format,
plane_state->rotation,
@@ -183,8 +181,7 @@ void update_surface_trace(
int surface_count)
{
int i;
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
DC_LOGGER_INIT(dc->ctx->logger);
for (i = 0; i < surface_count; i++) {
const struct dc_surface_update *update = &updates[i];
@@ -192,8 +189,8 @@ void update_surface_trace(
SURFACE_TRACE("Update %d\n", i);
if (update->flip_addr) {
SURFACE_TRACE("flip_addr->address.type = %d;\n"
"flip_addr->address.grph.addr.quad_part = 0x%X;\n"
"flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n"
"flip_addr->address.grph.addr.quad_part = 0x%llX;\n"
"flip_addr->address.grph.meta_addr.quad_part = 0x%llX;\n"
"flip_addr->flip_immediate = %d;\n",
update->flip_addr->address.type,
update->flip_addr->address.grph.addr.quad_part,
@@ -204,16 +201,15 @@ void update_surface_trace(
if (update->plane_info) {
SURFACE_TRACE(
"plane_info->color_space = %d;\n"
"plane_info->input_tf = %d;\n"
"plane_info->format = %d;\n"
"plane_info->plane_size.grph.surface_pitch = %d;\n"
"plane_info->plane_size.grph.surface_size.height = %d;\n"
"plane_info->plane_size.grph.surface_size.width = %d;\n"
"plane_info->plane_size.grph.surface_size.x = %d;\n"
"plane_info->plane_size.grph.surface_size.y = %d;\n"
"plane_info->rotation = %d;\n",
"plane_info->rotation = %d;\n"
"plane_info->stereo_format = %d;\n",
update->plane_info->color_space,
update->plane_info->input_tf,
update->plane_info->format,
update->plane_info->plane_size.grph.surface_pitch,
update->plane_info->plane_size.grph.surface_size.height,
@@ -303,8 +299,7 @@ void update_surface_trace(
void post_surface_trace(struct dc *dc)
{
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
DC_LOGGER_INIT(dc->ctx->logger);
SURFACE_TRACE("post surface process.\n");
@@ -316,10 +311,10 @@ void context_timing_trace(
{
int i;
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
struct crtc_position position;
unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
DC_LOGGER_INIT(dc->ctx->logger);
for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
@@ -354,9 +349,7 @@ void context_clock_trace(
struct dc_state *context)
{
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
DC_LOGGER_INIT(dc->ctx->logger);
CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
context->bw.dcn.calc_clk.dispclk_khz,
@@ -371,6 +364,7 @@ void context_clock_trace(
context->bw.dcn.calc_clk.dppclk_khz,
context->bw.dcn.calc_clk.dcfclk_khz,
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
context->bw.dcn.calc_clk.fclk_khz);
context->bw.dcn.calc_clk.fclk_khz,
context->bw.dcn.calc_clk.socclk_khz);
#endif
}

24
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
Parādīt failu

@@ -208,6 +208,7 @@ void color_space_to_black_color(
case COLOR_SPACE_YCBCR709:
case COLOR_SPACE_YCBCR601_LIMITED:
case COLOR_SPACE_YCBCR709_LIMITED:
case COLOR_SPACE_2020_YCBCR:
*black_color = black_color_format[BLACK_COLOR_FORMAT_YUV_CV];
break;
@@ -216,7 +217,25 @@ void color_space_to_black_color(
black_color_format[BLACK_COLOR_FORMAT_RGB_LIMITED];
break;
default:
/**
* Remove default and add case for all color space
* so when we forget to add new color space
* compiler will give a warning
*/
case COLOR_SPACE_UNKNOWN:
case COLOR_SPACE_SRGB:
case COLOR_SPACE_XR_RGB:
case COLOR_SPACE_MSREF_SCRGB:
case COLOR_SPACE_XV_YCC_709:
case COLOR_SPACE_XV_YCC_601:
case COLOR_SPACE_2020_RGB_FULLRANGE:
case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
case COLOR_SPACE_ADOBERGB:
case COLOR_SPACE_DCIP3:
case COLOR_SPACE_DISPLAYNATIVE:
case COLOR_SPACE_DOLBYVISION:
case COLOR_SPACE_APPCTRL:
case COLOR_SPACE_CUSTOMPOINTS:
/* fefault is sRGB black (full range). */
*black_color =
black_color_format[BLACK_COLOR_FORMAT_RGB_FULLRANGE];
@@ -230,6 +249,9 @@ bool hwss_wait_for_blank_complete(
{
int counter;
/* Not applicable if the pipe is not primary, save 300ms of boot time */
if (!tg->funcs->is_blanked)
return true;
for (counter = 0; counter < 100; counter++) {
if (tg->funcs->is_blanked(tg))
break;

63
drivers/gpu/drm/amd/display/dc/core/dc_link.c
Parādīt failu

@@ -45,8 +45,9 @@
#include "dce/dce_11_0_d.h"
#include "dce/dce_11_0_enum.h"
#include "dce/dce_11_0_sh_mask.h"
#define DC_LOGGER \
dc_ctx->logger
#define DC_LOGGER_INIT(logger)
#define LINK_INFO(...) \
DC_LOG_HW_HOTPLUG( \
@@ -561,7 +562,7 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
struct dc_context *dc_ctx = link->ctx;
struct dc_sink *sink = NULL;
enum dc_connection_type new_connection_type = dc_connection_none;
DC_LOGGER_INIT(link->ctx->logger);
if (link->connector_signal == SIGNAL_TYPE_VIRTUAL)
return false;
@@ -927,6 +928,7 @@ static bool construct(
struct integrated_info info = {{{ 0 }}};
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
DC_LOGGER_INIT(dc_ctx->logger);
link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
@@ -1135,7 +1137,8 @@ static void dpcd_configure_panel_mode(
{
union dpcd_edp_config edp_config_set;
bool panel_mode_edp = false;
struct dc_context *dc_ctx = link->ctx;
DC_LOGGER_INIT(link->ctx->logger);
memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
if (DP_PANEL_MODE_DEFAULT != panel_mode) {
@@ -1183,16 +1186,21 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx)
{
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->sink->link;
union down_spread_ctrl downspread;
union down_spread_ctrl old_downspread;
union down_spread_ctrl new_downspread;
core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
&downspread.raw, sizeof(downspread));
&old_downspread.raw, sizeof(old_downspread));
downspread.bits.IGNORE_MSA_TIMING_PARAM =
new_downspread.raw = old_downspread.raw;
new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
(stream->ignore_msa_timing_param) ? 1 : 0;
core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
&downspread.raw, sizeof(downspread));
if (new_downspread.raw != old_downspread.raw) {
core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
&new_downspread.raw, sizeof(new_downspread));
}
}
static enum dc_status enable_link_dp(
@@ -1843,9 +1851,22 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
static bool dp_active_dongle_validate_timing(
const struct dc_crtc_timing *timing,
const struct dc_dongle_caps *dongle_caps)
const struct dpcd_caps *dpcd_caps)
{
unsigned int required_pix_clk = timing->pix_clk_khz;
const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
switch (dpcd_caps->dongle_type) {
case DISPLAY_DONGLE_DP_VGA_CONVERTER:
case DISPLAY_DONGLE_DP_DVI_CONVERTER:
case DISPLAY_DONGLE_DP_DVI_DONGLE:
if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
return true;
else
return false;
default:
break;
}
if (dongle_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
dongle_caps->extendedCapValid == false)
@@ -1911,7 +1932,7 @@ enum dc_status dc_link_validate_mode_timing(
const struct dc_crtc_timing *timing)
{
uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk;
struct dc_dongle_caps *dongle_caps = &link->dpcd_caps.dongle_caps;
struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
/* A hack to avoid failing any modes for EDID override feature on
* topology change such as lower quality cable for DP or different dongle
@@ -1924,7 +1945,7 @@ enum dc_status dc_link_validate_mode_timing(
return DC_EXCEED_DONGLE_CAP;
/* Active Dongle*/
if (!dp_active_dongle_validate_timing(timing, dongle_caps))
if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
return DC_EXCEED_DONGLE_CAP;
switch (stream->signal) {
@@ -1950,10 +1971,10 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
struct dc *core_dc = link->ctx->dc;
struct abm *abm = core_dc->res_pool->abm;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
struct dc_context *dc_ctx = link->ctx;
unsigned int controller_id = 0;
bool use_smooth_brightness = true;
int i;
DC_LOGGER_INIT(link->ctx->logger);
if ((dmcu == NULL) ||
(abm == NULL) ||
@@ -1961,7 +1982,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
return false;
if (stream) {
if (stream->bl_pwm_level == 0)
if (stream->bl_pwm_level == EDP_BACKLIGHT_RAMP_DISABLE_LEVEL)
frame_ramp = 0;
((struct dc_stream_state *)stream)->bl_pwm_level = level;
@@ -2149,8 +2170,8 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
struct fixed31_32 avg_time_slots_per_mtp;
struct fixed31_32 pbn;
struct fixed31_32 pbn_per_slot;
struct dc_context *dc_ctx = link->ctx;
uint8_t i;
DC_LOGGER_INIT(link->ctx->logger);
/* enable_link_dp_mst already check link->enabled_stream_count
* and stream is in link->stream[]. This is called during set mode,
@@ -2178,11 +2199,11 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
link->mst_stream_alloc_table.stream_count);
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
DC_LOG_MST("stream_enc[%d]: 0x%x "
DC_LOG_MST("stream_enc[%d]: %p "
"stream[%d].vcp_id: %d "
"stream[%d].slot_count: %d\n",
i,
link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
i,
link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
i,
@@ -2229,7 +2250,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
struct fixed31_32 avg_time_slots_per_mtp = dal_fixed31_32_from_int(0);
uint8_t i;
bool mst_mode = (link->type == dc_connection_mst_branch);
struct dc_context *dc_ctx = link->ctx;
DC_LOGGER_INIT(link->ctx->logger);
/* deallocate_mst_payload is called before disable link. When mode or
* disable/enable monitor, new stream is created which is not in link
@@ -2268,11 +2289,11 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
link->mst_stream_alloc_table.stream_count);
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
DC_LOG_MST("stream_enc[%d]: 0x%x "
DC_LOG_MST("stream_enc[%d]: %p "
"stream[%d].vcp_id: %d "
"stream[%d].slot_count: %d\n",
i,
link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
(void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
i,
link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
i,
@@ -2302,8 +2323,8 @@ void core_link_enable_stream(
struct pipe_ctx *pipe_ctx)
{
struct dc *core_dc = pipe_ctx->stream->ctx->dc;
struct dc_context *dc_ctx = pipe_ctx->stream->ctx;
enum dc_status status;
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
/* eDP lit up by bios already, no need to enable again. */
if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

10
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
Parādīt failu

@@ -629,13 +629,14 @@ bool dal_ddc_service_query_ddc_data(
return ret;
}
ssize_t dal_ddc_service_read_dpcd_data(
enum ddc_result dal_ddc_service_read_dpcd_data(
struct ddc_service *ddc,
bool i2c,
enum i2c_mot_mode mot,
uint32_t address,
uint8_t *data,
uint32_t len)
uint32_t len,
uint32_t *read)
{
struct aux_payload read_payload = {
.i2c_over_aux = i2c,
@@ -652,6 +653,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
.mot = mot
};
*read = 0;
if (len > DEFAULT_AUX_MAX_DATA_SIZE) {
BREAK_TO_DEBUGGER();
return DDC_RESULT_FAILED_INVALID_OPERATION;
@@ -661,7 +664,8 @@ ssize_t dal_ddc_service_read_dpcd_data(
ddc->ctx->i2caux,
ddc->ddc_pin,
&command)) {
return (ssize_t)command.payloads->length;
*read = command.payloads->length;
return DDC_RESULT_SUCESSFULL;
}
return DDC_RESULT_FAILED_OPERATION;

30
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
Parādīt failu

@@ -1378,8 +1378,8 @@ static uint32_t bandwidth_in_kbps_from_timing(
{
uint32_t bits_per_channel = 0;
uint32_t kbps;
switch (timing->display_color_depth) {
switch (timing->display_color_depth) {
case COLOR_DEPTH_666:
bits_per_channel = 6;
break;
@@ -1401,14 +1401,20 @@ static uint32_t bandwidth_in_kbps_from_timing(
default:
break;
}
ASSERT(bits_per_channel != 0);
kbps = timing->pix_clk_khz;
kbps *= bits_per_channel;
if (timing->flags.Y_ONLY != 1)
if (timing->flags.Y_ONLY != 1) {
/*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
kbps *= 3;
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
kbps /= 2;
else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
kbps = kbps * 2 / 3;
}
return kbps;
@@ -2278,6 +2284,8 @@ static bool retrieve_link_cap(struct dc_link *link)
union edp_configuration_cap edp_config_cap;
union dp_downstream_port_present ds_port = { 0 };
enum dc_status status = DC_ERROR_UNEXPECTED;
uint32_t read_dpcd_retry_cnt = 3;
int i;
memset(dpcd_data, '\0', sizeof(dpcd_data));
memset(&down_strm_port_count,
@@ -2285,11 +2293,15 @@ static bool retrieve_link_cap(struct dc_link *link)
memset(&edp_config_cap, '\0',
sizeof(union edp_configuration_cap));
status = core_link_read_dpcd(
link,
DP_DPCD_REV,
dpcd_data,
sizeof(dpcd_data));
for (i = 0; i < read_dpcd_retry_cnt; i++) {
status = core_link_read_dpcd(
link,
DP_DPCD_REV,
dpcd_data,
sizeof(dpcd_data));
if (status == DC_OK)
break;
}
if (status != DC_OK) {
dm_error("%s: Read dpcd data failed.\n", __func__);
@@ -2376,6 +2388,10 @@ bool detect_dp_sink_caps(struct dc_link *link)
void detect_edp_sink_caps(struct dc_link *link)
{
retrieve_link_cap(link);
if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)
link->reported_link_cap.link_rate = LINK_RATE_HIGH2;
link->verified_link_cap = link->reported_link_cap;
}

272
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
Parādīt failu

@@ -45,8 +45,9 @@
#include "dcn10/dcn10_resource.h"
#endif
#include "dce120/dce120_resource.h"
#define DC_LOGGER \
ctx->logger
#define DC_LOGGER_INIT(logger)
enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
{
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
@@ -78,6 +79,10 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
dc_version = DCE_VERSION_11_2;
}
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
dc_version = DCE_VERSION_11_22;
#endif
break;
case FAMILY_AI:
dc_version = DCE_VERSION_12_0;
@@ -124,6 +129,9 @@ struct resource_pool *dc_create_resource_pool(
num_virtual_links, dc, asic_id);
break;
case DCE_VERSION_11_2:
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
#endif
res_pool = dce112_create_resource_pool(
num_virtual_links, dc);
break;
@@ -835,7 +843,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
struct view recout_skip = { 0 };
bool res = false;
struct dc_context *ctx = pipe_ctx->stream->ctx;
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
/* Important: scaling ratio calculation requires pixel format,
* lb depth calculation requires recout and taps require scaling ratios.
* Inits require viewport, taps, ratios and recout of split pipe
@@ -843,6 +851,9 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
pipe_ctx->plane_state->format);
if (pipe_ctx->stream->timing.flags.INTERLACE)
pipe_ctx->stream->dst.height *= 2;
calculate_scaling_ratios(pipe_ctx);
calculate_viewport(pipe_ctx);
@@ -863,6 +874,8 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
if (pipe_ctx->stream->timing.flags.INTERLACE)
pipe_ctx->plane_res.scl_data.v_active *= 2;
/* Taps calculations */
@@ -908,6 +921,9 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
plane_state->dst_rect.x,
plane_state->dst_rect.y);
if (pipe_ctx->stream->timing.flags.INTERLACE)
pipe_ctx->stream->dst.height /= 2;
return res;
}
@@ -1294,6 +1310,19 @@ bool dc_add_all_planes_for_stream(
}
static bool is_hdr_static_meta_changed(struct dc_stream_state *cur_stream,
struct dc_stream_state *new_stream)
{
if (cur_stream == NULL)
return true;
if (memcmp(&cur_stream->hdr_static_metadata,
&new_stream->hdr_static_metadata,
sizeof(struct dc_info_packet)) != 0)
return true;
return false;
}
static bool is_timing_changed(struct dc_stream_state *cur_stream,
struct dc_stream_state *new_stream)
@@ -1329,6 +1358,9 @@ static bool are_stream_backends_same(
if (is_timing_changed(stream_a, stream_b))
return false;
if (is_hdr_static_meta_changed(stream_a, stream_b))
return false;
return true;
}
@@ -1599,18 +1631,6 @@ enum dc_status dc_remove_stream_from_ctx(
return DC_OK;
}
static void copy_pipe_ctx(
const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx)
{
struct dc_plane_state *plane_state = to_pipe_ctx->plane_state;
struct dc_stream_state *stream = to_pipe_ctx->stream;
*to_pipe_ctx = *from_pipe_ctx;
to_pipe_ctx->stream = stream;
if (plane_state != NULL)
to_pipe_ctx->plane_state = plane_state;
}
static struct dc_stream_state *find_pll_sharable_stream(
struct dc_stream_state *stream_needs_pll,
struct dc_state *context)
@@ -1703,7 +1723,7 @@ enum dc_status resource_map_pool_resources(
pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
#endif
if (pipe_idx < 0)
if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
return DC_NO_CONTROLLER_RESOURCE;
pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
@@ -1752,26 +1772,6 @@ enum dc_status resource_map_pool_resources(
return DC_ERROR_UNEXPECTED;
}
/* first stream in the context is used to populate the rest */
void validate_guaranteed_copy_streams(
struct dc_state *context,
int max_streams)
{
int i;
for (i = 1; i < max_streams; i++) {
context->streams[i] = context->streams[0];
copy_pipe_ctx(&context->res_ctx.pipe_ctx[0],
&context->res_ctx.pipe_ctx[i]);
context->res_ctx.pipe_ctx[i].stream =
context->res_ctx.pipe_ctx[0].stream;
dc_stream_retain(context->streams[i]);
context->stream_count++;
}
}
void dc_resource_state_copy_construct_current(
const struct dc *dc,
struct dc_state *dst_ctx)
@@ -1798,9 +1798,9 @@ enum dc_status dc_validate_global_state(
return DC_ERROR_UNEXPECTED;
if (dc->res_pool->funcs->validate_global) {
result = dc->res_pool->funcs->validate_global(dc, new_ctx);
if (result != DC_OK)
return result;
result = dc->res_pool->funcs->validate_global(dc, new_ctx);
if (result != DC_OK)
return result;
}
for (i = 0; i < new_ctx->stream_count; i++) {
@@ -1843,7 +1843,7 @@ enum dc_status dc_validate_global_state(
}
static void patch_gamut_packet_checksum(
struct encoder_info_packet *gamut_packet)
struct dc_info_packet *gamut_packet)
{
/* For gamut we recalc checksum */
if (gamut_packet->valid) {
@@ -1862,12 +1862,11 @@ static void patch_gamut_packet_checksum(
}
static void set_avi_info_frame(
struct encoder_info_packet *info_packet,
struct dc_info_packet *info_packet,
struct pipe_ctx *pipe_ctx)
{
struct dc_stream_state *stream = pipe_ctx->stream;
enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
struct info_frame info_frame = { {0} };
uint32_t pixel_encoding = 0;
enum scanning_type scan_type = SCANNING_TYPE_NODATA;
enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
@@ -1877,22 +1876,24 @@ static void set_avi_info_frame(
unsigned int cn0_cn1_value = 0;
uint8_t *check_sum = NULL;
uint8_t byte_index = 0;
union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi;
union hdmi_info_packet hdmi_info;
union display_content_support support = {0};
unsigned int vic = pipe_ctx->stream->timing.vic;
enum dc_timing_3d_format format;
memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
color_space = pipe_ctx->stream->output_color_space;
if (color_space == COLOR_SPACE_UNKNOWN)
color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
/* Initialize header */
hdmi_info->bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
* not be used in HDMI 2.0 (Section 10.1) */
hdmi_info->bits.header.version = 2;
hdmi_info->bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
hdmi_info.bits.header.version = 2;
hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
/*
* IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
@@ -1918,39 +1919,39 @@ static void set_avi_info_frame(
/* Y0_Y1_Y2 : The pixel encoding */
/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
hdmi_info->bits.Y0_Y1_Y2 = pixel_encoding;
hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
/* A0 = 1 Active Format Information valid */
hdmi_info->bits.A0 = ACTIVE_FORMAT_VALID;
hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
/* B0, B1 = 3; Bar info data is valid */
hdmi_info->bits.B0_B1 = BAR_INFO_BOTH_VALID;
hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
hdmi_info->bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
/* S0, S1 : Underscan / Overscan */
/* TODO: un-hardcode scan type */
scan_type = SCANNING_TYPE_UNDERSCAN;
hdmi_info->bits.S0_S1 = scan_type;
hdmi_info.bits.S0_S1 = scan_type;
/* C0, C1 : Colorimetry */
if (color_space == COLOR_SPACE_YCBCR709 ||
color_space == COLOR_SPACE_YCBCR709_LIMITED)
hdmi_info->bits.C0_C1 = COLORIMETRY_ITU709;
hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
else if (color_space == COLOR_SPACE_YCBCR601 ||
color_space == COLOR_SPACE_YCBCR601_LIMITED)
hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601;
hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
else {
hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA;
hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
}
if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
color_space == COLOR_SPACE_2020_YCBCR) {
hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
} else if (color_space == COLOR_SPACE_ADOBERGB) {
hdmi_info->bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
hdmi_info->bits.C0_C1 = COLORIMETRY_EXTENDED;
hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
}
/* TODO: un-hardcode aspect ratio */
@@ -1959,18 +1960,18 @@ static void set_avi_info_frame(
switch (aspect) {
case ASPECT_RATIO_4_3:
case ASPECT_RATIO_16_9:
hdmi_info->bits.M0_M1 = aspect;
hdmi_info.bits.M0_M1 = aspect;
break;
case ASPECT_RATIO_NO_DATA:
case ASPECT_RATIO_64_27:
case ASPECT_RATIO_256_135:
default:
hdmi_info->bits.M0_M1 = 0;
hdmi_info.bits.M0_M1 = 0;
}
/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
hdmi_info->bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
/* TODO: un-hardcode cn0_cn1 and itc */
@@ -2013,8 +2014,8 @@ static void set_avi_info_frame(
}
}
}
hdmi_info->bits.CN0_CN1 = cn0_cn1_value;
hdmi_info->bits.ITC = itc_value;
hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
hdmi_info.bits.ITC = itc_value;
}
/* TODO : We should handle YCC quantization */
@@ -2023,19 +2024,19 @@ static void set_avi_info_frame(
stream->sink->edid_caps.qy_bit == 1) {
if (color_space == COLOR_SPACE_SRGB ||
color_space == COLOR_SPACE_2020_RGB_FULLRANGE) {
hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_FULL_RANGE;
} else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE) {
hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
} else {
hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
}
} else {
hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
hdmi_info->bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
}
///VIC
@@ -2060,51 +2061,49 @@ static void set_avi_info_frame(
break;
}
}
hdmi_info->bits.VIC0_VIC7 = vic;
hdmi_info.bits.VIC0_VIC7 = vic;
/* pixel repetition
* PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
* repetition start from 1 */
hdmi_info->bits.PR0_PR3 = 0;
hdmi_info.bits.PR0_PR3 = 0;
/* Bar Info
* barTop: Line Number of End of Top Bar.
* barBottom: Line Number of Start of Bottom Bar.
* barLeft: Pixel Number of End of Left Bar.
* barRight: Pixel Number of Start of Right Bar. */
hdmi_info->bits.bar_top = stream->timing.v_border_top;
hdmi_info->bits.bar_bottom = (stream->timing.v_total
hdmi_info.bits.bar_top = stream->timing.v_border_top;
hdmi_info.bits.bar_bottom = (stream->timing.v_total
- stream->timing.v_border_bottom + 1);
hdmi_info->bits.bar_left = stream->timing.h_border_left;
hdmi_info->bits.bar_right = (stream->timing.h_total
hdmi_info.bits.bar_left = stream->timing.h_border_left;
hdmi_info.bits.bar_right = (stream->timing.h_total
- stream->timing.h_border_right + 1);
/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0];
check_sum = &hdmi_info.packet_raw_data.sb[0];
*check_sum = HDMI_INFOFRAME_TYPE_AVI + HDMI_AVI_INFOFRAME_SIZE + 2;
for (byte_index = 1; byte_index <= HDMI_AVI_INFOFRAME_SIZE; byte_index++)
*check_sum += hdmi_info->packet_raw_data.sb[byte_index];
*check_sum += hdmi_info.packet_raw_data.sb[byte_index];
/* one byte complement */
*check_sum = (uint8_t) (0x100 - *check_sum);
/* Store in hw_path_mode */
info_packet->hb0 = hdmi_info->packet_raw_data.hb0;
info_packet->hb1 = hdmi_info->packet_raw_data.hb1;
info_packet->hb2 = hdmi_info->packet_raw_data.hb2;
info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
for (byte_index = 0; byte_index < sizeof(info_frame.avi_info_packet.
info_packet_hdmi.packet_raw_data.sb); byte_index++)
info_packet->sb[byte_index] = info_frame.avi_info_packet.
info_packet_hdmi.packet_raw_data.sb[byte_index];
for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
info_packet->valid = true;
}
static void set_vendor_info_packet(
struct encoder_info_packet *info_packet,
struct dc_info_packet *info_packet,
struct dc_stream_state *stream)
{
uint32_t length = 0;
@@ -2217,7 +2216,7 @@ static void set_vendor_info_packet(
}
static void set_spd_info_packet(
struct encoder_info_packet *info_packet,
struct dc_info_packet *info_packet,
struct dc_stream_state *stream)
{
/* SPD info packet for FreeSync */
@@ -2338,104 +2337,19 @@ static void set_spd_info_packet(
}
static void set_hdr_static_info_packet(
struct encoder_info_packet *info_packet,
struct dc_info_packet *info_packet,
struct dc_stream_state *stream)
{
uint16_t i = 0;
enum signal_type signal = stream->signal;
uint32_t data;
/* HDR Static Metadata info packet for HDR10 */
if (!stream->hdr_static_metadata.hdr_supported)
if (!stream->hdr_static_metadata.valid)
return;
if (dc_is_hdmi_signal(signal)) {
info_packet->valid = true;
info_packet->hb0 = 0x87;
info_packet->hb1 = 0x01;
info_packet->hb2 = 0x1A;
i = 1;
} else if (dc_is_dp_signal(signal)) {
info_packet->valid = true;
info_packet->hb0 = 0x00;
info_packet->hb1 = 0x87;
info_packet->hb2 = 0x1D;
info_packet->hb3 = (0x13 << 2);
i = 2;
}
data = stream->hdr_static_metadata.is_hdr;
info_packet->sb[i++] = data ? 0x02 : 0x00;
info_packet->sb[i++] = 0x00;
data = stream->hdr_static_metadata.chromaticity_green_x / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.chromaticity_green_y / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.chromaticity_blue_x / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.chromaticity_blue_y / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.chromaticity_red_x / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.chromaticity_red_y / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.chromaticity_white_point_x / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.chromaticity_white_point_y / 2;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.max_luminance;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.min_luminance;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.maximum_content_light_level;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
data = stream->hdr_static_metadata.maximum_frame_average_light_level;
info_packet->sb[i++] = data & 0xFF;
info_packet->sb[i++] = (data & 0xFF00) >> 8;
if (dc_is_hdmi_signal(signal)) {
uint32_t checksum = 0;
checksum += info_packet->hb0;
checksum += info_packet->hb1;
checksum += info_packet->hb2;
for (i = 1; i <= info_packet->hb2; i++)
checksum += info_packet->sb[i];
info_packet->sb[0] = 0x100 - checksum;
} else if (dc_is_dp_signal(signal)) {
info_packet->sb[0] = 0x01;
info_packet->sb[1] = 0x1A;
}
*info_packet = stream->hdr_static_metadata;
}
static void set_vsc_info_packet(
struct encoder_info_packet *info_packet,
struct dc_info_packet *info_packet,
struct dc_stream_state *stream)
{
unsigned int vscPacketRevision = 0;
@@ -2650,6 +2564,8 @@ bool pipe_need_reprogram(
if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
return true;
if (is_hdr_static_meta_changed(pipe_ctx_old->stream, pipe_ctx->stream))
return true;
return false;
}

24
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
Parādīt failu

@@ -101,14 +101,16 @@ static void construct(struct dc_stream_state *stream,
stream->status.link = stream->sink->link;
update_stream_signal(stream);
stream->out_transfer_func = dc_create_transfer_func();
stream->out_transfer_func->type = TF_TYPE_BYPASS;
}
static void destruct(struct dc_stream_state *stream)
{
dc_sink_release(stream->sink);
if (stream->out_transfer_func != NULL) {
dc_transfer_func_release(
stream->out_transfer_func);
dc_transfer_func_release(stream->out_transfer_func);
stream->out_transfer_func = NULL;
}
}
@@ -176,6 +178,7 @@ bool dc_stream_set_cursor_attributes(
int i;
struct dc *core_dc;
struct resource_context *res_ctx;
struct pipe_ctx *pipe_to_program = NULL;
if (NULL == stream) {
dm_error("DC: dc_stream is NULL!\n");
@@ -203,9 +206,17 @@ bool dc_stream_set_cursor_attributes(
if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
continue;
if (!pipe_to_program) {
pipe_to_program = pipe_ctx;
core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
}
core_dc->hwss.set_cursor_attribute(pipe_ctx);
}
if (pipe_to_program)
core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
return true;
}
@@ -216,6 +227,7 @@ bool dc_stream_set_cursor_position(
int i;
struct dc *core_dc;
struct resource_context *res_ctx;
struct pipe_ctx *pipe_to_program = NULL;
if (NULL == stream) {
dm_error("DC: dc_stream is NULL!\n");
@@ -241,9 +253,17 @@ bool dc_stream_set_cursor_position(
!pipe_ctx->plane_res.ipp)
continue;
if (!pipe_to_program) {
pipe_to_program = pipe_ctx;
core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, true);
}
core_dc->hwss.set_cursor_position(pipe_ctx);
}
if (pipe_to_program)
core_dc->hwss.pipe_control_lock(core_dc, pipe_to_program, false);
return true;
}

22
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
Parādīt failu

@@ -38,6 +38,12 @@
static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state)
{
plane_state->ctx = ctx;
plane_state->gamma_correction = dc_create_gamma();
plane_state->gamma_correction->is_identity = true;
plane_state->in_transfer_func = dc_create_transfer_func();
plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
}
static void destruct(struct dc_plane_state *plane_state)
@@ -66,8 +72,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc)
{
struct dc *core_dc = dc;
struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state),
GFP_KERNEL);
struct dc_plane_state *plane_state = kvzalloc(sizeof(*plane_state),
GFP_KERNEL);
if (NULL == plane_state)
return NULL;
@@ -120,7 +126,7 @@ static void dc_plane_state_free(struct kref *kref)
{
struct dc_plane_state *plane_state = container_of(kref, struct dc_plane_state, refcount);
destruct(plane_state);
kfree(plane_state);
kvfree(plane_state);
}
void dc_plane_state_release(struct dc_plane_state *plane_state)
@@ -136,7 +142,7 @@ void dc_gamma_retain(struct dc_gamma *gamma)
static void dc_gamma_free(struct kref *kref)
{
struct dc_gamma *gamma = container_of(kref, struct dc_gamma, refcount);
kfree(gamma);
kvfree(gamma);
}
void dc_gamma_release(struct dc_gamma **gamma)
@@ -147,7 +153,7 @@ void dc_gamma_release(struct dc_gamma **gamma)
struct dc_gamma *dc_create_gamma(void)
{
struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL);
struct dc_gamma *gamma = kvzalloc(sizeof(*gamma), GFP_KERNEL);
if (gamma == NULL)
goto alloc_fail;
@@ -167,7 +173,7 @@ void dc_transfer_func_retain(struct dc_transfer_func *tf)
static void dc_transfer_func_free(struct kref *kref)
{
struct dc_transfer_func *tf = container_of(kref, struct dc_transfer_func, refcount);
kfree(tf);
kvfree(tf);
}
void dc_transfer_func_release(struct dc_transfer_func *tf)
@@ -175,9 +181,9 @@ void dc_transfer_func_release(struct dc_transfer_func *tf)
kref_put(&tf->refcount, dc_transfer_func_free);
}
struct dc_transfer_func *dc_create_transfer_func(void)
struct dc_transfer_func *dc_create_transfer_func()
{
struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL);
struct dc_transfer_func *tf = kvzalloc(sizeof(*tf), GFP_KERNEL);
if (tf == NULL)
goto alloc_fail;

30
drivers/gpu/drm/amd/display/dc/dc.h
Parādīt failu

@@ -38,7 +38,7 @@
#include "inc/compressor.h"
#include "dml/display_mode_lib.h"
#define DC_VER "3.1.38"
#define DC_VER "3.1.44"
#define MAX_SURFACES 3
#define MAX_STREAMS 6
@@ -202,6 +202,7 @@ struct dc_debug {
bool timing_trace;
bool clock_trace;
bool validation_trace;
bool bandwidth_calcs_trace;
/* stutter efficiency related */
bool disable_stutter;
@@ -332,20 +333,6 @@ enum {
TRANSFER_FUNC_POINTS = 1025
};
// Moved here from color module for linux
enum color_transfer_func {
transfer_func_unknown,
transfer_func_srgb,
transfer_func_bt709,
transfer_func_pq2084,
transfer_func_pq2084_interim,
transfer_func_linear_0_1,
transfer_func_linear_0_125,
transfer_func_dolbyvision,
transfer_func_gamma_22,
transfer_func_gamma_26
};
struct dc_hdr_static_metadata {
/* display chromaticities and white point in units of 0.00001 */
unsigned int chromaticity_green_x;
@@ -361,9 +348,6 @@ struct dc_hdr_static_metadata {
uint32_t max_luminance;
uint32_t maximum_content_light_level;
uint32_t maximum_frame_average_light_level;
bool hdr_supported;
bool is_hdr;
};
enum dc_transfer_func_type {
@@ -419,7 +403,6 @@ union surface_update_flags {
/* Medium updates */
uint32_t dcc_change:1;
uint32_t color_space_change:1;
uint32_t input_tf_change:1;
uint32_t horizontal_mirror_change:1;
uint32_t per_pixel_alpha_change:1;
uint32_t rotation_change:1;
@@ -428,6 +411,7 @@ union surface_update_flags {
uint32_t position_change:1;
uint32_t in_transfer_func_change:1;
uint32_t input_csc_change:1;
uint32_t coeff_reduction_change:1;
uint32_t output_tf_change:1;
uint32_t pixel_format_change:1;
@@ -460,7 +444,7 @@ struct dc_plane_state {
struct dc_gamma *gamma_correction;
struct dc_transfer_func *in_transfer_func;
struct dc_bias_and_scale *bias_and_scale;
struct csc_transform input_csc_color_matrix;
struct dc_csc_transform input_csc_color_matrix;
struct fixed31_32 coeff_reduction_factor;
uint32_t sdr_white_level;
@@ -468,7 +452,6 @@ struct dc_plane_state {
struct dc_hdr_static_metadata hdr_static_ctx;
enum dc_color_space color_space;
enum color_transfer_func input_tf;
enum surface_pixel_format format;
enum dc_rotation_angle rotation;
@@ -498,7 +481,6 @@ struct dc_plane_info {
enum dc_rotation_angle rotation;
enum plane_stereo_format stereo_format;
enum dc_color_space color_space;
enum color_transfer_func input_tf;
unsigned int sdr_white_level;
bool horizontal_mirror;
bool visible;
@@ -525,10 +507,9 @@ struct dc_surface_update {
* null means no updates
*/
struct dc_gamma *gamma;
enum color_transfer_func color_input_tf;
struct dc_transfer_func *in_transfer_func;
struct csc_transform *input_csc_color_matrix;
struct dc_csc_transform *input_csc_color_matrix;
struct fixed31_32 *coeff_reduction_factor;
};
@@ -699,6 +680,7 @@ struct dc_cursor {
struct dc_cursor_attributes attributes;
};
/*******************************************************************************
* Interrupt interfaces
******************************************************************************/

59
drivers/gpu/drm/amd/display/dc/dc_helper.c
Parādīt failu

@@ -117,6 +117,65 @@ uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
return reg_val;
}
uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
uint8_t shift6, uint32_t mask6, uint32_t *field_value6)
{
uint32_t reg_val = dm_read_reg(ctx, addr);
*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
return reg_val;
}
uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
uint8_t shift7, uint32_t mask7, uint32_t *field_value7)
{
uint32_t reg_val = dm_read_reg(ctx, addr);
*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
return reg_val;
}
uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
uint8_t shift8, uint32_t mask8, uint32_t *field_value8)
{
uint32_t reg_val = dm_read_reg(ctx, addr);
*field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1);
*field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2);
*field_value3 = get_reg_field_value_ex(reg_val, mask3, shift3);
*field_value4 = get_reg_field_value_ex(reg_val, mask4, shift4);
*field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5);
*field_value6 = get_reg_field_value_ex(reg_val, mask6, shift6);
*field_value7 = get_reg_field_value_ex(reg_val, mask7, shift7);
*field_value8 = get_reg_field_value_ex(reg_val, mask8, shift8);
return reg_val;
}
/* note: va version of this is pretty bad idea, since there is a output parameter pass by pointer
* compiler won't be able to check for size match and is prone to stack corruption type of bugs

5
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
Parādīt failu

@@ -423,6 +423,11 @@ enum dc_gamma_type {
GAMMA_CS_TFM_1D = 3,
};
struct dc_csc_transform {
uint16_t matrix[12];
bool enable_adjustment;
};
struct dc_gamma {
struct kref refcount;
enum dc_gamma_type type;

9
drivers/gpu/drm/amd/display/dc/dc_link.h
Parādīt failu

@@ -51,6 +51,14 @@ struct link_mst_stream_allocation_table {
struct link_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
};
struct time_stamp {
uint64_t edp_poweroff;
uint64_t edp_poweron;
};
struct link_trace {
struct time_stamp time_stamp;
};
/*
* A link contains one or more sinks and their connected status.
* The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
@@ -114,6 +122,7 @@ struct dc_link {
struct dc_link_status link_status;
struct link_trace link_trace;
};
const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);

28
drivers/gpu/drm/amd/display/dc/dc_stream.h
Parādīt failu

@@ -58,18 +58,20 @@ struct dc_stream_state {
struct freesync_context freesync_ctx;
struct dc_hdr_static_metadata hdr_static_metadata;
struct dc_info_packet hdr_static_metadata;
struct dc_transfer_func *out_transfer_func;
struct colorspace_transform gamut_remap_matrix;
struct csc_transform csc_color_matrix;
struct dc_csc_transform csc_color_matrix;
enum dc_color_space output_color_space;
enum dc_dither_option dither_option;
enum view_3d_format view_format;
enum color_transfer_func output_tf;
bool ignore_msa_timing_param;
unsigned long long periodic_fn_vsync_delta;
/* TODO: custom INFO packets */
/* TODO: ABM info (DMCU) */
/* PSR info */
@@ -110,9 +112,10 @@ struct dc_stream_update {
struct rect src;
struct rect dst;
struct dc_transfer_func *out_transfer_func;
struct dc_hdr_static_metadata *hdr_static_metadata;
enum color_transfer_func color_output_tf;
struct dc_info_packet *hdr_static_metadata;
unsigned int *abm_level;
unsigned long long *periodic_fn_vsync_delta;
};
bool dc_is_stream_unchanged(
@@ -131,13 +134,6 @@ bool dc_is_stream_scaling_unchanged(
* This does not trigger a flip. No surface address is programmed.
*/
bool dc_commit_planes_to_stream(
struct dc *dc,
struct dc_plane_state **plane_states,
uint8_t new_plane_count,
struct dc_stream_state *dc_stream,
struct dc_state *state);
void dc_commit_updates_for_stream(struct dc *dc,
struct dc_surface_update *srf_updates,
int surface_count,
@@ -208,14 +204,6 @@ bool dc_add_all_planes_for_stream(
enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
/*
* This function takes a stream and checks if it is guaranteed to be supported.
* Guaranteed means that MAX_COFUNC similar streams are supported.
*
* After this call:
* No hardware is programmed for call. Only validation is done.
*/
/*
* Set up streams and links associated to drive sinks
* The streams parameter is an absolute set of all active streams.

15
drivers/gpu/drm/amd/display/dc/dc_types.h
Parādīt failu

@@ -370,12 +370,6 @@ struct dc_csc_adjustments {
struct fixed31_32 hue;
};
enum {
MAX_LANES = 2,
MAX_COFUNC_PATH = 6,
LAYER_INDEX_PRIMARY = -1,
};
enum dpcd_downstream_port_max_bpc {
DOWN_STREAM_MAX_8BPC = 0,
DOWN_STREAM_MAX_10BPC,
@@ -530,6 +524,15 @@ struct vrr_params {
uint32_t frame_counter;
};
struct dc_info_packet {
bool valid;
uint8_t hb0;
uint8_t hb1;
uint8_t hb2;
uint8_t hb3;
uint8_t sb[32];
};
#define DC_PLANE_UPDATE_TIMES_MAX 10
struct dc_plane_flip_time {

9
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
Parādīt failu

@@ -33,8 +33,9 @@
#define CTX \
aud->base.ctx
#define DC_LOGGER \
aud->base.ctx->logger
#define DC_LOGGER_INIT()
#define REG(reg)\
(aud->regs->reg)
@@ -348,8 +349,8 @@ static void set_audio_latency(
void dce_aud_az_enable(struct audio *audio)
{
struct dce_audio *aud = DCE_AUD(audio);
uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
DC_LOGGER_INIT();
set_reg_field_value(value, 1,
AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
@@ -371,7 +372,7 @@ void dce_aud_az_enable(struct audio *audio)
void dce_aud_az_disable(struct audio *audio)
{
uint32_t value;
struct dce_audio *aud = DCE_AUD(audio);
DC_LOGGER_INIT();
value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
set_reg_field_value(value, 1,

17
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
Parādīt failu

@@ -41,8 +41,9 @@
#define CTX \
clk_src->base.ctx
#define DC_LOGGER \
calc_pll_cs->ctx->logger
#define DC_LOGGER_INIT()
#undef FN
#define FN(reg_name, field_name) \
clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
@@ -467,7 +468,7 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
{
uint32_t field = 0;
uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
DC_LOGGER_INIT();
/* Check if reference clock is external (not pcie/xtalin)
* HW Dce80 spec:
* 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB
@@ -557,8 +558,8 @@ static uint32_t dce110_get_pix_clk_dividers(
struct pll_settings *pll_settings)
{
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
DC_LOGGER_INIT();
if (pix_clk_params == NULL || pll_settings == NULL
|| pix_clk_params->requested_pix_clk == 0) {
@@ -589,6 +590,9 @@ static uint32_t dce110_get_pix_clk_dividers(
pll_settings, pix_clk_params);
break;
case DCE_VERSION_11_2:
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
#endif
case DCE_VERSION_12_0:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0:
@@ -978,6 +982,9 @@ static bool dce110_program_pix_clk(
break;
case DCE_VERSION_11_2:
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
#endif
case DCE_VERSION_12_0:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case DCN_VERSION_1_0:
@@ -1054,7 +1061,7 @@ static void get_ss_info_from_atombios(
struct spread_spectrum_info *ss_info_cur;
struct spread_spectrum_data *ss_data_cur;
uint32_t i;
struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
DC_LOGGER_INIT();
if (ss_entries_num == NULL) {
DC_LOG_SYNC(
"Invalid entry !!!\n");

3
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
Parādīt failu

@@ -53,7 +53,8 @@ void dce_pipe_control_lock(struct dc *dc,
struct dce_hwseq *hws = dc->hwseq;
/* Not lock pipe when blank */
if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
if (lock && pipe->stream_res.tg->funcs->is_blanked &&
pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
return;
val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],

6
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
Parādīt failu

@@ -113,6 +113,7 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = {
.connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe,
.enable_hpd = dce110_link_encoder_enable_hpd,
.disable_hpd = dce110_link_encoder_disable_hpd,
.is_dig_enabled = dce110_is_dig_enabled,
.destroy = dce110_link_encoder_destroy
};
@@ -535,8 +536,9 @@ void dce110_psr_program_secondary_packet(struct link_encoder *enc,
DP_SEC_GSP0_PRIORITY, 1);
}
static bool is_dig_enabled(const struct dce110_link_encoder *enc110)
bool dce110_is_dig_enabled(struct link_encoder *enc)
{
struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
uint32_t value;
REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
@@ -1031,7 +1033,7 @@ void dce110_link_encoder_disable_output(
struct bp_transmitter_control cntl = { 0 };
enum bp_result result;
if (!is_dig_enabled(enc110)) {
if (!dce110_is_dig_enabled(enc)) {
/* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
return;
}

2
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
Parādīt failu

@@ -263,4 +263,6 @@ void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
void dce110_psr_program_secondary_packet(struct link_encoder *enc,
unsigned int sdp_transmit_line_num_deadline);
bool dce110_is_dig_enabled(struct link_encoder *enc);
#endif /* __DC_LINK_ENCODER__DCE110_H__ */

103
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
Parādīt failu

@@ -174,6 +174,25 @@ static void program_urgency_watermark(
URGENCY_HIGH_WATERMARK, urgency_high_wm);
}
static void dce120_program_urgency_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
uint32_t urgency_low_wm,
uint32_t urgency_high_wm)
{
REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
URGENCY_WATERMARK_MASK, wm_select);
REG_SET_2(DPG_PIPE_URGENCY_CONTROL, 0,
URGENCY_LOW_WATERMARK, urgency_low_wm,
URGENCY_HIGH_WATERMARK, urgency_high_wm);
REG_SET_2(DPG_PIPE_URGENT_LEVEL_CONTROL, 0,
URGENT_LEVEL_LOW_WATERMARK, urgency_low_wm,
URGENT_LEVEL_HIGH_WATERMARK, urgency_high_wm);
}
static void program_nbp_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
@@ -206,6 +225,25 @@ static void program_nbp_watermark(
}
}
static void dce120_program_stutter_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
uint32_t stutter_mark,
uint32_t stutter_entry)
{
REG_UPDATE(DPG_WATERMARK_MASK_CONTROL,
STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select);
if (REG(DPG_PIPE_STUTTER_CONTROL2))
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL2,
STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark,
STUTTER_ENTER_SELF_REFRESH_WATERMARK, stutter_entry);
else
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark,
STUTTER_ENTER_SELF_REFRESH_WATERMARK, stutter_entry);
}
static void program_stutter_watermark(
struct dce_mem_input *dce_mi,
uint32_t wm_select,
@@ -225,7 +263,8 @@ static void program_stutter_watermark(
static void dce_mi_program_display_marks(
struct mem_input *mi,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
struct dce_watermarks stutter_exit,
struct dce_watermarks stutter_enter,
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
{
@@ -243,13 +282,14 @@ static void dce_mi_program_display_marks(
program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */
program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */
program_stutter_watermark(dce_mi, 2, stutter.a_mark); /* set a */
program_stutter_watermark(dce_mi, 1, stutter.d_mark); /* set d */
program_stutter_watermark(dce_mi, 2, stutter_exit.a_mark); /* set a */
program_stutter_watermark(dce_mi, 1, stutter_exit.d_mark); /* set d */
}
static void dce120_mi_program_display_marks(struct mem_input *mi,
static void dce112_mi_program_display_marks(struct mem_input *mi,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
struct dce_watermarks stutter_exit,
struct dce_watermarks stutter_entry,
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
{
@@ -273,10 +313,43 @@ static void dce120_mi_program_display_marks(struct mem_input *mi,
program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
program_stutter_watermark(dce_mi, 0, stutter.a_mark); /* set a */
program_stutter_watermark(dce_mi, 1, stutter.b_mark); /* set b */
program_stutter_watermark(dce_mi, 2, stutter.c_mark); /* set c */
program_stutter_watermark(dce_mi, 3, stutter.d_mark); /* set d */
program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark); /* set a */
program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark); /* set b */
program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark); /* set c */
program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark); /* set d */
}
static void dce120_mi_program_display_marks(struct mem_input *mi,
struct dce_watermarks nbp,
struct dce_watermarks stutter_exit,
struct dce_watermarks stutter_entry,
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
{
struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);
uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;
dce120_program_urgency_watermark(dce_mi, 0, /* set a */
urgent.a_mark, total_dest_line_time_ns);
dce120_program_urgency_watermark(dce_mi, 1, /* set b */
urgent.b_mark, total_dest_line_time_ns);
dce120_program_urgency_watermark(dce_mi, 2, /* set c */
urgent.c_mark, total_dest_line_time_ns);
dce120_program_urgency_watermark(dce_mi, 3, /* set d */
urgent.d_mark, total_dest_line_time_ns);
REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,
STUTTER_ENABLE, stutter_en,
STUTTER_IGNORE_FBC, 1);
program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */
program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */
program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */
program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */
dce120_program_stutter_watermark(dce_mi, 0, stutter_exit.a_mark, stutter_entry.a_mark); /* set a */
dce120_program_stutter_watermark(dce_mi, 1, stutter_exit.b_mark, stutter_entry.b_mark); /* set b */
dce120_program_stutter_watermark(dce_mi, 2, stutter_exit.c_mark, stutter_entry.c_mark); /* set c */
dce120_program_stutter_watermark(dce_mi, 3, stutter_exit.d_mark, stutter_entry.d_mark); /* set d */
}
static void program_tiling(
@@ -694,6 +767,18 @@ void dce112_mem_input_construct(
const struct dce_mem_input_registers *regs,
const struct dce_mem_input_shift *mi_shift,
const struct dce_mem_input_mask *mi_mask)
{
dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
dce_mi->base.funcs->mem_input_program_display_marks = dce112_mi_program_display_marks;
}
void dce120_mem_input_construct(
struct dce_mem_input *dce_mi,
struct dc_context *ctx,
int inst,
const struct dce_mem_input_registers *regs,
const struct dce_mem_input_shift *mi_shift,
const struct dce_mem_input_mask *mi_mask)
{
dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);
dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks;

17
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
Parādīt failu

@@ -106,6 +106,7 @@ struct dce_mem_input_registers {
uint32_t DPG_PIPE_ARBITRATION_CONTROL1;
uint32_t DPG_WATERMARK_MASK_CONTROL;
uint32_t DPG_PIPE_URGENCY_CONTROL;
uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL;
uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL;
uint32_t DPG_PIPE_LOW_POWER_CONTROL;
uint32_t DPG_PIPE_STUTTER_CONTROL;
@@ -213,6 +214,11 @@ struct dce_mem_input_registers {
#define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\
SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\
SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\
SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\
SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\
SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\
SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\
SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\
SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\
@@ -286,6 +292,8 @@ struct dce_mem_input_registers {
type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \
type URGENCY_LOW_WATERMARK; \
type URGENCY_HIGH_WATERMARK; \
type URGENT_LEVEL_LOW_WATERMARK;\
type URGENT_LEVEL_HIGH_WATERMARK;\
type NB_PSTATE_CHANGE_ENABLE; \
type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \
type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \
@@ -297,6 +305,7 @@ struct dce_mem_input_registers {
type STUTTER_ENABLE; \
type STUTTER_IGNORE_FBC; \
type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \
type STUTTER_ENTER_SELF_REFRESH_WATERMARK; \
type DMIF_BUFFERS_ALLOCATED; \
type DMIF_BUFFERS_ALLOCATION_COMPLETED; \
type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\
@@ -344,4 +353,12 @@ void dce112_mem_input_construct(
const struct dce_mem_input_shift *mi_shift,
const struct dce_mem_input_mask *mi_mask);
void dce120_mem_input_construct(
struct dce_mem_input *dce_mi,
struct dc_context *ctx,
int inst,
const struct dce_mem_input_registers *regs,
const struct dce_mem_input_shift *mi_shift,
const struct dce_mem_input_mask *mi_mask);
#endif /*__DCE_MEM_INPUT_H__*/

68
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
Parādīt failu

@@ -26,27 +26,10 @@
#include "dc_bios_types.h"
#include "dce_stream_encoder.h"
#include "reg_helper.h"
#include "hw_shared.h"
#define DC_LOGGER \
enc110->base.ctx->logger
enum DP_PIXEL_ENCODING {
DP_PIXEL_ENCODING_RGB444 = 0x00000000,
DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
DP_PIXEL_ENCODING_RESERVED = 0x00000006,
};
enum DP_COMPONENT_DEPTH {
DP_COMPONENT_DEPTH_6BPC = 0x00000000,
DP_COMPONENT_DEPTH_8BPC = 0x00000001,
DP_COMPONENT_DEPTH_10BPC = 0x00000002,
DP_COMPONENT_DEPTH_12BPC = 0x00000003,
DP_COMPONENT_DEPTH_16BPC = 0x00000004,
DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
};
#define REG(reg)\
@@ -80,7 +63,7 @@ enum {
static void dce110_update_generic_info_packet(
struct dce110_stream_encoder *enc110,
uint32_t packet_index,
const struct encoder_info_packet *info_packet)
const struct dc_info_packet *info_packet)
{
uint32_t regval;
/* TODOFPGA Figure out a proper number for max_retries polling for lock
@@ -196,7 +179,7 @@ static void dce110_update_generic_info_packet(
static void dce110_update_hdmi_info_packet(
struct dce110_stream_encoder *enc110,
uint32_t packet_index,
const struct encoder_info_packet *info_packet)
const struct dc_info_packet *info_packet)
{
uint32_t cont, send, line;
@@ -314,11 +297,11 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
switch (crtc_timing->pixel_encoding) {
case PIXEL_ENCODING_YCBCR422:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR422);
DP_PIXEL_ENCODING_TYPE_YCBCR422);
break;
case PIXEL_ENCODING_YCBCR444:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR444);
DP_PIXEL_ENCODING_TYPE_YCBCR444);
if (crtc_timing->flags.Y_ONLY)
if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
@@ -326,7 +309,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
* Color depth of Y-only could be
* 8, 10, 12, 16 bits */
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_Y_ONLY);
DP_PIXEL_ENCODING_TYPE_Y_ONLY);
/* Note: DP_MSA_MISC1 bit 7 is the indicator
* of Y-only mode.
* This bit is set in HW if register
@@ -334,7 +317,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
case PIXEL_ENCODING_YCBCR420:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_YCBCR420);
DP_PIXEL_ENCODING_TYPE_YCBCR420);
if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
@@ -345,7 +328,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
DP_PIXEL_ENCODING_RGB444);
DP_PIXEL_ENCODING_TYPE_RGB444);
break;
}
@@ -363,20 +346,20 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
break;
case COLOR_DEPTH_888:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_8BPC);
DP_COMPONENT_PIXEL_DEPTH_8BPC);
break;
case COLOR_DEPTH_101010:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_10BPC);
DP_COMPONENT_PIXEL_DEPTH_10BPC);
break;
case COLOR_DEPTH_121212:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_12BPC);
DP_COMPONENT_PIXEL_DEPTH_12BPC);
break;
default:
REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
DP_COMPONENT_DEPTH_6BPC);
DP_COMPONENT_PIXEL_DEPTH_6BPC);
break;
}
@@ -836,7 +819,7 @@ static void dce110_stream_encoder_update_dp_info_packets(
const struct encoder_info_frame *info_frame)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL);
uint32_t value = 0;
if (info_frame->vsc.valid)
dce110_update_generic_info_packet(
@@ -870,6 +853,7 @@ static void dce110_stream_encoder_update_dp_info_packets(
* Therefore we need to enable master bit
* if at least on of the fields is not 0
*/
value = REG_READ(DP_SEC_CNTL);
if (value)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
}
@@ -879,7 +863,7 @@ static void dce110_stream_encoder_stop_dp_info_packets(
{
/* stop generic packets on DP */
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL);
uint32_t value = 0;
if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
REG_SET_7(DP_SEC_CNTL, 0,
@@ -892,25 +876,10 @@ static void dce110_stream_encoder_stop_dp_info_packets(
DP_SEC_STREAM_ENABLE, 0);
}
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (enc110->se_mask->DP_SEC_GSP7_ENABLE) {
REG_SET_10(DP_SEC_CNTL, 0,
DP_SEC_GSP0_ENABLE, 0,
DP_SEC_GSP1_ENABLE, 0,
DP_SEC_GSP2_ENABLE, 0,
DP_SEC_GSP3_ENABLE, 0,
DP_SEC_GSP4_ENABLE, 0,
DP_SEC_GSP5_ENABLE, 0,
DP_SEC_GSP6_ENABLE, 0,
DP_SEC_GSP7_ENABLE, 0,
DP_SEC_MPG_ENABLE, 0,
DP_SEC_STREAM_ENABLE, 0);
}
#endif
/* this register shared with audio info frame.
* therefore we need to keep master enabled
* if at least one of the fields is not 0 */
value = REG_READ(DP_SEC_CNTL);
if (value)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
@@ -1513,7 +1482,7 @@ static void dce110_se_disable_dp_audio(
struct stream_encoder *enc)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t value = REG_READ(DP_SEC_CNTL);
uint32_t value = 0;
/* Disable Audio packets */
REG_UPDATE_5(DP_SEC_CNTL,
@@ -1525,6 +1494,7 @@ static void dce110_se_disable_dp_audio(
/* This register shared with encoder info frame. Therefore we need to
keep master enabled if at least on of the fields is not 0 */
value = REG_READ(DP_SEC_CNTL);
if (value != 0)
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);

33
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
Parādīt failu

@@ -733,38 +733,6 @@ enum dc_status dce100_add_stream_to_ctx(
return result;
}
enum dc_status dce100_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = dc_stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, dc_stream);
if (result == DC_OK)
result = resource_map_clock_resources(dc, context, dc_stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, dc_stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK)
if (!dce100_validate_bandwidth(dc, context))
result = DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
static void dce100_destroy_resource_pool(struct resource_pool **pool)
{
struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
@@ -786,7 +754,6 @@ enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, s
static const struct resource_funcs dce100_res_pool_funcs = {
.destroy = dce100_destroy_resource_pool,
.link_enc_create = dce100_link_encoder_create,
.validate_guaranteed = dce100_validate_guaranteed,
.validate_bandwidth = dce100_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce100_add_stream_to_ctx,

95
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
Parādīt failu

@@ -70,8 +70,9 @@
#define CTX \
hws->ctx
#define DC_LOGGER \
ctx->logger
#define DC_LOGGER_INIT()
#define REG(reg)\
hws->regs->reg
@@ -279,7 +280,9 @@ dce110_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
build_prescale_params(&prescale_params, plane_state);
ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
if (plane_state->gamma_correction &&
!plane_state->gamma_correction->is_identity &&
dce_use_lut(plane_state->format))
ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
if (tf == NULL) {
@@ -851,6 +854,28 @@ void hwss_edp_power_control(
if (power_up != is_panel_powered_on(hwseq)) {
/* Send VBIOS command to prompt eDP panel power */
if (power_up) {
unsigned long long current_ts = dm_get_timestamp(ctx);
unsigned long long duration_in_ms =
dm_get_elapse_time_in_ns(
ctx,
current_ts,
div64_u64(link->link_trace.time_stamp.edp_poweroff, 1000000));
unsigned long long wait_time_ms = 0;
/* max 500ms from LCDVDD off to on */
if (link->link_trace.time_stamp.edp_poweroff == 0)
wait_time_ms = 500;
else if (duration_in_ms < 500)
wait_time_ms = 500 - duration_in_ms;
if (wait_time_ms) {
msleep(wait_time_ms);
dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
__func__, wait_time_ms);
}
}
DC_LOG_HW_RESUME_S3(
"%s: Panel Power action: %s\n",
@@ -864,9 +889,14 @@ void hwss_edp_power_control(
cntl.coherent = false;
cntl.lanes_number = LANE_COUNT_FOUR;
cntl.hpd_sel = link->link_enc->hpd_source;
bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
if (!power_up)
/*save driver power off time stamp*/
link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
else
link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
if (bp_result != BP_RESULT_OK)
DC_LOG_ERROR(
"%s: Panel Power bp_result: %d\n",
@@ -1011,7 +1041,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
link->dc->hwss.edp_backlight_control(link, true);
stream->bl_pwm_level = 0;
stream->bl_pwm_level = EDP_BACKLIGHT_RAMP_DISABLE_LEVEL;
}
}
void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
@@ -1203,7 +1233,7 @@ static void program_scaler(const struct dc *dc,
&pipe_ctx->plane_res.scl_data);
}
static enum dc_status dce110_prog_pixclk_crtc_otg(
static enum dc_status dce110_enable_stream_timing(
struct pipe_ctx *pipe_ctx,
struct dc_state *context,
struct dc *dc)
@@ -1269,7 +1299,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
pipe_ctx[pipe_ctx->pipe_idx];
/* */
dc->hwss.prog_pixclk_crtc_otg(pipe_ctx, context, dc);
dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
/* FPGA does not program backend */
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
@@ -1441,6 +1471,17 @@ static void disable_vga_and_power_gate_all_controllers(
}
}
static struct dc_link *get_link_for_edp(struct dc *dc)
{
int i;
for (i = 0; i < dc->link_count; i++) {
if (dc->links[i]->connector_signal == SIGNAL_TYPE_EDP)
return dc->links[i];
}
return NULL;
}
static struct dc_link *get_link_for_edp_not_in_use(
struct dc *dc,
struct dc_state *context)
@@ -1475,20 +1516,21 @@ static struct dc_link *get_link_for_edp_not_in_use(
*/
void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
{
struct dc_bios *dcb = dc->ctx->dc_bios;
/* vbios already light up eDP, so we can leverage vbios and skip eDP
* programming
*/
bool can_eDP_fast_boot_optimize =
(dcb->funcs->get_vga_enabled_displays(dc->ctx->dc_bios) == ATOM_DISPLAY_LCD1_ACTIVE);
/* if OS doesn't light up eDP and eDP link is available, we want to disable */
struct dc_link *edp_link_to_turnoff = NULL;
struct dc_link *edp_link = get_link_for_edp(dc);
bool can_eDP_fast_boot_optimize = false;
if (edp_link) {
can_eDP_fast_boot_optimize =
edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
}
if (can_eDP_fast_boot_optimize) {
edp_link_to_turnoff = get_link_for_edp_not_in_use(dc, context);
/* if OS doesn't light up eDP and eDP link is available, we want to disable
* If resume from S4/S5, should optimization.
*/
if (!edp_link_to_turnoff)
dc->apply_edp_fast_boot_optimization = true;
}
@@ -1544,6 +1586,7 @@ static void dce110_set_displaymarks(
pipe_ctx->plane_res.mi,
context->bw.dce.nbp_state_change_wm_ns[num_pipes],
context->bw.dce.stutter_exit_wm_ns[num_pipes],
context->bw.dce.stutter_entry_wm_ns[num_pipes],
context->bw.dce.urgent_wm_ns[num_pipes],
total_dest_line_time_ns);
if (i == underlay_idx) {
@@ -1569,6 +1612,7 @@ static void set_safe_displaymarks(
MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
struct dce_watermarks nbp_marks = {
SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
struct dce_watermarks min_marks = { 0, 0, 0, 0};
for (i = 0; i < MAX_PIPES; i++) {
if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
@@ -1578,6 +1622,7 @@ static void set_safe_displaymarks(
res_ctx->pipe_ctx[i].plane_res.mi,
nbp_marks,
max_marks,
min_marks,
max_marks,
MAX_WATERMARK);
@@ -1803,6 +1848,9 @@ static bool should_enable_fbc(struct dc *dc,
}
}
/* Pipe context should be found */
ASSERT(pipe_ctx);
/* Only supports eDP */
if (pipe_ctx->stream->sink->link->connector_signal != SIGNAL_TYPE_EDP)
return false;
@@ -2699,8 +2747,11 @@ static void dce110_program_front_end_for_pipe(
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
struct xfm_grph_csc_adjustment adjust;
struct out_csc_color_matrix tbl_entry;
#if defined(CONFIG_DRM_AMD_DC_FBC)
unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
#endif
unsigned int i;
struct dc_context *ctx = dc->ctx;
DC_LOGGER_INIT();
memset(&tbl_entry, 0, sizeof(tbl_entry));
if (dc->current_state)
@@ -2740,7 +2791,9 @@ static void dce110_program_front_end_for_pipe(
program_scaler(dc, pipe_ctx);
#if defined(CONFIG_DRM_AMD_DC_FBC)
if (dc->fbc_compressor && old_pipe->stream) {
/* fbc not applicable on Underlay pipe */
if (dc->fbc_compressor && old_pipe->stream &&
pipe_ctx->pipe_idx != underlay_idx) {
if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
else
@@ -2776,13 +2829,13 @@ static void dce110_program_front_end_for_pipe(
dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
DC_LOG_SURFACE(
"Pipe:%d 0x%x: addr hi:0x%x, "
"Pipe:%d %p: addr hi:0x%x, "
"addr low:0x%x, "
"src: %d, %d, %d,"
" %d; dst: %d, %d, %d, %d;"
"clip: %d, %d, %d, %d\n",
pipe_ctx->pipe_idx,
pipe_ctx->plane_state,
(void *) pipe_ctx->plane_state,
pipe_ctx->plane_state->address.grph.addr.high_part,
pipe_ctx->plane_state->address.grph.addr.low_part,
pipe_ctx->plane_state->src_rect.x,
@@ -2993,7 +3046,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.get_position = get_position,
.set_static_screen_control = set_static_screen_control,
.reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
.prog_pixclk_crtc_otg = dce110_prog_pixclk_crtc_otg,
.enable_stream_timing = dce110_enable_stream_timing,
.setup_stereo = NULL,
.set_avmute = dce110_set_avmute,
.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,

1
drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
Parādīt failu

@@ -923,6 +923,7 @@ void dce_mem_input_v_program_display_marks(
struct mem_input *mem_input,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
struct dce_watermarks stutter_enter,
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns)
{

33
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
Parādīt failu

@@ -930,38 +930,6 @@ static enum dc_status dce110_add_stream_to_ctx(
return result;
}
static enum dc_status dce110_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = dc_stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, dc_stream);
if (result == DC_OK)
result = resource_map_clock_resources(dc, context, dc_stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, dc_stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK)
if (!dce110_validate_bandwidth(dc, context))
result = DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
static struct pipe_ctx *dce110_acquire_underlay(
struct dc_state *context,
const struct resource_pool *pool,
@@ -1036,7 +1004,6 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce110_res_pool_funcs = {
.destroy = dce110_destroy_resource_pool,
.link_enc_create = dce110_link_encoder_create,
.validate_guaranteed = dce110_validate_guaranteed,
.validate_bandwidth = dce110_validate_bandwidth,
.validate_plane = dce110_validate_plane,
.acquire_idle_pipe_for_layer = dce110_acquire_underlay,

16
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
Parādīt failu

@@ -431,14 +431,6 @@ void dce110_timing_generator_set_drr(
0,
CRTC_V_TOTAL_CONTROL,
CRTC_SET_V_TOTAL_MIN_MASK);
set_reg_field_value(v_total_min,
0,
CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN);
set_reg_field_value(v_total_max,
0,
CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX);
set_reg_field_value(v_total_cntl,
0,
CRTC_V_TOTAL_CONTROL,
@@ -447,6 +439,14 @@ void dce110_timing_generator_set_drr(
0,
CRTC_V_TOTAL_CONTROL,
CRTC_V_TOTAL_MAX_SEL);
set_reg_field_value(v_total_min,
0,
CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN);
set_reg_field_value(v_total_max,
0,
CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX);
set_reg_field_value(v_total_cntl,
0,
CRTC_V_TOTAL_CONTROL,

7
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
Parādīt failu

@@ -648,12 +648,6 @@ static void dce110_timing_generator_v_disable_vga(
return;
}
static bool dce110_tg_v_is_blanked(struct timing_generator *tg)
{
/* Signal comes from the primary pipe, underlay is never blanked. */
return false;
}
/** ********************************************************************************************
*
* DCE11 Timing Generator Constructor / Destructor
@@ -670,7 +664,6 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = {
.set_early_control = dce110_timing_generator_v_set_early_control,
.wait_for_state = dce110_timing_generator_v_wait_for_state,
.set_blank = dce110_timing_generator_v_set_blank,
.is_blanked = dce110_tg_v_is_blanked,
.set_colors = dce110_timing_generator_v_set_colors,
.set_overscan_blank_color =
dce110_timing_generator_v_set_overscan_color_black,

35
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
Parādīt failu

@@ -430,7 +430,7 @@ static struct stream_encoder *dce112_stream_encoder_create(
if (!enc110)
return NULL;
dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
&stream_enc_regs[eng_id],
&se_shift, &se_mask);
@@ -867,38 +867,6 @@ enum dc_status dce112_add_stream_to_ctx(
return result;
}
enum dc_status dce112_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, stream);
if (result == DC_OK)
result = resource_map_phy_clock_resources(dc, context, stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK)
if (!dce112_validate_bandwidth(dc, context))
result = DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
enum dc_status dce112_validate_global(
struct dc *dc,
struct dc_state *context)
@@ -921,7 +889,6 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce112_res_pool_funcs = {
.destroy = dce112_destroy_resource_pool,
.link_enc_create = dce112_link_encoder_create,
.validate_guaranteed = dce112_validate_guaranteed,
.validate_bandwidth = dce112_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce112_add_stream_to_ctx,

5
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h
Parādīt failu

@@ -42,11 +42,6 @@ enum dc_status dce112_validate_with_context(
struct dc_state *context,
struct dc_state *old_context);
enum dc_status dce112_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context);
bool dce112_validate_bandwidth(
struct dc *dc,
struct dc_state *context);

3
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
Parādīt failu

@@ -652,7 +652,7 @@ static struct mem_input *dce120_mem_input_create(
return NULL;
}
dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
dce120_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
return &dce_mi->base;
}
@@ -684,7 +684,6 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce120_res_pool_funcs = {
.destroy = dce120_destroy_resource_pool,
.link_enc_create = dce120_link_encoder_create,
.validate_guaranteed = dce112_validate_guaranteed,
.validate_bandwidth = dce112_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce112_add_stream_to_ctx

12
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
Parādīt failu

@@ -570,18 +570,18 @@ void dce120_timing_generator_set_drr(
0x180);
} else {
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN, 0);
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX, 0);
CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN, 0);
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX, 0);
CRTC_REG_UPDATE(
CRTC0_CRTC_STATIC_SCREEN_CONTROL,
CRTC_STATIC_SCREEN_EVENT_MASK,

49
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
Parādīt failu

@@ -691,23 +691,6 @@ static void destruct(struct dce110_resource_pool *pool)
}
}
static enum dc_status build_mapped_resource(
const struct dc *dc,
struct dc_state *context,
struct dc_stream_state *stream)
{
struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
if (!pipe_ctx)
return DC_ERROR_UNEXPECTED;
dce110_resource_build_pipe_hw_param(pipe_ctx);
resource_build_info_frame(pipe_ctx);
return DC_OK;
}
bool dce80_validate_bandwidth(
struct dc *dc,
struct dc_state *context)
@@ -749,37 +732,6 @@ enum dc_status dce80_validate_global(
return DC_OK;
}
enum dc_status dce80_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = dc_stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, dc_stream);
if (result == DC_OK)
result = resource_map_clock_resources(dc, context, dc_stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, dc_stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK)
result = dce80_validate_bandwidth(dc, context);
return result;
}
static void dce80_destroy_resource_pool(struct resource_pool **pool)
{
struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
@@ -792,7 +744,6 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool)
static const struct resource_funcs dce80_res_pool_funcs = {
.destroy = dce80_destroy_resource_pool,
.link_enc_create = dce80_link_encoder_create,
.validate_guaranteed = dce80_validate_guaranteed,
.validate_bandwidth = dce80_validate_bandwidth,
.validate_plane = dce100_validate_plane,
.add_stream_to_ctx = dce100_add_stream_to_ctx,

2
drivers/gpu/drm/amd/display/dc/dcn10/Makefile
Parādīt failu

@@ -26,7 +26,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
dcn10_hubp.o dcn10_mpc.o \
dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
dcn10_hubbub.o
dcn10_hubbub.o dcn10_stream_encoder.o
AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))

12
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
Parādīt failu

@@ -367,15 +367,15 @@ bool cm_helper_translate_curve_to_hw_format(
lut_params->hw_points_num = hw_points;
i = 1;
for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
k = 0;
for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
if (seg_distr[k] != -1) {
lut_params->arr_curve_points[k].segments_num =
seg_distr[k];
lut_params->arr_curve_points[i].offset =
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
}
i++;
k++;
}
if (seg_distr[k] != -1)
@@ -529,15 +529,15 @@ bool cm_helper_translate_curve_to_degamma_hw_format(
lut_params->hw_points_num = hw_points;
i = 1;
for (k = 0; k < MAX_REGIONS_NUMBER && i < MAX_REGIONS_NUMBER; k++) {
k = 0;
for (i = 1; i < MAX_REGIONS_NUMBER; i++) {
if (seg_distr[k] != -1) {
lut_params->arr_curve_points[k].segments_num =
seg_distr[k];
lut_params->arr_curve_points[i].offset =
lut_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
}
i++;
k++;
}
if (seg_distr[k] != -1)

36
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
Parādīt failu

@@ -98,6 +98,30 @@ enum gamut_remap_select {
GAMUT_REMAP_COMB_COEFF
};
void dpp_read_state(struct dpp *dpp_base,
struct dcn_dpp_state *s)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
REG_GET(CM_IGAM_CONTROL,
CM_IGAM_LUT_MODE, &s->igam_lut_mode);
REG_GET(CM_IGAM_CONTROL,
CM_IGAM_INPUT_FORMAT, &s->igam_input_format);
REG_GET(CM_DGAM_CONTROL,
CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
REG_GET(CM_RGAM_CONTROL,
CM_RGAM_LUT_MODE, &s->rgam_lut_mode);
REG_GET(CM_GAMUT_REMAP_CONTROL,
CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
}
/* Program gamut remap in bypass mode */
void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
{
@@ -121,6 +145,13 @@ bool dpp_get_optimal_number_of_taps(
else
pixel_width = scl_data->viewport.width;
/* Some ASICs does not support FP16 scaling, so we reject modes require this*/
if (scl_data->viewport.width != scl_data->h_active &&
scl_data->viewport.height != scl_data->v_active &&
dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
scl_data->format == PIXEL_FORMAT_FP16)
return false;
/* TODO: add lb check */
/* No support for programming ratio of 4, drop to 3.99999.. */
@@ -257,7 +288,7 @@ void dpp1_cnv_setup (
struct dpp *dpp_base,
enum surface_pixel_format format,
enum expansion_mode mode,
struct csc_transform input_csc_color_matrix,
struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space)
{
uint32_t pixel_format;
@@ -416,7 +447,7 @@ void dpp1_set_cursor_position(
if (src_x_offset >= (int)param->viewport_width)
cur_en = 0; /* not visible beyond right edge*/
if (src_x_offset + (int)width < 0)
if (src_x_offset + (int)width <= 0)
cur_en = 0; /* not visible beyond left edge*/
REG_UPDATE(CURSOR0_CONTROL,
@@ -443,6 +474,7 @@ void dpp1_dppclk_control(
}
static const struct dpp_funcs dcn10_dpp_funcs = {
.dpp_read_state = dpp_read_state,
.dpp_reset = dpp_reset,
.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
.dpp_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps,

76
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
Parādīt failu

@@ -44,6 +44,10 @@
#define TF_REG_LIST_DCN(id) \
SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
@@ -108,6 +112,8 @@
SRI(CM_DGAM_LUT_DATA, CM, id), \
SRI(CM_CONTROL, CM, id), \
SRI(CM_DGAM_CONTROL, CM, id), \
SRI(CM_TEST_DEBUG_INDEX, CM, id), \
SRI(CM_TEST_DEBUG_DATA, CM, id), \
SRI(FORMAT_CONTROL, CNVC_CFG, id), \
SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
@@ -175,6 +181,14 @@
TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
@@ -300,6 +314,7 @@
TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
@@ -417,6 +432,41 @@
TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
/*
*
DCN1 CM debug status register definition
register :ID9_CM_STATUS do
implement_ref :cm
map to: :cmdebugind, at: j
width 32
disclosure NEVER
field :ID9_VUPDATE_CFG, [0], R
field :ID9_IGAM_LUT_MODE, [2..1], R
field :ID9_BNS_BYPASS, [3], R
field :ID9_ICSC_MODE, [5..4], R
field :ID9_DGAM_LUT_MODE, [8..6], R
field :ID9_HDR_BYPASS, [9], R
field :ID9_GAMUT_REMAP_MODE, [11..10], R
field :ID9_RGAM_LUT_MODE, [14..12], R
#1 free bit
field :ID9_OCSC_MODE, [18..16], R
field :ID9_DENORM_MODE, [21..19], R
field :ID9_ROUND_TRUNC_MODE, [25..22], R
field :ID9_DITHER_EN, [26], R
field :ID9_DITHER_MODE, [28..27], R
end
*/
#define TF_DEBUG_REG_LIST_SH_DCN10 \
.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, \
.CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16
#define TF_DEBUG_REG_LIST_MASK_DCN10 \
.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, \
.CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x70000
#define TF_REG_FIELD_LIST(type) \
type EXT_OVERSCAN_LEFT; \
type EXT_OVERSCAN_RIGHT; \
@@ -486,6 +536,14 @@
type CM_GAMUT_REMAP_MODE; \
type CM_GAMUT_REMAP_C11; \
type CM_GAMUT_REMAP_C12; \
type CM_GAMUT_REMAP_C13; \
type CM_GAMUT_REMAP_C14; \
type CM_GAMUT_REMAP_C21; \
type CM_GAMUT_REMAP_C22; \
type CM_GAMUT_REMAP_C23; \
type CM_GAMUT_REMAP_C24; \
type CM_GAMUT_REMAP_C31; \
type CM_GAMUT_REMAP_C32; \
type CM_GAMUT_REMAP_C33; \
type CM_GAMUT_REMAP_C34; \
type CM_COMA_C11; \
@@ -1010,6 +1068,9 @@
type CUR0_EXPANSION_MODE; \
type CUR0_ENABLE; \
type CM_BYPASS; \
type CM_TEST_DEBUG_INDEX; \
type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
type CM_TEST_DEBUG_DATA_ID9_OCSC_MODE;\
type FORMAT_CONTROL__ALPHA_EN; \
type CUR0_COLOR0; \
type CUR0_COLOR1; \
@@ -1054,6 +1115,10 @@ struct dcn_dpp_mask {
uint32_t RECOUT_SIZE; \
uint32_t CM_GAMUT_REMAP_CONTROL; \
uint32_t CM_GAMUT_REMAP_C11_C12; \
uint32_t CM_GAMUT_REMAP_C13_C14; \
uint32_t CM_GAMUT_REMAP_C21_C22; \
uint32_t CM_GAMUT_REMAP_C23_C24; \
uint32_t CM_GAMUT_REMAP_C31_C32; \
uint32_t CM_GAMUT_REMAP_C33_C34; \
uint32_t CM_COMA_C11_C12; \
uint32_t CM_COMA_C33_C34; \
@@ -1255,6 +1320,8 @@ struct dcn_dpp_mask {
uint32_t CM_IGAM_LUT_RW_CONTROL; \
uint32_t CM_IGAM_LUT_RW_INDEX; \
uint32_t CM_IGAM_LUT_SEQ_COLOR; \
uint32_t CM_TEST_DEBUG_INDEX; \
uint32_t CM_TEST_DEBUG_DATA; \
uint32_t FORMAT_CONTROL; \
uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
uint32_t CURSOR_CONTROL; \
@@ -1289,8 +1356,8 @@ struct dcn10_dpp {
enum dcn10_input_csc_select {
INPUT_CSC_SELECT_BYPASS = 0,
INPUT_CSC_SELECT_ICSC,
INPUT_CSC_SELECT_COMA
INPUT_CSC_SELECT_ICSC = 1,
INPUT_CSC_SELECT_COMA = 2
};
void dpp1_set_cursor_attributes(
@@ -1364,6 +1431,9 @@ bool dpp_get_optimal_number_of_taps(
struct scaler_data *scl_data,
const struct scaling_taps *in_taps);
void dpp_read_state(struct dpp *dpp_base,
struct dcn_dpp_state *s);
void dpp_reset(struct dpp *dpp_base);
void dpp1_cm_program_regamma_lut(
@@ -1408,7 +1478,7 @@ void dpp1_cnv_setup (
struct dpp *dpp_base,
enum surface_pixel_format format,
enum expansion_mode mode,
struct csc_transform input_csc_color_matrix,
struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space);
void dpp1_full_bypass(struct dpp *dpp_base);

90
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
Parādīt failu

@@ -216,41 +216,55 @@ static void dpp1_cm_program_color_matrix(
struct dcn10_dpp *dpp,
const uint16_t *regval)
{
uint32_t mode;
uint32_t ocsc_mode;
uint32_t cur_mode;
struct color_matrices_reg gam_regs;
REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
if (regval == NULL) {
BREAK_TO_DEBUGGER();
return;
}
mode = 4;
/* determine which CSC matrix (ocsc or comb) we are using
* currently. select the alternate set to double buffer
* the CSC update so CSC is updated on frame boundary
*/
REG_SET(CM_TEST_DEBUG_INDEX, 0,
CM_TEST_DEBUG_INDEX, 9);
REG_GET(CM_TEST_DEBUG_DATA,
CM_TEST_DEBUG_DATA_ID9_OCSC_MODE, &cur_mode);
if (cur_mode != 4)
ocsc_mode = 4;
else
ocsc_mode = 5;
gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;
gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;
gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;
gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;
if (mode == 4) {
if (ocsc_mode == 4) {
gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
cm_helper_program_color_matrices(
dpp->base.ctx,
regval,
&gam_regs);
} else {
gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
cm_helper_program_color_matrices(
dpp->base.ctx,
regval,
&gam_regs);
}
cm_helper_program_color_matrices(
dpp->base.ctx,
regval,
&gam_regs);
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
}
void dpp1_cm_set_output_csc_default(
@@ -260,15 +274,14 @@ void dpp1_cm_set_output_csc_default(
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
const uint16_t *regval = NULL;
int arr_size;
uint32_t ocsc_mode = 4;
regval = find_color_matrix(colorspace, &arr_size);
if (regval == NULL) {
BREAK_TO_DEBUGGER();
return;
}
dpp1_cm_program_color_matrix(dpp, regval);
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
}
static void dpp1_cm_get_reg_field(
@@ -329,9 +342,8 @@ void dpp1_cm_set_output_csc_adjustment(
const uint16_t *regval)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
uint32_t ocsc_mode = 4;
dpp1_cm_program_color_matrix(dpp, regval);
REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
}
void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,
@@ -437,17 +449,18 @@ void dpp1_cm_program_regamma_lutb_settings(
void dpp1_program_input_csc(
struct dpp *dpp_base,
enum dc_color_space color_space,
enum dcn10_input_csc_select select,
enum dcn10_input_csc_select input_select,
const struct out_csc_color_matrix *tbl_entry)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
int i;
int arr_size = sizeof(dcn10_input_csc_matrix)/sizeof(struct dcn10_input_csc_matrix);
const uint16_t *regval = NULL;
uint32_t selection = 1;
uint32_t cur_select = 0;
enum dcn10_input_csc_select select;
struct color_matrices_reg gam_regs;
if (select == INPUT_CSC_SELECT_BYPASS) {
if (input_select == INPUT_CSC_SELECT_BYPASS) {
REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0);
return;
}
@@ -467,36 +480,45 @@ void dpp1_program_input_csc(
regval = tbl_entry->regval;
}
if (select == INPUT_CSC_SELECT_COMA)
selection = 2;
REG_SET(CM_ICSC_CONTROL, 0,
CM_ICSC_MODE, selection);
/* determine which CSC matrix (icsc or coma) we are using
* currently. select the alternate set to double buffer
* the CSC update so CSC is updated on frame boundary
*/
REG_SET(CM_TEST_DEBUG_INDEX, 0,
CM_TEST_DEBUG_INDEX, 9);
REG_GET(CM_TEST_DEBUG_DATA,
CM_TEST_DEBUG_DATA_ID9_ICSC_MODE, &cur_select);
if (cur_select != INPUT_CSC_SELECT_ICSC)
select = INPUT_CSC_SELECT_ICSC;
else
select = INPUT_CSC_SELECT_COMA;
gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;
gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;
gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;
gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;
if (select == INPUT_CSC_SELECT_ICSC) {
gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12);
gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34);
cm_helper_program_color_matrices(
dpp->base.ctx,
regval,
&gam_regs);
} else {
gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
cm_helper_program_color_matrices(
dpp->base.ctx,
regval,
&gam_regs);
}
cm_helper_program_color_matrices(
dpp->base.ctx,
regval,
&gam_regs);
REG_SET(CM_ICSC_CONTROL, 0,
CM_ICSC_MODE, select);
}
//keep here for now, decide multi dce support later

221
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
Parādīt failu

@@ -476,8 +476,227 @@ void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub)
DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);
}
static bool hubbub1_dcc_support_swizzle(
enum swizzle_mode_values swizzle,
unsigned int bytes_per_element,
enum segment_order *segment_order_horz,
enum segment_order *segment_order_vert)
{
bool standard_swizzle = false;
bool display_swizzle = false;
switch (swizzle) {
case DC_SW_4KB_S:
case DC_SW_64KB_S:
case DC_SW_VAR_S:
case DC_SW_4KB_S_X:
case DC_SW_64KB_S_X:
case DC_SW_VAR_S_X:
standard_swizzle = true;
break;
case DC_SW_4KB_D:
case DC_SW_64KB_D:
case DC_SW_VAR_D:
case DC_SW_4KB_D_X:
case DC_SW_64KB_D_X:
case DC_SW_VAR_D_X:
display_swizzle = true;
break;
default:
break;
}
if (bytes_per_element == 1 && standard_swizzle) {
*segment_order_horz = segment_order__contiguous;
*segment_order_vert = segment_order__na;
return true;
}
if (bytes_per_element == 2 && standard_swizzle) {
*segment_order_horz = segment_order__non_contiguous;
*segment_order_vert = segment_order__contiguous;
return true;
}
if (bytes_per_element == 4 && standard_swizzle) {
*segment_order_horz = segment_order__non_contiguous;
*segment_order_vert = segment_order__contiguous;
return true;
}
if (bytes_per_element == 8 && standard_swizzle) {
*segment_order_horz = segment_order__na;
*segment_order_vert = segment_order__contiguous;
return true;
}
if (bytes_per_element == 8 && display_swizzle) {
*segment_order_horz = segment_order__contiguous;
*segment_order_vert = segment_order__non_contiguous;
return true;
}
return false;
}
static bool hubbub1_dcc_support_pixel_format(
enum surface_pixel_format format,
unsigned int *bytes_per_element)
{
/* DML: get_bytes_per_element */
switch (format) {
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
*bytes_per_element = 2;
return true;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
*bytes_per_element = 4;
return true;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
*bytes_per_element = 8;
return true;
default:
return false;
}
}
static void hubbub1_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
unsigned int bytes_per_element)
{
/* copied from DML. might want to refactor DML to leverage from DML */
/* DML : get_blk256_size */
if (bytes_per_element == 1) {
*blk256_width = 16;
*blk256_height = 16;
} else if (bytes_per_element == 2) {
*blk256_width = 16;
*blk256_height = 8;
} else if (bytes_per_element == 4) {
*blk256_width = 8;
*blk256_height = 8;
} else if (bytes_per_element == 8) {
*blk256_width = 8;
*blk256_height = 4;
}
}
static void hubbub1_det_request_size(
unsigned int height,
unsigned int width,
unsigned int bpe,
bool *req128_horz_wc,
bool *req128_vert_wc)
{
unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
unsigned int blk256_height = 0;
unsigned int blk256_width = 0;
unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
hubbub1_get_blk256_size(&blk256_width, &blk256_height, bpe);
swath_bytes_horz_wc = height * blk256_height * bpe;
swath_bytes_vert_wc = width * blk256_width * bpe;
*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
false : /* full 256B request */
true; /* half 128b request */
*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
false : /* full 256B request */
true; /* half 128b request */
}
static bool hubbub1_get_dcc_compression_cap(struct hubbub *hubbub,
const struct dc_dcc_surface_param *input,
struct dc_surface_dcc_cap *output)
{
struct dc *dc = hubbub->ctx->dc;
/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
enum dcc_control dcc_control;
unsigned int bpe;
enum segment_order segment_order_horz, segment_order_vert;
bool req128_horz_wc, req128_vert_wc;
memset(output, 0, sizeof(*output));
if (dc->debug.disable_dcc == DCC_DISABLE)
return false;
if (!hubbub->funcs->dcc_support_pixel_format(input->format, &bpe))
return false;
if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
&segment_order_horz, &segment_order_vert))
return false;
hubbub1_det_request_size(input->surface_size.height, input->surface_size.width,
bpe, &req128_horz_wc, &req128_vert_wc);
if (!req128_horz_wc && !req128_vert_wc) {
dcc_control = dcc_control__256_256_xxx;
} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
if (!req128_horz_wc)
dcc_control = dcc_control__256_256_xxx;
else if (segment_order_horz == segment_order__contiguous)
dcc_control = dcc_control__128_128_xxx;
else
dcc_control = dcc_control__256_64_64;
} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
if (!req128_vert_wc)
dcc_control = dcc_control__256_256_xxx;
else if (segment_order_vert == segment_order__contiguous)
dcc_control = dcc_control__128_128_xxx;
else
dcc_control = dcc_control__256_64_64;
} else {
if ((req128_horz_wc &&
segment_order_horz == segment_order__non_contiguous) ||
(req128_vert_wc &&
segment_order_vert == segment_order__non_contiguous))
/* access_dir not known, must use most constraining */
dcc_control = dcc_control__256_64_64;
else
/* reg128 is true for either horz and vert
* but segment_order is contiguous
*/
dcc_control = dcc_control__128_128_xxx;
}
if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
dcc_control != dcc_control__256_256_xxx)
return false;
switch (dcc_control) {
case dcc_control__256_256_xxx:
output->grph.rgb.max_uncompressed_blk_size = 256;
output->grph.rgb.max_compressed_blk_size = 256;
output->grph.rgb.independent_64b_blks = false;
break;
case dcc_control__128_128_xxx:
output->grph.rgb.max_uncompressed_blk_size = 128;
output->grph.rgb.max_compressed_blk_size = 128;
output->grph.rgb.independent_64b_blks = false;
break;
case dcc_control__256_64_64:
output->grph.rgb.max_uncompressed_blk_size = 256;
output->grph.rgb.max_compressed_blk_size = 64;
output->grph.rgb.independent_64b_blks = true;
break;
}
output->capable = true;
output->const_color_support = false;
return true;
}
static const struct hubbub_funcs hubbub1_funcs = {
.update_dchub = hubbub1_update_dchub
.update_dchub = hubbub1_update_dchub,
.dcc_support_swizzle = hubbub1_dcc_support_swizzle,
.dcc_support_pixel_format = hubbub1_dcc_support_pixel_format,
.get_dcc_compression_cap = hubbub1_get_dcc_compression_cap,
};
void hubbub1_construct(struct hubbub *hubbub,

7
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
Parādīt failu

@@ -27,6 +27,7 @@
#define __DC_HUBBUB_DCN10_H__
#include "core_types.h"
#include "dchubbub.h"
#define HUBHUB_REG_LIST_DCN()\
SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
@@ -173,12 +174,6 @@ struct dcn_hubbub_wm {
struct dcn_hubbub_wm_set sets[4];
};
struct hubbub_funcs {
void (*update_dchub)(
struct hubbub *hubbub,
struct dchub_init_data *dh_data);
};
struct hubbub {
const struct hubbub_funcs *funcs;
struct dc_context *ctx;

187
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
Parādīt failu

@@ -146,6 +146,9 @@ void hubp1_program_size_and_rotation(
* 444 or 420 luma
*/
if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
ASSERT(plane_size->video.chroma_pitch != 0);
/* Chroma pitch zero can cause system hang! */
pitch = plane_size->video.luma_pitch - 1;
meta_pitch = dcc->video.meta_pitch_l - 1;
pitch_c = plane_size->video.chroma_pitch - 1;
@@ -535,11 +538,13 @@ void hubp1_program_deadline(
REG_SET(VBLANK_PARAMETERS_3, 0,
REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
REG_SET(NOM_PARAMETERS_0, 0,
DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
if (REG(NOM_PARAMETERS_0))
REG_SET(NOM_PARAMETERS_0, 0,
DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
REG_SET(NOM_PARAMETERS_1, 0,
REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
if (REG(NOM_PARAMETERS_1))
REG_SET(NOM_PARAMETERS_1, 0,
REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
REG_SET(NOM_PARAMETERS_4, 0,
DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
@@ -568,11 +573,13 @@ void hubp1_program_deadline(
REG_SET(VBLANK_PARAMETERS_4, 0,
REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
REG_SET(NOM_PARAMETERS_2, 0,
DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
if (REG(NOM_PARAMETERS_2))
REG_SET(NOM_PARAMETERS_2, 0,
DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
REG_SET(NOM_PARAMETERS_3, 0,
REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
if (REG(NOM_PARAMETERS_3))
REG_SET(NOM_PARAMETERS_3, 0,
REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
REG_SET(NOM_PARAMETERS_6, 0,
DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
@@ -609,6 +616,13 @@ void hubp1_program_deadline(
REG_SET(DCN_SURF1_TTU_CNTL1, 0,
REFCYC_PER_REQ_DELIVERY_PRE,
ttu_attr->refcyc_per_req_delivery_pre_c);
REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
REG_SET(DCN_CUR0_TTU_CNTL1, 0,
REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
}
static void hubp1_setup(
@@ -752,9 +766,159 @@ void min_set_viewport(
PRI_VIEWPORT_Y_START_C, viewport_c->y);
}
void hubp1_read_state(struct dcn10_hubp *hubp1,
struct dcn_hubp_state *s)
void hubp1_read_state(struct hubp *hubp)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
struct dcn_hubp_state *s = &hubp1->state;
struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
/* Requester */
REG_GET(HUBPRET_CONTROL,
DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
REG_GET_4(DCN_EXPANSION_MODE,
DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
/* DLG - Per hubp */
REG_GET_2(BLANK_OFFSET_0,
REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
REG_GET(BLANK_OFFSET_1,
MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
REG_GET(DST_DIMENSIONS,
REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
REG_GET_2(DST_AFTER_SCALER,
REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
if (REG(PREFETCH_SETTINS))
REG_GET_2(PREFETCH_SETTINS,
DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
else
REG_GET_2(PREFETCH_SETTINGS,
DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
REG_GET_2(VBLANK_PARAMETERS_0,
DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
REG_GET(REF_FREQ_TO_PIX_FREQ,
REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
/* DLG - Per luma/chroma */
REG_GET(VBLANK_PARAMETERS_1,
REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
REG_GET(VBLANK_PARAMETERS_3,
REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
if (REG(NOM_PARAMETERS_0))
REG_GET(NOM_PARAMETERS_0,
DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
if (REG(NOM_PARAMETERS_1))
REG_GET(NOM_PARAMETERS_1,
REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
REG_GET(NOM_PARAMETERS_4,
DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
REG_GET(NOM_PARAMETERS_5,
REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
REG_GET_2(PER_LINE_DELIVERY_PRE,
REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
REG_GET_2(PER_LINE_DELIVERY,
REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
if (REG(PREFETCH_SETTINS_C))
REG_GET(PREFETCH_SETTINS_C,
VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
else
REG_GET(PREFETCH_SETTINGS_C,
VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
REG_GET(VBLANK_PARAMETERS_2,
REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
REG_GET(VBLANK_PARAMETERS_4,
REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
if (REG(NOM_PARAMETERS_2))
REG_GET(NOM_PARAMETERS_2,
DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
if (REG(NOM_PARAMETERS_3))
REG_GET(NOM_PARAMETERS_3,
REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
REG_GET(NOM_PARAMETERS_6,
DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
REG_GET(NOM_PARAMETERS_7,
REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
/* TTU - per hubp */
REG_GET_2(DCN_TTU_QOS_WM,
QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
REG_GET_2(DCN_GLOBAL_TTU_CNTL,
MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
/* TTU - per luma/chroma */
/* Assumed surf0 is luma and 1 is chroma */
REG_GET_3(DCN_SURF0_TTU_CNTL0,
REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
REG_GET(DCN_SURF0_TTU_CNTL1,
REFCYC_PER_REQ_DELIVERY_PRE,
&ttu_attr->refcyc_per_req_delivery_pre_l);
REG_GET_3(DCN_SURF1_TTU_CNTL0,
REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
REG_GET(DCN_SURF1_TTU_CNTL1,
REFCYC_PER_REQ_DELIVERY_PRE,
&ttu_attr->refcyc_per_req_delivery_pre_c);
/* Rest of hubp */
REG_GET(DCSURF_SURFACE_CONFIG,
SURFACE_PIXEL_FORMAT, &s->pixel_format);
@@ -897,7 +1061,7 @@ void hubp1_cursor_set_position(
if (src_x_offset >= (int)param->viewport_width)
cur_en = 0; /* not visible beyond right edge*/
if (src_x_offset + (int)hubp->curs_attr.width < 0)
if (src_x_offset + (int)hubp->curs_attr.width <= 0)
cur_en = 0; /* not visible beyond left edge*/
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
@@ -952,6 +1116,7 @@ static struct hubp_funcs dcn10_hubp_funcs = {
.hubp_disconnect = hubp1_disconnect,
.hubp_clk_cntl = hubp1_clk_cntl,
.hubp_vtg_sel = hubp1_vtg_sel,
.hubp_read_state = hubp1_read_state,
};
/*****************************************/

79
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
Parādīt failu

@@ -30,6 +30,7 @@
#define TO_DCN10_HUBP(hubp)\
container_of(hubp, struct dcn10_hubp, base)
/* Register address initialization macro for all ASICs (including those with reduced functionality) */
#define HUBP_REG_LIST_DCN(id)\
SRI(DCHUBP_CNTL, HUBP, id),\
SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
@@ -78,16 +79,12 @@
SRI(REF_FREQ_TO_PIX_FREQ, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_1, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_3, HUBPREQ, id),\
SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
SRI(NOM_PARAMETERS_4, HUBPREQ, id),\
SRI(NOM_PARAMETERS_5, HUBPREQ, id),\
SRI(PER_LINE_DELIVERY_PRE, HUBPREQ, id),\
SRI(PER_LINE_DELIVERY, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_2, HUBPREQ, id),\
SRI(VBLANK_PARAMETERS_4, HUBPREQ, id),\
SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
SRI(NOM_PARAMETERS_6, HUBPREQ, id),\
SRI(NOM_PARAMETERS_7, HUBPREQ, id),\
SRI(DCN_TTU_QOS_WM, HUBPREQ, id),\
@@ -96,11 +93,21 @@
SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\
SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\
SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\
SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\
SRI(DCN_CUR0_TTU_CNTL0, HUBPREQ, id),\
SRI(DCN_CUR0_TTU_CNTL1, HUBPREQ, id),\
SRI(HUBP_CLK_CNTL, HUBP, id)
/* Register address initialization macro for ASICs with VM */
#define HUBP_REG_LIST_DCN_VM(id)\
SRI(NOM_PARAMETERS_0, HUBPREQ, id),\
SRI(NOM_PARAMETERS_1, HUBPREQ, id),\
SRI(NOM_PARAMETERS_2, HUBPREQ, id),\
SRI(NOM_PARAMETERS_3, HUBPREQ, id),\
SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id)
#define HUBP_REG_LIST_DCN10(id)\
HUBP_REG_LIST_DCN(id),\
HUBP_REG_LIST_DCN_VM(id),\
SRI(PREFETCH_SETTINS, HUBPREQ, id),\
SRI(PREFETCH_SETTINS_C, HUBPREQ, id),\
SRI(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, HUBPREQ, id),\
@@ -198,6 +205,8 @@
uint32_t DCN_SURF0_TTU_CNTL1; \
uint32_t DCN_SURF1_TTU_CNTL0; \
uint32_t DCN_SURF1_TTU_CNTL1; \
uint32_t DCN_CUR0_TTU_CNTL0; \
uint32_t DCN_CUR0_TTU_CNTL1; \
uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB; \
uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB; \
uint32_t DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB; \
@@ -237,6 +246,7 @@
#define HUBP_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
/* Mask/shift struct generation macro for all ASICs (including those with reduced functionality) */
#define HUBP_MASK_SH_LIST_DCN(mask_sh)\
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
@@ -335,8 +345,6 @@
HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
@@ -345,8 +353,6 @@
HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
@@ -357,12 +363,24 @@
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
/* Mask/shift struct generation macro for ASICs with VM */
#define HUBP_MASK_SH_LIST_DCN_VM(mask_sh)\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_0, DST_Y_PER_PTE_ROW_NOM_L, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_1, REFCYC_PER_PTE_GROUP_NOM_L, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_2, DST_Y_PER_PTE_ROW_NOM_C, mask_sh),\
HUBP_SF(HUBPREQ0_NOM_PARAMETERS_3, REFCYC_PER_PTE_GROUP_NOM_C, mask_sh),\
HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\
HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\
HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh)
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
HUBP_SF(HUBPREQ0_DCN_CUR0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh)
#define HUBP_MASK_SH_LIST_DCN10(mask_sh)\
HUBP_MASK_SH_LIST_DCN(mask_sh),\
HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, DST_Y_PREFETCH, mask_sh),\
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS, VRATIO_PREFETCH, mask_sh),\
HUBP_SF(HUBPREQ0_PREFETCH_SETTINS_C, VRATIO_PREFETCH_C, mask_sh),\
@@ -601,8 +619,29 @@ struct dcn_mi_mask {
DCN_HUBP_REG_FIELD_LIST(uint32_t);
};
struct dcn_hubp_state {
struct _vcs_dpi_display_dlg_regs_st dlg_attr;
struct _vcs_dpi_display_ttu_regs_st ttu_attr;
struct _vcs_dpi_display_rq_regs_st rq_regs;
uint32_t pixel_format;
uint32_t inuse_addr_hi;
uint32_t viewport_width;
uint32_t viewport_height;
uint32_t rotation_angle;
uint32_t h_mirror_en;
uint32_t sw_mode;
uint32_t dcc_en;
uint32_t blank_en;
uint32_t underflow_status;
uint32_t ttu_disable;
uint32_t min_ttu_vblank;
uint32_t qos_level_low_wm;
uint32_t qos_level_high_wm;
};
struct dcn10_hubp {
struct hubp base;
struct dcn_hubp_state state;
const struct dcn_mi_registers *hubp_regs;
const struct dcn_mi_shift *hubp_shift;
const struct dcn_mi_mask *hubp_mask;
@@ -680,25 +719,7 @@ void dcn10_hubp_construct(
const struct dcn_mi_shift *hubp_shift,
const struct dcn_mi_mask *hubp_mask);
struct dcn_hubp_state {
uint32_t pixel_format;
uint32_t inuse_addr_hi;
uint32_t viewport_width;
uint32_t viewport_height;
uint32_t rotation_angle;
uint32_t h_mirror_en;
uint32_t sw_mode;
uint32_t dcc_en;
uint32_t blank_en;
uint32_t underflow_status;
uint32_t ttu_disable;
uint32_t min_ttu_vblank;
uint32_t qos_level_low_wm;
uint32_t qos_level_high_wm;
};
void hubp1_read_state(struct dcn10_hubp *hubp1,
struct dcn_hubp_state *s);
void hubp1_read_state(struct hubp *hubp);
enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);

286
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
Parādīt failu

@@ -45,8 +45,8 @@
#include "dcn10_hubbub.h"
#include "dcn10_cm_common.h"
#define DC_LOGGER \
ctx->logger
#define DC_LOGGER_INIT(logger)
#define CTX \
hws->ctx
#define REG(reg)\
@@ -56,16 +56,17 @@
#define FN(reg_name, field_name) \
hws->shifts->field_name, hws->masks->field_name
/*print is 17 wide, first two characters are spaces*/
#define DTN_INFO_MICRO_SEC(ref_cycle) \
print_microsec(dc_ctx, ref_cycle)
void print_microsec(struct dc_context *dc_ctx, uint32_t ref_cycle)
{
static const uint32_t ref_clk_mhz = 48;
static const unsigned int frac = 10;
const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clock_inKhz / 1000;
static const unsigned int frac = 1000;
uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
DTN_INFO("%d.%d \t ",
DTN_INFO(" %11d.%03d",
us_x10 / frac,
us_x10 % frac);
}
@@ -92,14 +93,14 @@ void dcn10_log_hubbub_state(struct dc *dc)
hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);
DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "
"sr_enter \t sr_exit \t dram_clk_change \n");
DTN_INFO("HUBBUB WM: data_urgent pte_meta_urgent"
" sr_enter sr_exit dram_clk_change\n");
for (i = 0; i < 4; i++) {
struct dcn_hubbub_wm_set *s;
s = &wm.sets[i];
DTN_INFO("WM_Set[%d]:\t ", s->wm_set);
DTN_INFO("WM_Set[%d]:", s->wm_set);
DTN_INFO_MICRO_SEC(s->data_urgent);
DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
DTN_INFO_MICRO_SEC(s->sr_enter);
@@ -111,6 +112,116 @@ void dcn10_log_hubbub_state(struct dc *dc)
DTN_INFO("\n");
}
static void dcn10_log_hubp_states(struct dc *dc)
{
struct dc_context *dc_ctx = dc->ctx;
struct resource_pool *pool = dc->res_pool;
int i;
DTN_INFO("HUBP: format addr_hi width height"
" rot mir sw_mode dcc_en blank_en ttu_dis underflow"
" min_ttu_vblank qos_low_wm qos_high_wm\n");
for (i = 0; i < pool->pipe_count; i++) {
struct hubp *hubp = pool->hubps[i];
struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
hubp->funcs->hubp_read_state(hubp);
DTN_INFO("[%2d]: %5xh %6xh %5d %6d %2xh %2xh %6xh"
" %6d %8d %7d %8xh",
hubp->inst,
s->pixel_format,
s->inuse_addr_hi,
s->viewport_width,
s->viewport_height,
s->rotation_angle,
s->h_mirror_en,
s->sw_mode,
s->dcc_en,
s->blank_en,
s->ttu_disable,
s->underflow_status);
DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
DTN_INFO("\n");
}
DTN_INFO("\n=========RQ========\n");
DTN_INFO("HUBP: drq_exp_m prq_exp_m mrq_exp_m crq_exp_m plane1_ba L:chunk_s min_chu_s meta_ch_s"
" min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h C:chunk_s min_chu_s meta_ch_s"
" min_m_c_s dpte_gr_s mpte_gr_s swath_hei pte_row_h\n");
for (i = 0; i < pool->pipe_count; i++) {
struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
i, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
}
DTN_INFO("========DLG========\n");
DTN_INFO("HUBP: rc_hbe dlg_vbe min_d_y_n rc_per_ht rc_x_a_s "
" dst_y_a_s dst_y_pf dst_y_vvb dst_y_rvb dst_y_vfl dst_y_rfl rf_pix_fq"
" vratio_pf vrat_pf_c rc_pg_vbl rc_pg_vbc rc_mc_vbl rc_mc_vbc rc_pg_fll"
" rc_pg_flc rc_mc_fll rc_mc_flc pr_nom_l pr_nom_c rc_pg_nl rc_pg_nc "
" mr_nom_l mr_nom_c rc_mc_nl rc_mc_nc rc_ld_pl rc_ld_pc rc_ld_l "
" rc_ld_c cha_cur0 ofst_cur1 cha_cur1 vr_af_vc0 ddrq_limt x_rt_dlay"
" x_rp_dlay x_rr_sfl\n");
for (i = 0; i < pool->pipe_count; i++) {
struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
"% 8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh"
" %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
i, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
dlg_regs->xfc_reg_remote_surface_flip_latency);
}
DTN_INFO("========TTU========\n");
DTN_INFO("HUBP: qos_ll_wm qos_lh_wm mn_ttu_vb qos_l_flp rc_rd_p_l rc_rd_l rc_rd_p_c"
" rc_rd_c rc_rd_c0 rc_rd_pc0 rc_rd_c1 rc_rd_pc1 qos_lf_l qos_rds_l"
" qos_lf_c qos_rds_c qos_lf_c0 qos_rds_c0 qos_lf_c1 qos_rds_c1\n");
for (i = 0; i < pool->pipe_count; i++) {
struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
DTN_INFO("[%2d]: %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh %8xh\n",
i, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
}
DTN_INFO("\n");
}
void dcn10_log_hw_state(struct dc *dc)
{
struct dc_context *dc_ctx = dc->ctx;
@@ -121,41 +232,64 @@ void dcn10_log_hw_state(struct dc *dc)
dcn10_log_hubbub_state(dc);
DTN_INFO("HUBP:\t format \t addr_hi \t width \t height \t "
"rotation \t mirror \t sw_mode \t "
"dcc_en \t blank_en \t ttu_dis \t underflow \t "
"min_ttu_vblank \t qos_low_wm \t qos_high_wm \n");
dcn10_log_hubp_states(dc);
DTN_INFO("DPP: IGAM format IGAM mode DGAM mode RGAM mode"
" GAMUT mode C11 C12 C13 C14 C21 C22 C23 C24 "
"C31 C32 C33 C34\n");
for (i = 0; i < pool->pipe_count; i++) {
struct hubp *hubp = pool->hubps[i];
struct dcn_hubp_state s;
struct dpp *dpp = pool->dpps[i];
struct dcn_dpp_state s;
hubp1_read_state(TO_DCN10_HUBP(hubp), &s);
dpp->funcs->dpp_read_state(dpp, &s);
DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t "
"%xh \t %xh \t %xh \t "
"%d \t %d \t %d \t %xh \t",
hubp->inst,
s.pixel_format,
s.inuse_addr_hi,
s.viewport_width,
s.viewport_height,
s.rotation_angle,
s.h_mirror_en,
s.sw_mode,
s.dcc_en,
s.blank_en,
s.ttu_disable,
s.underflow_status);
DTN_INFO_MICRO_SEC(s.min_ttu_vblank);
DTN_INFO_MICRO_SEC(s.qos_level_low_wm);
DTN_INFO_MICRO_SEC(s.qos_level_high_wm);
DTN_INFO("[%2d]: %11xh %-11s %-11s %-11s"
"%8x %08xh %08xh %08xh %08xh %08xh %08xh",
dpp->inst,
s.igam_input_format,
(s.igam_lut_mode == 0) ? "BypassFixed" :
((s.igam_lut_mode == 1) ? "BypassFloat" :
((s.igam_lut_mode == 2) ? "RAM" :
((s.igam_lut_mode == 3) ? "RAM" :
"Unknown"))),
(s.dgam_lut_mode == 0) ? "Bypass" :
((s.dgam_lut_mode == 1) ? "sRGB" :
((s.dgam_lut_mode == 2) ? "Ycc" :
((s.dgam_lut_mode == 3) ? "RAM" :
((s.dgam_lut_mode == 4) ? "RAM" :
"Unknown")))),
(s.rgam_lut_mode == 0) ? "Bypass" :
((s.rgam_lut_mode == 1) ? "sRGB" :
((s.rgam_lut_mode == 2) ? "Ycc" :
((s.rgam_lut_mode == 3) ? "RAM" :
((s.rgam_lut_mode == 4) ? "RAM" :
"Unknown")))),
s.gamut_remap_mode,
s.gamut_remap_c11_c12,
s.gamut_remap_c13_c14,
s.gamut_remap_c21_c22,
s.gamut_remap_c23_c24,
s.gamut_remap_c31_c32,
s.gamut_remap_c33_c34);
DTN_INFO("\n");
}
DTN_INFO("\n");
DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t "
"h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n");
DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
for (i = 0; i < pool->pipe_count; i++) {
struct mpcc_state s = {0};
pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
if (s.opp_id != 0xf)
DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d\n",
i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
s.idle);
}
DTN_INFO("\n");
DTN_INFO("OTG: v_bs v_be v_ss v_se vpol vmax vmin vmax_sel vmin_sel"
" h_bs h_be h_ss h_se hpol htot vtot underflow\n");
for (i = 0; i < pool->timing_generator_count; i++) {
struct timing_generator *tg = pool->timing_generators[i];
@@ -167,9 +301,8 @@ void dcn10_log_hw_state(struct dc *dc)
if ((s.otg_enabled & 1) == 0)
continue;
DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t "
"%d \t %d \t %d \t %d \t %d \t %d \t "
"%d \t %d \t %d \t %d \t %d \t ",
DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
" %5d %5d %5d %5d %9d\n",
tg->inst,
s.v_blank_start,
s.v_blank_end,
@@ -178,6 +311,8 @@ void dcn10_log_hw_state(struct dc *dc)
s.v_sync_a_pol,
s.v_total_max,
s.v_total_min,
s.v_total_max_sel,
s.v_total_min_sel,
s.h_blank_start,
s.h_blank_end,
s.h_sync_a_start,
@@ -186,10 +321,19 @@ void dcn10_log_hw_state(struct dc *dc)
s.h_total,
s.v_total,
s.underflow_occurred_status);
DTN_INFO("\n");
}
DTN_INFO("\n");
DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n"
"dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
dc->current_state->bw.dcn.calc_clk.dcfclk_khz,
dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
dc->current_state->bw.dcn.calc_clk.dispclk_khz,
dc->current_state->bw.dcn.calc_clk.dppclk_khz,
dc->current_state->bw.dcn.calc_clk.max_supported_dppclk_khz,
dc->current_state->bw.dcn.calc_clk.fclk_khz,
dc->current_state->bw.dcn.calc_clk.socclk_khz);
log_mpc_crc(dc);
DTN_INFO_END();
@@ -354,7 +498,7 @@ static void power_on_plane(
struct dce_hwseq *hws,
int plane_id)
{
struct dc_context *ctx = hws->ctx;
DC_LOGGER_INIT(hws->ctx->logger);
if (REG(DC_IP_REQUEST_CNTL)) {
REG_SET(DC_IP_REQUEST_CNTL, 0,
IP_REQUEST_EN, 1);
@@ -461,7 +605,7 @@ static void false_optc_underflow_wa(
tg->funcs->clear_optc_underflow(tg);
}
static enum dc_status dcn10_prog_pixclk_crtc_otg(
static enum dc_status dcn10_enable_stream_timing(
struct pipe_ctx *pipe_ctx,
struct dc_state *context,
struct dc *dc)
@@ -553,7 +697,7 @@ static void reset_back_end_for_pipe(
struct dc_state *context)
{
int i;
struct dc_context *ctx = dc->ctx;
DC_LOGGER_INIT(dc->ctx->logger);
if (pipe_ctx->stream_res.stream_enc == NULL) {
pipe_ctx->stream = NULL;
return;
@@ -649,7 +793,7 @@ static void plane_atomic_power_down(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
struct dce_hwseq *hws = dc->hwseq;
struct dpp *dpp = pipe_ctx->plane_res.dpp;
struct dc_context *ctx = dc->ctx;
DC_LOGGER_INIT(dc->ctx->logger);
if (REG(DC_IP_REQUEST_CNTL)) {
REG_SET(DC_IP_REQUEST_CNTL, 0,
@@ -699,7 +843,7 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
{
struct dc_context *ctx = dc->ctx;
DC_LOGGER_INIT(dc->ctx->logger);
if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
return;
@@ -945,9 +1089,8 @@ static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
tf = plane_state->in_transfer_func;
if (plane_state->gamma_correction &&
plane_state->gamma_correction->is_identity)
dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
else if (plane_state->gamma_correction && dce_use_lut(plane_state->format))
!plane_state->gamma_correction->is_identity
&& dce_use_lut(plane_state->format))
dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
if (tf == NULL)
@@ -1433,7 +1576,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
}
}
static void program_output_csc(struct dc *dc,
static void dcn10_program_output_csc(struct dc *dc,
struct pipe_ctx *pipe_ctx,
enum dc_color_space colorspace,
uint16_t *matrix,
@@ -1623,6 +1766,8 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
struct mpc *mpc = dc->res_pool->mpc;
struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
/* TODO: proper fix once fpga works */
if (dc->debug.surface_visual_confirm)
@@ -1649,6 +1794,7 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
pipe_ctx->stream->output_color_space)
&& per_pixel_alpha;
/*
* TODO: remove hack
* Note: currently there is a bug in init_hw such that
@@ -1659,6 +1805,12 @@ static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
*/
mpcc_id = hubp->inst;
/* If there is no full update, don't need to touch MPC tree*/
if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
return;
}
/* check if this MPCC is already being used */
new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
/* remove MPCC if being used */
@@ -1777,7 +1929,7 @@ static void update_dchubp_dpp(
/*gamut remap*/
program_gamut_remap(pipe_ctx);
program_output_csc(dc,
dc->hwss.program_output_csc(dc,
pipe_ctx,
pipe_ctx->stream->output_color_space,
pipe_ctx->stream->csc_color_matrix.matrix,
@@ -1810,9 +1962,9 @@ static void update_dchubp_dpp(
hubp->funcs->set_blank(hubp, false);
}
static void dcn10_otg_blank(
static void dcn10_blank_pixel_data(
struct dc *dc,
struct stream_resource stream_res,
struct stream_resource *stream_res,
struct dc_stream_state *stream,
bool blank)
{
@@ -1823,21 +1975,21 @@ static void dcn10_otg_blank(
color_space = stream->output_color_space;
color_space_to_black_color(dc, color_space, &black_color);
if (stream_res.tg->funcs->set_blank_color)
stream_res.tg->funcs->set_blank_color(
stream_res.tg,
if (stream_res->tg->funcs->set_blank_color)
stream_res->tg->funcs->set_blank_color(
stream_res->tg,
&black_color);
if (!blank) {
if (stream_res.tg->funcs->set_blank)
stream_res.tg->funcs->set_blank(stream_res.tg, blank);
if (stream_res.abm)
stream_res.abm->funcs->set_abm_level(stream_res.abm, stream->abm_level);
if (stream_res->tg->funcs->set_blank)
stream_res->tg->funcs->set_blank(stream_res->tg, blank);
if (stream_res->abm)
stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
} else if (blank) {
if (stream_res.abm)
stream_res.abm->funcs->set_abm_immediate_disable(stream_res.abm);
if (stream_res.tg->funcs->set_blank)
stream_res.tg->funcs->set_blank(stream_res.tg, blank);
if (stream_res->abm)
stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
if (stream_res->tg->funcs->set_blank)
stream_res->tg->funcs->set_blank(stream_res->tg, blank);
}
}
@@ -1876,7 +2028,7 @@ static void program_all_pipe_in_tree(
pipe_ctx->stream_res.tg->funcs->program_global_sync(
pipe_ctx->stream_res.tg);
dcn10_otg_blank(dc, pipe_ctx->stream_res,
dc->hwss.blank_pixel_data(dc, &pipe_ctx->stream_res,
pipe_ctx->stream, blank);
}
@@ -1983,9 +2135,9 @@ static void dcn10_apply_ctx_for_surface(
bool removed_pipe[4] = { false };
unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
bool program_water_mark = false;
struct dc_context *ctx = dc->ctx;
struct pipe_ctx *top_pipe_to_program =
find_top_pipe_for_stream(dc, context, stream);
DC_LOGGER_INIT(dc->ctx->logger);
if (!top_pipe_to_program)
return;
@@ -1996,7 +2148,7 @@ static void dcn10_apply_ctx_for_surface(
if (num_planes == 0) {
/* OTG blank before remove all front end */
dcn10_otg_blank(dc, top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);
dc->hwss.blank_pixel_data(dc, &top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);
}
/* Disconnect unused mpcc */
@@ -2527,6 +2679,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.update_pending_status = dcn10_update_pending_status,
.set_input_transfer_func = dcn10_set_input_transfer_func,
.set_output_transfer_func = dcn10_set_output_transfer_func,
.program_output_csc = dcn10_program_output_csc,
.power_down = dce110_power_down,
.enable_accelerated_mode = dce110_enable_accelerated_mode,
.enable_timing_synchronization = dcn10_enable_timing_synchronization,
@@ -2538,10 +2691,11 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
.blank_stream = dce110_blank_stream,
.enable_display_power_gating = dcn10_dummy_display_power_gating,
.disable_plane = dcn10_disable_plane,
.blank_pixel_data = dcn10_blank_pixel_data,
.pipe_control_lock = dcn10_pipe_control_lock,
.set_bandwidth = dcn10_set_bandwidth,
.reset_hw_ctx_wrap = reset_hw_ctx_wrap,
.prog_pixclk_crtc_otg = dcn10_prog_pixclk_crtc_otg,
.enable_stream_timing = dcn10_enable_stream_timing,
.set_drr = set_drr,
.get_position = get_position,
.set_static_screen_control = set_static_screen_control,

24
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
Parādīt failu

@@ -65,6 +65,7 @@ static void mpc1_update_blending(
int mpcc_id)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id);
REG_UPDATE_5(MPCC_CONTROL[mpcc_id],
MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode,
@@ -74,6 +75,7 @@ static void mpc1_update_blending(
MPCC_GLOBAL_GAIN, blnd_cfg->global_gain);
mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
mpcc->blnd_cfg = *blnd_cfg;
}
void mpc1_update_stereo_mix(
@@ -235,8 +237,7 @@ struct mpcc *mpc1_insert_plane(
}
/* update the blending configuration */
new_mpcc->blnd_cfg = *blnd_cfg;
mpc->funcs->update_blending(mpc, &new_mpcc->blnd_cfg, mpcc_id);
mpc->funcs->update_blending(mpc, blnd_cfg, mpcc_id);
/* update the stereo mix settings, if provided */
if (sm_cfg != NULL) {
@@ -409,7 +410,26 @@ void mpc1_init_mpcc_list_from_hw(
}
}
void mpc1_read_mpcc_state(
struct mpc *mpc,
int mpcc_inst,
struct mpcc_state *s)
{
struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc);
REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
MPCC_BUSY, &s->busy);
}
const struct mpc_funcs dcn10_mpc_funcs = {
.read_mpcc_state = mpc1_read_mpcc_state,
.insert_plane = mpc1_insert_plane,
.remove_mpcc = mpc1_remove_mpcc,
.mpc_init = mpc1_mpc_init,

5
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h
Parādīt failu

@@ -183,4 +183,9 @@ struct mpcc *mpc1_get_mpcc_for_dpp(
struct mpc_tree *tree,
int dpp_id);
void mpc1_read_mpcc_state(
struct mpc *mpc,
int mpcc_inst,
struct mpcc_state *s);
#endif

94
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
Parādīt failu

@@ -93,6 +93,81 @@ static void optc1_disable_stereo(struct timing_generator *optc)
OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
}
static uint32_t get_start_vline(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing)
{
struct dc_crtc_timing patched_crtc_timing;
int vesa_sync_start;
int asic_blank_end;
int interlace_factor;
int vertical_line_start;
patched_crtc_timing = *dc_crtc_timing;
optc1_apply_front_porch_workaround(optc, &patched_crtc_timing);
vesa_sync_start = patched_crtc_timing.h_addressable +
patched_crtc_timing.h_border_right +
patched_crtc_timing.h_front_porch;
asic_blank_end = patched_crtc_timing.h_total -
vesa_sync_start -
patched_crtc_timing.h_border_left;
interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
vesa_sync_start = patched_crtc_timing.v_addressable +
patched_crtc_timing.v_border_bottom +
patched_crtc_timing.v_front_porch;
asic_blank_end = (patched_crtc_timing.v_total -
vesa_sync_start -
patched_crtc_timing.v_border_top)
* interlace_factor;
vertical_line_start = asic_blank_end - optc->dlg_otg_param.vstartup_start + 1;
if (vertical_line_start < 0) {
ASSERT(0);
vertical_line_start = 0;
}
return vertical_line_start;
}
void optc1_program_vline_interrupt(
struct timing_generator *optc,
const struct dc_crtc_timing *dc_crtc_timing,
unsigned long long vsync_delta)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
unsigned long long req_delta_tens_of_usec = div64_u64((vsync_delta + 9999), 10000);
unsigned long long pix_clk_hundreds_khz = div64_u64((dc_crtc_timing->pix_clk_khz + 99), 100);
uint32_t req_delta_lines = (uint32_t) div64_u64(
(req_delta_tens_of_usec * pix_clk_hundreds_khz + dc_crtc_timing->h_total - 1),
dc_crtc_timing->h_total);
uint32_t vsync_line = get_start_vline(optc, dc_crtc_timing);
uint32_t start_line = 0;
uint32_t endLine = 0;
if (req_delta_lines != 0)
req_delta_lines--;
if (req_delta_lines > vsync_line)
start_line = dc_crtc_timing->v_total - (req_delta_lines - vsync_line) - 1;
else
start_line = vsync_line - req_delta_lines;
endLine = start_line + 2;
if (endLine >= dc_crtc_timing->v_total)
endLine = 2;
REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
OTG_VERTICAL_INTERRUPT0_LINE_END, endLine);
}
/**
* program_timing_generator used by mode timing set
* Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition.
@@ -780,17 +855,17 @@ void optc1_set_drr(
OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
OTG_SET_V_TOTAL_MIN_MASK, 0);
} else {
REG_SET(OTG_V_TOTAL_MIN, 0,
OTG_V_TOTAL_MIN, 0);
REG_SET(OTG_V_TOTAL_MAX, 0,
OTG_V_TOTAL_MAX, 0);
REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
OTG_SET_V_TOTAL_MIN_MASK, 0,
OTG_V_TOTAL_MIN_SEL, 0,
OTG_V_TOTAL_MAX_SEL, 0,
OTG_FORCE_LOCK_ON_EVENT, 0);
REG_SET(OTG_V_TOTAL_MIN, 0,
OTG_V_TOTAL_MIN, 0);
REG_SET(OTG_V_TOTAL_MAX, 0,
OTG_V_TOTAL_MAX, 0);
}
}
@@ -1154,6 +1229,12 @@ void optc1_read_otg_state(struct optc *optc1,
REG_GET(OTG_V_TOTAL_MIN,
OTG_V_TOTAL_MIN, &s->v_total_min);
REG_GET(OTG_V_TOTAL_CONTROL,
OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
REG_GET(OTG_V_TOTAL_CONTROL,
OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
REG_GET_2(OTG_V_SYNC_A,
OTG_V_SYNC_A_START, &s->v_sync_a_start,
OTG_V_SYNC_A_END, &s->v_sync_a_end);
@@ -1215,6 +1296,7 @@ static bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
static const struct timing_generator_funcs dcn10_tg_funcs = {
.validate_timing = optc1_validate_timing,
.program_timing = optc1_program_timing,
.program_vline_interrupt = optc1_program_vline_interrupt,
.program_global_sync = optc1_program_global_sync,
.enable_crtc = optc1_enable_crtc,
.disable_crtc = optc1_disable_crtc,

16
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
Parādīt failu

@@ -65,6 +65,8 @@
SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
SRI(OTG_BLACK_COLOR, OTG, inst),\
SRI(OTG_CLOCK_CONTROL, OTG, inst),\
SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
@@ -124,6 +126,8 @@ struct dcn_optc_registers {
uint32_t OTG_TEST_PATTERN_CONTROL;
uint32_t OTG_TEST_PATTERN_COLOR;
uint32_t OTG_CLOCK_CONTROL;
uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL;
uint32_t OTG_VERTICAL_INTERRUPT0_POSITION;
uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL;
uint32_t OTG_VERTICAL_INTERRUPT2_POSITION;
uint32_t OPTC_INPUT_CLOCK_CONTROL;
@@ -206,6 +210,9 @@ struct dcn_optc_registers {
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
@@ -323,6 +330,9 @@ struct dcn_optc_registers {
type OTG_CLOCK_EN;\
type OTG_CLOCK_ON;\
type OTG_CLOCK_GATE_DIS;\
type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\
type OTG_VERTICAL_INTERRUPT0_LINE_START;\
type OTG_VERTICAL_INTERRUPT0_LINE_END;\
type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\
type OTG_VERTICAL_INTERRUPT2_LINE_START;\
type OPTC_INPUT_CLK_EN;\
@@ -396,6 +406,8 @@ struct dcn_otg_state {
uint32_t v_total;
uint32_t v_total_max;
uint32_t v_total_min;
uint32_t v_total_min_sel;
uint32_t v_total_max_sel;
uint32_t v_sync_a_start;
uint32_t v_sync_a_end;
uint32_t h_blank_start;
@@ -420,6 +432,10 @@ void optc1_program_timing(
const struct dc_crtc_timing *dc_crtc_timing,
bool use_vbios);
void optc1_program_vline_interrupt(struct timing_generator *optc,
const struct dc_crtc_timing *dc_crtc_timing,
unsigned long long vsync_delta);
void optc1_program_global_sync(
struct timing_generator *optc);

303
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
Parādīt failu

@@ -39,7 +39,7 @@
#include "dce110/dce110_hw_sequencer.h"
#include "dcn10/dcn10_opp.h"
#include "dce/dce_link_encoder.h"
#include "dce/dce_stream_encoder.h"
#include "dcn10/dcn10_stream_encoder.h"
#include "dce/dce_clocks.h"
#include "dce/dce_clock_source.h"
#include "dce/dce_audio.h"
@@ -166,36 +166,22 @@ static const struct dce_abm_mask abm_mask = {
#define stream_enc_regs(id)\
[id] = {\
SE_DCN_REG_LIST(id),\
.TMDS_CNTL = 0,\
.AFMT_AVI_INFO0 = 0,\
.AFMT_AVI_INFO1 = 0,\
.AFMT_AVI_INFO2 = 0,\
.AFMT_AVI_INFO3 = 0,\
SE_DCN_REG_LIST(id)\
}
static const struct dce110_stream_enc_registers stream_enc_regs[] = {
static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
stream_enc_regs(0),
stream_enc_regs(1),
stream_enc_regs(2),
stream_enc_regs(3),
};
static const struct dce_stream_encoder_shift se_shift = {
static const struct dcn10_stream_encoder_shift se_shift = {
SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT)
};
static const struct dce_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCN10(_MASK),
.AFMT_GENERIC0_UPDATE = 0,
.AFMT_GENERIC2_UPDATE = 0,
.DP_DYN_RANGE = 0,
.DP_YCBCR_RANGE = 0,
.HDMI_AVI_INFO_SEND = 0,
.HDMI_AVI_INFO_CONT = 0,
.HDMI_AVI_INFO_LINE = 0,
.DP_SEC_AVI_ENABLE = 0,
.AFMT_AVI_INFO_VERSION = 0
static const struct dcn10_stream_encoder_mask se_mask = {
SE_COMMON_MASK_SH_LIST_DCN10(_MASK)
};
#define audio_regs(id)\
@@ -320,11 +306,14 @@ static const struct dcn_dpp_registers tf_regs[] = {
};
static const struct dcn_dpp_shift tf_shift = {
TF_REG_LIST_SH_MASK_DCN10(__SHIFT)
TF_REG_LIST_SH_MASK_DCN10(__SHIFT),
TF_DEBUG_REG_LIST_SH_DCN10
};
static const struct dcn_dpp_mask tf_mask = {
TF_REG_LIST_SH_MASK_DCN10(_MASK),
TF_DEBUG_REG_LIST_MASK_DCN10
};
static const struct dcn_mpc_registers mpc_regs = {
@@ -650,16 +639,16 @@ static struct stream_encoder *dcn10_stream_encoder_create(
enum engine_id eng_id,
struct dc_context *ctx)
{
struct dce110_stream_encoder *enc110 =
kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
struct dcn10_stream_encoder *enc1 =
kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
if (!enc110)
if (!enc1)
return NULL;
dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
dcn10_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
&stream_enc_regs[eng_id],
&se_shift, &se_mask);
return &enc110->base;
return &enc1->base;
}
static const struct dce_hwseq_registers hwseq_reg = {
@@ -918,36 +907,6 @@ enum dc_status dcn10_add_stream_to_ctx(
return result;
}
enum dc_status dcn10_validate_guaranteed(
struct dc *dc,
struct dc_stream_state *dc_stream,
struct dc_state *context)
{
enum dc_status result = DC_ERROR_UNEXPECTED;
context->streams[0] = dc_stream;
dc_stream_retain(context->streams[0]);
context->stream_count++;
result = resource_map_pool_resources(dc, context, dc_stream);
if (result == DC_OK)
result = resource_map_phy_clock_resources(dc, context, dc_stream);
if (result == DC_OK)
result = build_mapped_resource(dc, context, dc_stream);
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
if (result == DC_OK && !dcn_validate_bandwidth(dc, context))
return DC_FAIL_BANDWIDTH_VALIDATE;
return result;
}
static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
struct dc_state *context,
const struct resource_pool *pool,
@@ -978,235 +937,16 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
return idle_pipe;
}
enum dcc_control {
dcc_control__256_256_xxx,
dcc_control__128_128_xxx,
dcc_control__256_64_64,
};
enum segment_order {
segment_order__na,
segment_order__contiguous,
segment_order__non_contiguous,
};
static bool dcc_support_pixel_format(
enum surface_pixel_format format,
unsigned int *bytes_per_element)
{
/* DML: get_bytes_per_element */
switch (format) {
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
*bytes_per_element = 2;
return true;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
*bytes_per_element = 4;
return true;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
*bytes_per_element = 8;
return true;
default:
return false;
}
}
static bool dcc_support_swizzle(
enum swizzle_mode_values swizzle,
unsigned int bytes_per_element,
enum segment_order *segment_order_horz,
enum segment_order *segment_order_vert)
{
bool standard_swizzle = false;
bool display_swizzle = false;
switch (swizzle) {
case DC_SW_4KB_S:
case DC_SW_64KB_S:
case DC_SW_VAR_S:
case DC_SW_4KB_S_X:
case DC_SW_64KB_S_X:
case DC_SW_VAR_S_X:
standard_swizzle = true;
break;
case DC_SW_4KB_D:
case DC_SW_64KB_D:
case DC_SW_VAR_D:
case DC_SW_4KB_D_X:
case DC_SW_64KB_D_X:
case DC_SW_VAR_D_X:
display_swizzle = true;
break;
default:
break;
}
if (bytes_per_element == 1 && standard_swizzle) {
*segment_order_horz = segment_order__contiguous;
*segment_order_vert = segment_order__na;
return true;
}
if (bytes_per_element == 2 && standard_swizzle) {
*segment_order_horz = segment_order__non_contiguous;
*segment_order_vert = segment_order__contiguous;
return true;
}
if (bytes_per_element == 4 && standard_swizzle) {
*segment_order_horz = segment_order__non_contiguous;
*segment_order_vert = segment_order__contiguous;
return true;
}
if (bytes_per_element == 8 && standard_swizzle) {
*segment_order_horz = segment_order__na;
*segment_order_vert = segment_order__contiguous;
return true;
}
if (bytes_per_element == 8 && display_swizzle) {
*segment_order_horz = segment_order__contiguous;
*segment_order_vert = segment_order__non_contiguous;
return true;
}
return false;
}
static void get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
unsigned int bytes_per_element)
{
/* copied from DML. might want to refactor DML to leverage from DML */
/* DML : get_blk256_size */
if (bytes_per_element == 1) {
*blk256_width = 16;
*blk256_height = 16;
} else if (bytes_per_element == 2) {
*blk256_width = 16;
*blk256_height = 8;
} else if (bytes_per_element == 4) {
*blk256_width = 8;
*blk256_height = 8;
} else if (bytes_per_element == 8) {
*blk256_width = 8;
*blk256_height = 4;
}
}
static void det_request_size(
unsigned int height,
unsigned int width,
unsigned int bpe,
bool *req128_horz_wc,
bool *req128_vert_wc)
{
unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
unsigned int blk256_height = 0;
unsigned int blk256_width = 0;
unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
get_blk256_size(&blk256_width, &blk256_height, bpe);
swath_bytes_horz_wc = height * blk256_height * bpe;
swath_bytes_vert_wc = width * blk256_width * bpe;
*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
false : /* full 256B request */
true; /* half 128b request */
*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
false : /* full 256B request */
true; /* half 128b request */
}
static bool get_dcc_compression_cap(const struct dc *dc,
static bool dcn10_get_dcc_compression_cap(const struct dc *dc,
const struct dc_dcc_surface_param *input,
struct dc_surface_dcc_cap *output)
{
/* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
enum dcc_control dcc_control;
unsigned int bpe;
enum segment_order segment_order_horz, segment_order_vert;
bool req128_horz_wc, req128_vert_wc;
memset(output, 0, sizeof(*output));
if (dc->debug.disable_dcc == DCC_DISABLE)
return false;
if (!dcc_support_pixel_format(input->format,
&bpe))
return false;
if (!dcc_support_swizzle(input->swizzle_mode, bpe,
&segment_order_horz, &segment_order_vert))
return false;
det_request_size(input->surface_size.height, input->surface_size.width,
bpe, &req128_horz_wc, &req128_vert_wc);
if (!req128_horz_wc && !req128_vert_wc) {
dcc_control = dcc_control__256_256_xxx;
} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
if (!req128_horz_wc)
dcc_control = dcc_control__256_256_xxx;
else if (segment_order_horz == segment_order__contiguous)
dcc_control = dcc_control__128_128_xxx;
else
dcc_control = dcc_control__256_64_64;
} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
if (!req128_vert_wc)
dcc_control = dcc_control__256_256_xxx;
else if (segment_order_vert == segment_order__contiguous)
dcc_control = dcc_control__128_128_xxx;
else
dcc_control = dcc_control__256_64_64;
} else {
if ((req128_horz_wc &&
segment_order_horz == segment_order__non_contiguous) ||
(req128_vert_wc &&
segment_order_vert == segment_order__non_contiguous))
/* access_dir not known, must use most constraining */
dcc_control = dcc_control__256_64_64;
else
/* reg128 is true for either horz and vert
* but segment_order is contiguous
*/
dcc_control = dcc_control__128_128_xxx;
}
if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
dcc_control != dcc_control__256_256_xxx)
return false;
switch (dcc_control) {
case dcc_control__256_256_xxx:
output->grph.rgb.max_uncompressed_blk_size = 256;
output->grph.rgb.max_compressed_blk_size = 256;
output->grph.rgb.independent_64b_blks = false;
break;
case dcc_control__128_128_xxx:
output->grph.rgb.max_uncompressed_blk_size = 128;
output->grph.rgb.max_compressed_blk_size = 128;
output->grph.rgb.independent_64b_blks = false;
break;
case dcc_control__256_64_64:
output->grph.rgb.max_uncompressed_blk_size = 256;
output->grph.rgb.max_compressed_blk_size = 64;
output->grph.rgb.independent_64b_blks = true;
break;
}
output->capable = true;
output->const_color_support = false;
return true;
return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
dc->res_pool->hubbub,
input,
output);
}
static void dcn10_destroy_resource_pool(struct resource_pool **pool)
{
struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool);
@@ -1227,13 +967,12 @@ static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_st
}
static struct dc_cap_funcs cap_funcs = {
.get_dcc_compression_cap = get_dcc_compression_cap
.get_dcc_compression_cap = dcn10_get_dcc_compression_cap
};
static struct resource_funcs dcn10_res_pool_funcs = {
.destroy = dcn10_destroy_resource_pool,
.link_enc_create = dcn10_link_encoder_create,
.validate_guaranteed = dcn10_validate_guaranteed,
.validate_bandwidth = dcn_validate_bandwidth,
.acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer,
.validate_plane = dcn10_validate_plane,

1490
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c Parasts fails
Parādīt failu

Failā izmaiņas netiks attēlotas, jo tās ir par lielu Ielādēt izmaiņas

524
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h Parasts fails
Parādīt failu

@@ -0,0 +1,524 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DC_STREAM_ENCODER_DCN10_H__
#define __DC_STREAM_ENCODER_DCN10_H__
#include "stream_encoder.h"
#define DCN10STRENC_FROM_STRENC(stream_encoder)\
container_of(stream_encoder, struct dcn10_stream_encoder, base)
#define SE_COMMON_DCN_REG_LIST(id) \
SRI(AFMT_CNTL, DIG, id), \
SRI(AFMT_GENERIC_0, DIG, id), \
SRI(AFMT_GENERIC_1, DIG, id), \
SRI(AFMT_GENERIC_2, DIG, id), \
SRI(AFMT_GENERIC_3, DIG, id), \
SRI(AFMT_GENERIC_4, DIG, id), \
SRI(AFMT_GENERIC_5, DIG, id), \
SRI(AFMT_GENERIC_6, DIG, id), \
SRI(AFMT_GENERIC_7, DIG, id), \
SRI(AFMT_GENERIC_HDR, DIG, id), \
SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
SRI(AFMT_60958_0, DIG, id), \
SRI(AFMT_60958_1, DIG, id), \
SRI(AFMT_60958_2, DIG, id), \
SRI(DIG_FE_CNTL, DIG, id), \
SRI(HDMI_CONTROL, DIG, id), \
SRI(HDMI_DB_CONTROL, DIG, id), \
SRI(HDMI_GC, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
SRI(HDMI_ACR_32_0, DIG, id),\
SRI(HDMI_ACR_32_1, DIG, id),\
SRI(HDMI_ACR_44_0, DIG, id),\
SRI(HDMI_ACR_44_1, DIG, id),\
SRI(HDMI_ACR_48_0, DIG, id),\
SRI(HDMI_ACR_48_1, DIG, id),\
SRI(DP_DB_CNTL, DP, id), \
SRI(DP_MSA_MISC, DP, id), \
SRI(DP_MSA_COLORIMETRY, DP, id), \
SRI(DP_MSA_TIMING_PARAM1, DP, id), \
SRI(DP_MSA_TIMING_PARAM2, DP, id), \
SRI(DP_MSA_TIMING_PARAM3, DP, id), \
SRI(DP_MSA_TIMING_PARAM4, DP, id), \
SRI(DP_MSE_RATE_CNTL, DP, id), \
SRI(DP_MSE_RATE_UPDATE, DP, id), \
SRI(DP_PIXEL_FORMAT, DP, id), \
SRI(DP_SEC_CNTL, DP, id), \
SRI(DP_STEER_FIFO, DP, id), \
SRI(DP_VID_M, DP, id), \
SRI(DP_VID_N, DP, id), \
SRI(DP_VID_STREAM_CNTL, DP, id), \
SRI(DP_VID_TIMING, DP, id), \
SRI(DP_SEC_AUD_N, DP, id), \
SRI(DP_SEC_TIMESTAMP, DP, id)
#define SE_DCN_REG_LIST(id)\
SE_COMMON_DCN_REG_LIST(id)
struct dcn10_stream_enc_registers {
uint32_t AFMT_CNTL;
uint32_t AFMT_AVI_INFO0;
uint32_t AFMT_AVI_INFO1;
uint32_t AFMT_AVI_INFO2;
uint32_t AFMT_AVI_INFO3;
uint32_t AFMT_GENERIC_0;
uint32_t AFMT_GENERIC_1;
uint32_t AFMT_GENERIC_2;
uint32_t AFMT_GENERIC_3;
uint32_t AFMT_GENERIC_4;
uint32_t AFMT_GENERIC_5;
uint32_t AFMT_GENERIC_6;
uint32_t AFMT_GENERIC_7;
uint32_t AFMT_GENERIC_HDR;
uint32_t AFMT_INFOFRAME_CONTROL0;
uint32_t AFMT_VBI_PACKET_CONTROL;
uint32_t AFMT_VBI_PACKET_CONTROL1;
uint32_t AFMT_AUDIO_PACKET_CONTROL;
uint32_t AFMT_AUDIO_PACKET_CONTROL2;
uint32_t AFMT_AUDIO_SRC_CONTROL;
uint32_t AFMT_60958_0;
uint32_t AFMT_60958_1;
uint32_t AFMT_60958_2;
uint32_t DIG_FE_CNTL;
uint32_t DP_MSE_RATE_CNTL;
uint32_t DP_MSE_RATE_UPDATE;
uint32_t DP_PIXEL_FORMAT;
uint32_t DP_SEC_CNTL;
uint32_t DP_STEER_FIFO;
uint32_t DP_VID_M;
uint32_t DP_VID_N;
uint32_t DP_VID_STREAM_CNTL;
uint32_t DP_VID_TIMING;
uint32_t DP_SEC_AUD_N;
uint32_t DP_SEC_TIMESTAMP;
uint32_t HDMI_CONTROL;
uint32_t HDMI_GC;
uint32_t HDMI_GENERIC_PACKET_CONTROL0;
uint32_t HDMI_GENERIC_PACKET_CONTROL1;
uint32_t HDMI_GENERIC_PACKET_CONTROL2;
uint32_t HDMI_GENERIC_PACKET_CONTROL3;
uint32_t HDMI_GENERIC_PACKET_CONTROL4;
uint32_t HDMI_GENERIC_PACKET_CONTROL5;
uint32_t HDMI_INFOFRAME_CONTROL0;
uint32_t HDMI_INFOFRAME_CONTROL1;
uint32_t HDMI_VBI_PACKET_CONTROL;
uint32_t HDMI_AUDIO_PACKET_CONTROL;
uint32_t HDMI_ACR_PACKET_CONTROL;
uint32_t HDMI_ACR_32_0;
uint32_t HDMI_ACR_32_1;
uint32_t HDMI_ACR_44_0;
uint32_t HDMI_ACR_44_1;
uint32_t HDMI_ACR_48_0;
uint32_t HDMI_ACR_48_1;
uint32_t DP_DB_CNTL;
uint32_t DP_MSA_MISC;
uint32_t DP_MSA_COLORIMETRY;
uint32_t DP_MSA_TIMING_PARAM1;
uint32_t DP_MSA_TIMING_PARAM2;
uint32_t DP_MSA_TIMING_PARAM3;
uint32_t DP_MSA_TIMING_PARAM4;
uint32_t HDMI_DB_CONTROL;
};
#define SE_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh)
#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)
#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
#define SE_REG_FIELD_LIST_DCN1_0(type) \
type AFMT_GENERIC_INDEX;\
type AFMT_GENERIC_HB0;\
type AFMT_GENERIC_HB1;\
type AFMT_GENERIC_HB2;\
type AFMT_GENERIC_HB3;\
type AFMT_GENERIC_LOCK_STATUS;\
type AFMT_GENERIC_CONFLICT;\
type AFMT_GENERIC_CONFLICT_CLR;\
type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\
type AFMT_GENERIC0_FRAME_UPDATE;\
type AFMT_GENERIC1_FRAME_UPDATE;\
type AFMT_GENERIC2_FRAME_UPDATE;\
type AFMT_GENERIC3_FRAME_UPDATE;\
type AFMT_GENERIC4_FRAME_UPDATE;\
type AFMT_GENERIC5_FRAME_UPDATE;\
type AFMT_GENERIC6_FRAME_UPDATE;\
type AFMT_GENERIC7_FRAME_UPDATE;\
type HDMI_GENERIC0_CONT;\
type HDMI_GENERIC0_SEND;\
type HDMI_GENERIC0_LINE;\
type HDMI_GENERIC1_CONT;\
type HDMI_GENERIC1_SEND;\
type HDMI_GENERIC1_LINE;\
type HDMI_GENERIC2_CONT;\
type HDMI_GENERIC2_SEND;\
type HDMI_GENERIC2_LINE;\
type HDMI_GENERIC3_CONT;\
type HDMI_GENERIC3_SEND;\
type HDMI_GENERIC3_LINE;\
type HDMI_GENERIC4_CONT;\
type HDMI_GENERIC4_SEND;\
type HDMI_GENERIC4_LINE;\
type HDMI_GENERIC5_CONT;\
type HDMI_GENERIC5_SEND;\
type HDMI_GENERIC5_LINE;\
type HDMI_GENERIC6_CONT;\
type HDMI_GENERIC6_SEND;\
type HDMI_GENERIC6_LINE;\
type HDMI_GENERIC7_CONT;\
type HDMI_GENERIC7_SEND;\
type HDMI_GENERIC7_LINE;\
type DP_PIXEL_ENCODING;\
type DP_COMPONENT_DEPTH;\
type HDMI_PACKET_GEN_VERSION;\
type HDMI_KEEPOUT_MODE;\
type HDMI_DEEP_COLOR_ENABLE;\
type HDMI_CLOCK_CHANNEL_RATE;\
type HDMI_DEEP_COLOR_DEPTH;\
type HDMI_GC_CONT;\
type HDMI_GC_SEND;\
type HDMI_NULL_SEND;\
type HDMI_DATA_SCRAMBLE_EN;\
type HDMI_AUDIO_INFO_SEND;\
type AFMT_AUDIO_INFO_UPDATE;\
type HDMI_AUDIO_INFO_LINE;\
type HDMI_GC_AVMUTE;\
type DP_MSE_RATE_X;\
type DP_MSE_RATE_Y;\
type DP_MSE_RATE_UPDATE_PENDING;\
type DP_SEC_GSP0_ENABLE;\
type DP_SEC_STREAM_ENABLE;\
type DP_SEC_GSP1_ENABLE;\
type DP_SEC_GSP2_ENABLE;\
type DP_SEC_GSP3_ENABLE;\
type DP_SEC_GSP4_ENABLE;\
type DP_SEC_GSP5_ENABLE;\
type DP_SEC_GSP6_ENABLE;\
type DP_SEC_GSP7_ENABLE;\
type DP_SEC_MPG_ENABLE;\
type DP_VID_STREAM_DIS_DEFER;\
type DP_VID_STREAM_ENABLE;\
type DP_VID_STREAM_STATUS;\
type DP_STEER_FIFO_RESET;\
type DP_VID_M_N_GEN_EN;\
type DP_VID_N;\
type DP_VID_M;\
type DIG_START;\
type AFMT_AUDIO_SRC_SELECT;\
type AFMT_AUDIO_CHANNEL_ENABLE;\
type HDMI_AUDIO_PACKETS_PER_LINE;\
type HDMI_AUDIO_DELAY_EN;\
type AFMT_60958_CS_UPDATE;\
type AFMT_AUDIO_LAYOUT_OVRD;\
type AFMT_60958_OSF_OVRD;\
type HDMI_ACR_AUTO_SEND;\
type HDMI_ACR_SOURCE;\
type HDMI_ACR_AUDIO_PRIORITY;\
type HDMI_ACR_CTS_32;\
type HDMI_ACR_N_32;\
type HDMI_ACR_CTS_44;\
type HDMI_ACR_N_44;\
type HDMI_ACR_CTS_48;\
type HDMI_ACR_N_48;\
type AFMT_60958_CS_CHANNEL_NUMBER_L;\
type AFMT_60958_CS_CLOCK_ACCURACY;\
type AFMT_60958_CS_CHANNEL_NUMBER_R;\
type AFMT_60958_CS_CHANNEL_NUMBER_2;\
type AFMT_60958_CS_CHANNEL_NUMBER_3;\
type AFMT_60958_CS_CHANNEL_NUMBER_4;\
type AFMT_60958_CS_CHANNEL_NUMBER_5;\
type AFMT_60958_CS_CHANNEL_NUMBER_6;\
type AFMT_60958_CS_CHANNEL_NUMBER_7;\
type DP_SEC_AUD_N;\
type DP_SEC_TIMESTAMP_MODE;\
type DP_SEC_ASP_ENABLE;\
type DP_SEC_ATP_ENABLE;\
type DP_SEC_AIP_ENABLE;\
type DP_SEC_ACM_ENABLE;\
type AFMT_AUDIO_SAMPLE_SEND;\
type AFMT_AUDIO_CLOCK_EN;\
type TMDS_PIXEL_ENCODING;\
type TMDS_COLOR_FORMAT;\
type DIG_STEREOSYNC_SELECT;\
type DIG_STEREOSYNC_GATE_EN;\
type DP_DB_DISABLE;\
type DP_MSA_MISC0;\
type DP_MSA_HTOTAL;\
type DP_MSA_VTOTAL;\
type DP_MSA_HSTART;\
type DP_MSA_VSTART;\
type DP_MSA_HSYNCWIDTH;\
type DP_MSA_HSYNCPOLARITY;\
type DP_MSA_VSYNCWIDTH;\
type DP_MSA_VSYNCPOLARITY;\
type DP_MSA_HWIDTH;\
type DP_MSA_VHEIGHT;\
type HDMI_DB_DISABLE;\
type DP_VID_N_MUL;\
type DP_VID_M_DOUBLE_VALUE_EN
struct dcn10_stream_encoder_shift {
SE_REG_FIELD_LIST_DCN1_0(uint8_t);
};
struct dcn10_stream_encoder_mask {
SE_REG_FIELD_LIST_DCN1_0(uint32_t);
};
struct dcn10_stream_encoder {
struct stream_encoder base;
const struct dcn10_stream_enc_registers *regs;
const struct dcn10_stream_encoder_shift *se_shift;
const struct dcn10_stream_encoder_mask *se_mask;
};
void dcn10_stream_encoder_construct(
struct dcn10_stream_encoder *enc1,
struct dc_context *ctx,
struct dc_bios *bp,
enum engine_id eng_id,
const struct dcn10_stream_enc_registers *regs,
const struct dcn10_stream_encoder_shift *se_shift,
const struct dcn10_stream_encoder_mask *se_mask);
void enc1_update_generic_info_packet(
struct dcn10_stream_encoder *enc1,
uint32_t packet_index,
const struct dc_info_packet *info_packet);
void enc1_stream_encoder_dp_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
enum dc_color_space output_color_space);
void enc1_stream_encoder_hdmi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
int actual_pix_clk_khz,
bool enable_audio);
void enc1_stream_encoder_dvi_set_stream_attribute(
struct stream_encoder *enc,
struct dc_crtc_timing *crtc_timing,
bool is_dual_link);
void enc1_stream_encoder_set_mst_bandwidth(
struct stream_encoder *enc,
struct fixed31_32 avg_time_slots_per_mtp);
void enc1_stream_encoder_update_dp_info_packets(
struct stream_encoder *enc,
const struct encoder_info_frame *info_frame);
void enc1_stream_encoder_stop_dp_info_packets(
struct stream_encoder *enc);
void enc1_stream_encoder_dp_blank(
struct stream_encoder *enc);
void enc1_stream_encoder_dp_unblank(
struct stream_encoder *enc,
const struct encoder_unblank_param *param);
void enc1_setup_stereo_sync(
struct stream_encoder *enc,
int tg_inst, bool enable);
void enc1_stream_encoder_set_avmute(
struct stream_encoder *enc,
bool enable);
void enc1_se_audio_mute_control(
struct stream_encoder *enc,
bool mute);
void enc1_se_dp_audio_setup(
struct stream_encoder *enc,
unsigned int az_inst,
struct audio_info *info);
void enc1_se_dp_audio_enable(
struct stream_encoder *enc);
void enc1_se_dp_audio_disable(
struct stream_encoder *enc);
void enc1_se_hdmi_audio_setup(
struct stream_encoder *enc,
unsigned int az_inst,
struct audio_info *info,
struct audio_crtc_info *audio_crtc_info);
void enc1_se_hdmi_audio_disable(
struct stream_encoder *enc);
#endif /* __DC_STREAM_ENCODER_DCN10_H__ */

4
drivers/gpu/drm/amd/display/dc/dm_services.h
Parādīt failu

@@ -341,6 +341,10 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);
unsigned long long dm_get_timestamp(struct dc_context *ctx);
unsigned long long dm_get_elapse_time_in_ns(struct dc_context *ctx,
unsigned long long current_time_stamp,
unsigned long long last_time_stamp);
/*
* performance tracing
*/

138
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
Parādīt failu

@@ -26,75 +26,89 @@
#include "display_mode_lib.h"
#include "dc_features.h"
static const struct _vcs_dpi_ip_params_st dcn1_0_ip = {
.rob_buffer_size_kbytes = 64,
.det_buffer_size_kbytes = 164,
.dpte_buffer_size_in_pte_reqs = 42,
.dpp_output_buffer_pixels = 2560,
.opp_output_buffer_lines = 1,
.pixel_chunk_size_kbytes = 8,
.pte_enable = 1,
.pte_chunk_size_kbytes = 2,
.meta_chunk_size_kbytes = 2,
.writeback_chunk_size_kbytes = 2,
.line_buffer_size_bits = 589824,
.max_line_buffer_lines = 12,
.IsLineBufferBppFixed = 0,
.LineBufferFixedBpp = -1,
.writeback_luma_buffer_size_kbytes = 12,
.writeback_chroma_buffer_size_kbytes = 8,
.max_num_dpp = 4,
.max_num_wb = 2,
.max_dchub_pscl_bw_pix_per_clk = 4,
.max_pscl_lb_bw_pix_per_clk = 2,
.max_lb_vscl_bw_pix_per_clk = 4,
.max_vscl_hscl_bw_pix_per_clk = 4,
.max_hscl_ratio = 4,
.max_vscl_ratio = 4,
.hscl_mults = 4,
.vscl_mults = 4,
.max_hscl_taps = 8,
.max_vscl_taps = 8,
.dispclk_ramp_margin_percent = 1,
.underscan_factor = 1.10,
.min_vblank_lines = 14,
.dppclk_delay_subtotal = 90,
.dispclk_delay_subtotal = 42,
.dcfclk_cstate_latency = 10,
.max_inter_dcn_tile_repeaters = 8,
.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0,
.bug_forcing_LC_req_same_size_fixed = 0,
};
static const struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = {
.sr_exit_time_us = 9.0,
.sr_enter_plus_exit_time_us = 11.0,
.urgent_latency_us = 4.0,
.writeback_latency_us = 12.0,
.ideal_dram_bw_after_urgent_percent = 80.0,
.max_request_size_bytes = 256,
.downspread_percent = 0.5,
.dram_page_open_time_ns = 50.0,
.dram_rw_turnaround_time_ns = 17.5,
.dram_return_buffer_per_channel_bytes = 8192,
.round_trip_ping_latency_dcfclk_cycles = 128,
.urgent_out_of_order_return_per_channel_bytes = 256,
.channel_interleave_bytes = 256,
.num_banks = 8,
.num_chans = 2,
.vmm_page_size_bytes = 4096,
.dram_clock_change_latency_us = 17.0,
.writeback_dram_clock_change_latency_us = 23.0,
.return_bus_width_bytes = 64,
};
static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)
{
if (project == DML_PROJECT_RAVEN1) {
soc->sr_exit_time_us = 9.0;
soc->sr_enter_plus_exit_time_us = 11.0;
soc->urgent_latency_us = 4.0;
soc->writeback_latency_us = 12.0;
soc->ideal_dram_bw_after_urgent_percent = 80.0;
soc->max_request_size_bytes = 256;
soc->downspread_percent = 0.5;
soc->dram_page_open_time_ns = 50.0;
soc->dram_rw_turnaround_time_ns = 17.5;
soc->dram_return_buffer_per_channel_bytes = 8192;
soc->round_trip_ping_latency_dcfclk_cycles = 128;
soc->urgent_out_of_order_return_per_channel_bytes = 256;
soc->channel_interleave_bytes = 256;
soc->num_banks = 8;
soc->num_chans = 2;
soc->vmm_page_size_bytes = 4096;
soc->dram_clock_change_latency_us = 17.0;
soc->writeback_dram_clock_change_latency_us = 23.0;
soc->return_bus_width_bytes = 64;
} else {
BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
switch (project) {
case DML_PROJECT_RAVEN1:
*soc = dcn1_0_soc;
break;
default:
ASSERT(0);
break;
}
}
static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project project)
{
if (project == DML_PROJECT_RAVEN1) {
ip->rob_buffer_size_kbytes = 64;
ip->det_buffer_size_kbytes = 164;
ip->dpte_buffer_size_in_pte_reqs = 42;
ip->dpp_output_buffer_pixels = 2560;
ip->opp_output_buffer_lines = 1;
ip->pixel_chunk_size_kbytes = 8;
ip->pte_enable = 1;
ip->pte_chunk_size_kbytes = 2;
ip->meta_chunk_size_kbytes = 2;
ip->writeback_chunk_size_kbytes = 2;
ip->line_buffer_size_bits = 589824;
ip->max_line_buffer_lines = 12;
ip->IsLineBufferBppFixed = 0;
ip->LineBufferFixedBpp = -1;
ip->writeback_luma_buffer_size_kbytes = 12;
ip->writeback_chroma_buffer_size_kbytes = 8;
ip->max_num_dpp = 4;
ip->max_num_wb = 2;
ip->max_dchub_pscl_bw_pix_per_clk = 4;
ip->max_pscl_lb_bw_pix_per_clk = 2;
ip->max_lb_vscl_bw_pix_per_clk = 4;
ip->max_vscl_hscl_bw_pix_per_clk = 4;
ip->max_hscl_ratio = 4;
ip->max_vscl_ratio = 4;
ip->hscl_mults = 4;
ip->vscl_mults = 4;
ip->max_hscl_taps = 8;
ip->max_vscl_taps = 8;
ip->dispclk_ramp_margin_percent = 1;
ip->underscan_factor = 1.10;
ip->min_vblank_lines = 14;
ip->dppclk_delay_subtotal = 90;
ip->dispclk_delay_subtotal = 42;
ip->dcfclk_cstate_latency = 10;
ip->max_inter_dcn_tile_repeaters = 8;
ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0;
ip->bug_forcing_LC_req_same_size_fixed = 0;
} else {
BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
switch (project) {
case DML_PROJECT_RAVEN1:
*ip = dcn1_0_ip;
break;
default:
ASSERT(0);
break;
}
}

5
drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
Parādīt failu

@@ -215,8 +215,8 @@ struct writeback_st {
int wb_vtaps_luma;
int wb_htaps_chroma;
int wb_vtaps_chroma;
int wb_hratio;
int wb_vratio;
double wb_hratio;
double wb_vratio;
};
struct _vcs_dpi_display_output_params_st {
@@ -224,6 +224,7 @@ struct _vcs_dpi_display_output_params_st {
int output_bpp;
int dsc_enable;
int wb_enable;
int num_active_wb;
int opp_input_bpc;
int output_type;
int output_format;

3
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
Parādīt failu

@@ -75,6 +75,9 @@ bool dal_hw_factory_init(
return true;
case DCE_VERSION_11_0:
case DCE_VERSION_11_2:
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
#endif
dal_hw_factory_dce110_init(factory);
return true;
case DCE_VERSION_12_0:

3
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
Parādīt failu

@@ -72,6 +72,9 @@ bool dal_hw_translate_init(
case DCE_VERSION_10_0:
case DCE_VERSION_11_0:
case DCE_VERSION_11_2:
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
#endif
dal_hw_translate_dce110_init(translate);
return true;
case DCE_VERSION_12_0:

2
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
Parādīt failu

@@ -527,7 +527,7 @@ static void construct(
REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
if (xtal_ref_div == 0) {
DC_LOG_WARNING("Invalid base timer divider\n",
DC_LOG_WARNING("Invalid base timer divider [%s]\n",
__func__);
xtal_ref_div = 2;
}

3
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c
Parādīt failu

@@ -83,6 +83,9 @@ struct i2caux *dal_i2caux_create(
case DCE_VERSION_8_3:
return dal_i2caux_dce80_create(ctx);
case DCE_VERSION_11_2:
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
case DCE_VERSION_11_22:
#endif
return dal_i2caux_dce112_create(ctx);
case DCE_VERSION_11_0:
return dal_i2caux_dce110_create(ctx);

6
drivers/gpu/drm/amd/display/dc/inc/core_types.h
Parādīt failu

@@ -95,11 +95,6 @@ struct resource_funcs {
struct link_encoder *(*link_enc_create)(
const struct encoder_init_data *init);
enum dc_status (*validate_guaranteed)(
struct dc *dc,
struct dc_stream_state *stream,
struct dc_state *context);
bool (*validate_bandwidth)(
struct dc *dc,
struct dc_state *context);
@@ -250,6 +245,7 @@ struct dce_bw_output {
bool all_displays_in_sync;
struct dce_watermarks urgent_wm_ns[MAX_PIPES];
struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
int sclk_khz;
int sclk_deep_sleep_khz;

5
drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
Parādīt failu

@@ -102,13 +102,14 @@ bool dal_ddc_service_query_ddc_data(
uint8_t *read_buf,
uint32_t read_size);
ssize_t dal_ddc_service_read_dpcd_data(
enum ddc_result dal_ddc_service_read_dpcd_data(
struct ddc_service *ddc,
bool i2c,
enum i2c_mot_mode mot,
uint32_t address,
uint8_t *data,
uint32_t len);
uint32_t len,
uint32_t *read);
enum ddc_result dal_ddc_service_write_dpcd_data(
struct ddc_service *ddc,

4
drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
Parādīt failu

@@ -42,6 +42,10 @@ enum bw_calcs_version {
BW_CALCS_VERSION_CARRIZO,
BW_CALCS_VERSION_POLARIS10,
BW_CALCS_VERSION_POLARIS11,
BW_CALCS_VERSION_POLARIS12,
#if defined(CONFIG_DRM_AMD_DC_VEGAM)
BW_CALCS_VERSION_VEGAM,
#endif
BW_CALCS_VERSION_STONEY,
BW_CALCS_VERSION_VEGA10
};

64
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h Parasts fails
Parādīt failu

@@ -0,0 +1,64 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DAL_DCHUBBUB_H__
#define __DAL_DCHUBBUB_H__
enum dcc_control {
dcc_control__256_256_xxx,
dcc_control__128_128_xxx,
dcc_control__256_64_64,
};
enum segment_order {
segment_order__na,
segment_order__contiguous,
segment_order__non_contiguous,
};
struct hubbub_funcs {
void (*update_dchub)(
struct hubbub *hubbub,
struct dchub_init_data *dh_data);
bool (*get_dcc_compression_cap)(struct hubbub *hubbub,
const struct dc_dcc_surface_param *input,
struct dc_surface_dcc_cap *output);
bool (*dcc_support_swizzle)(
enum swizzle_mode_values swizzle,
unsigned int bytes_per_element,
enum segment_order *segment_order_horz,
enum segment_order *segment_order_vert);
bool (*dcc_support_pixel_format)(
enum surface_pixel_format format,
unsigned int *bytes_per_element);
};
#endif

18
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
Parādīt failu

@@ -44,7 +44,23 @@ struct dpp_grph_csc_adjustment {
enum graphics_gamut_adjust_type gamut_adjust_type;
};
struct dcn_dpp_state {
uint32_t igam_lut_mode;
uint32_t igam_input_format;
uint32_t dgam_lut_mode;
uint32_t rgam_lut_mode;
uint32_t gamut_remap_mode;
uint32_t gamut_remap_c11_c12;
uint32_t gamut_remap_c13_c14;
uint32_t gamut_remap_c21_c22;
uint32_t gamut_remap_c23_c24;
uint32_t gamut_remap_c31_c32;
uint32_t gamut_remap_c33_c34;
};
struct dpp_funcs {
void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
void (*dpp_reset)(struct dpp *dpp);
void (*dpp_set_scaler)(struct dpp *dpp,
@@ -117,7 +133,7 @@ struct dpp_funcs {
struct dpp *dpp_base,
enum surface_pixel_format format,
enum expansion_mode mode,
struct csc_transform input_csc_color_matrix,
struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space);
void (*dpp_full_bypass)(struct dpp *dpp_base);

2
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
Parādīt failu

@@ -56,7 +56,6 @@ struct hubp {
bool power_gated;
};
struct hubp_funcs {
void (*hubp_setup)(
struct hubp *hubp,
@@ -121,6 +120,7 @@ struct hubp_funcs {
void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
void (*hubp_read_state)(struct hubp *hubp);
};

10
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
Parādīt failu

@@ -140,11 +140,6 @@ enum opp_regamma {
OPP_REGAMMA_USER
};
struct csc_transform {
uint16_t matrix[12];
bool enable_adjustment;
};
struct dc_bias_and_scale {
uint16_t scale_red;
uint16_t bias_red;
@@ -191,4 +186,9 @@ enum controller_dp_test_pattern {
CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
};
enum dc_lut_mode {
LUT_BYPASS,
LUT_RAM_A,
LUT_RAM_B
};
#endif /* __DAL_HW_SHARED_H__ */

2
drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h
Parādīt failu

@@ -87,7 +87,7 @@ struct ipp_funcs {
struct input_pixel_processor *ipp,
enum surface_pixel_format format,
enum expansion_mode mode,
struct csc_transform input_csc_color_matrix,
struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space);
/* DCE function to setup IPP. TODO: see if we can consolidate to setup */

1
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
Parādīt failu

@@ -149,6 +149,7 @@ struct link_encoder_funcs {
bool connect);
void (*enable_hpd)(struct link_encoder *enc);
void (*disable_hpd)(struct link_encoder *enc);
bool (*is_dig_enabled)(struct link_encoder *enc);
void (*destroy)(struct link_encoder **enc);
};

1
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
Parādīt failu

@@ -104,6 +104,7 @@ struct mem_input_funcs {
struct mem_input *mem_input,
struct dce_watermarks nbp,
struct dce_watermarks stutter,
struct dce_watermarks stutter_enter,
struct dce_watermarks urgent,
uint32_t total_dest_line_time_ns);

17
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
Parādīt failu

@@ -105,7 +105,24 @@ struct mpc {
struct mpcc mpcc_array[MAX_MPCC];
};
struct mpcc_state {
uint32_t opp_id;
uint32_t dpp_id;
uint32_t bot_mpcc_id;
uint32_t mode;
uint32_t alpha_mode;
uint32_t pre_multiplied_alpha;
uint32_t overlap_only;
uint32_t idle;
uint32_t busy;
};
struct mpc_funcs {
void (*read_mpcc_state)(
struct mpc *mpc,
int mpcc_inst,
struct mpcc_state *s);
/*
* Insert DPP into MPC tree based on specified blending position.
* Only used for planes that are part of blending chain for OPP output

36
drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
Parādīt failu

@@ -29,31 +29,40 @@
#define STREAM_ENCODER_H_
#include "audio_types.h"
#include "hw_shared.h"
struct dc_bios;
struct dc_context;
struct dc_crtc_timing;
struct encoder_info_packet {
bool valid;
uint8_t hb0;
uint8_t hb1;
uint8_t hb2;
uint8_t hb3;
uint8_t sb[32];
enum dp_pixel_encoding_type {
DP_PIXEL_ENCODING_TYPE_RGB444 = 0x00000000,
DP_PIXEL_ENCODING_TYPE_YCBCR422 = 0x00000001,
DP_PIXEL_ENCODING_TYPE_YCBCR444 = 0x00000002,
DP_PIXEL_ENCODING_TYPE_RGB_WIDE_GAMUT = 0x00000003,
DP_PIXEL_ENCODING_TYPE_Y_ONLY = 0x00000004,
DP_PIXEL_ENCODING_TYPE_YCBCR420 = 0x00000005
};
enum dp_component_depth {
DP_COMPONENT_PIXEL_DEPTH_6BPC = 0x00000000,
DP_COMPONENT_PIXEL_DEPTH_8BPC = 0x00000001,
DP_COMPONENT_PIXEL_DEPTH_10BPC = 0x00000002,
DP_COMPONENT_PIXEL_DEPTH_12BPC = 0x00000003,
DP_COMPONENT_PIXEL_DEPTH_16BPC = 0x00000004
};
struct encoder_info_frame {
/* auxiliary video information */
struct encoder_info_packet avi;
struct encoder_info_packet gamut;
struct encoder_info_packet vendor;
struct dc_info_packet avi;
struct dc_info_packet gamut;
struct dc_info_packet vendor;
/* source product description */
struct encoder_info_packet spd;
struct dc_info_packet spd;
/* video stream configuration */
struct encoder_info_packet vsc;
struct dc_info_packet vsc;
/* HDR Static MetaData */
struct encoder_info_packet hdrsmd;
struct dc_info_packet hdrsmd;
};
struct encoder_unblank_param {
@@ -147,6 +156,7 @@ struct stream_encoder_funcs {
void (*set_avmute)(
struct stream_encoder *enc, bool enable);
};
#endif /* STREAM_ENCODER_H_ */

3
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
Parādīt failu

@@ -140,6 +140,9 @@ struct timing_generator_funcs {
void (*program_timing)(struct timing_generator *tg,
const struct dc_crtc_timing *timing,
bool use_vbios);
void (*program_vline_interrupt)(struct timing_generator *optc,
const struct dc_crtc_timing *dc_crtc_timing,
unsigned long long vsync_delta);
bool (*enable_crtc)(struct timing_generator *tg);
bool (*disable_crtc)(struct timing_generator *tg);
bool (*is_counter_moving)(struct timing_generator *tg);

2
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h
Parādīt failu

@@ -252,7 +252,7 @@ struct transform_funcs {
struct transform *xfm_base,
enum surface_pixel_format format,
enum expansion_mode mode,
struct csc_transform input_csc_color_matrix,
struct dc_csc_transform input_csc_color_matrix,
enum dc_color_space input_color_space);
void (*ipp_full_bypass)(struct transform *xfm_base);

17
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
Parādīt failu

@@ -32,6 +32,8 @@
#include "inc/hw/link_encoder.h"
#include "core_status.h"
#define EDP_BACKLIGHT_RAMP_DISABLE_LEVEL 0xFFFFFFFF
enum pipe_gating_control {
PIPE_GATING_CONTROL_DISABLE = 0,
PIPE_GATING_CONTROL_ENABLE,
@@ -63,6 +65,7 @@ struct dchub_init_data;
struct dc_static_screen_events;
struct resource_pool;
struct resource_context;
struct stream_resource;
struct hw_sequencer_funcs {
@@ -93,6 +96,12 @@ struct hw_sequencer_funcs {
enum dc_color_space colorspace,
uint16_t *matrix);
void (*program_output_csc)(struct dc *dc,
struct pipe_ctx *pipe_ctx,
enum dc_color_space colorspace,
uint16_t *matrix,
int opp_id);
void (*update_plane_addr)(
const struct dc *dc,
struct pipe_ctx *pipe_ctx);
@@ -154,6 +163,11 @@ struct hw_sequencer_funcs {
struct dc *dc,
struct pipe_ctx *pipe,
bool lock);
void (*blank_pixel_data)(
struct dc *dc,
struct stream_resource *stream_res,
struct dc_stream_state *stream,
bool blank);
void (*set_bandwidth)(
struct dc *dc,
@@ -169,7 +183,7 @@ struct hw_sequencer_funcs {
void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx,
int num_pipes, const struct dc_static_screen_events *events);
enum dc_status (*prog_pixclk_crtc_otg)(
enum dc_status (*enable_stream_timing)(
struct pipe_ctx *pipe_ctx,
struct dc_state *context,
struct dc *dc);
@@ -201,6 +215,7 @@ struct hw_sequencer_funcs {
void (*set_cursor_position)(struct pipe_ctx *pipe);
void (*set_cursor_attribute)(struct pipe_ctx *pipe);
};
void color_space_to_black_color(

56
drivers/gpu/drm/amd/display/dc/inc/reg_helper.h
Parādīt failu

@@ -183,6 +183,36 @@
FN(reg_name, f4), v4, \
FN(reg_name, f5), v5)
#define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
generic_reg_get6(CTX, REG(reg_name), \
FN(reg_name, f1), v1, \
FN(reg_name, f2), v2, \
FN(reg_name, f3), v3, \
FN(reg_name, f4), v4, \
FN(reg_name, f5), v5, \
FN(reg_name, f6), v6)
#define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
generic_reg_get7(CTX, REG(reg_name), \
FN(reg_name, f1), v1, \
FN(reg_name, f2), v2, \
FN(reg_name, f3), v3, \
FN(reg_name, f4), v4, \
FN(reg_name, f5), v5, \
FN(reg_name, f6), v6, \
FN(reg_name, f7), v7)
#define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
generic_reg_get8(CTX, REG(reg_name), \
FN(reg_name, f1), v1, \
FN(reg_name, f2), v2, \
FN(reg_name, f3), v3, \
FN(reg_name, f4), v4, \
FN(reg_name, f5), v5, \
FN(reg_name, f6), v6, \
FN(reg_name, f7), v7, \
FN(reg_name, f8), v8)
/* macro to poll and wait for a register field to read back given value */
#define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try) \
@@ -389,4 +419,30 @@ uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
uint8_t shift6, uint32_t mask6, uint32_t *field_value6);
uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
uint8_t shift7, uint32_t mask7, uint32_t *field_value7);
uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
uint8_t shift8, uint32_t mask8, uint32_t *field_value8);
#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */

4
drivers/gpu/drm/amd/display/dc/inc/resource.h
Parādīt failu

@@ -139,10 +139,6 @@ bool resource_validate_attach_surfaces(
struct dc_state *context,
const struct resource_pool *pool);
void validate_guaranteed_copy_streams(
struct dc_state *context,
int max_streams);
void resource_validate_ctx_update_pointer_after_copy(
const struct dc_state *src_ctx,
struct dc_state *dst_ctx);

7
drivers/gpu/drm/amd/display/dc/irq_types.h
Parādīt failu

@@ -135,6 +135,13 @@ enum dc_irq_source {
DC_IRQ_SOURCE_VBLANK5,
DC_IRQ_SOURCE_VBLANK6,
DC_IRQ_SOURCE_DC1_VLINE0,
DC_IRQ_SOURCE_DC2_VLINE0,
DC_IRQ_SOURCE_DC3_VLINE0,
DC_IRQ_SOURCE_DC4_VLINE0,
DC_IRQ_SOURCE_DC5_VLINE0,
DC_IRQ_SOURCE_DC6_VLINE0,
DAL_IRQ_SOURCES_NUMBER
};