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ARM: dts: stm32: Fix PHY post-reset delay on Avenger96

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[ Upstream commit ef2d90708883f4025a801feb0ba8411a7a4387e1 ]

Per KSZ9031RNX PHY datasheet FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING
Note 2: After the de-assertion of reset, wait a minimum of 100 μs before
starting programming on the MIIM (MDC/MDIO) interface.

Add 1ms post-reset delay to guarantee this figure.

Fixes: 010ca9fe50 ("ARM: dts: stm32: Add missing ethernet PHY reset on AV96")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Marek Vasut
2022-03-25 18:58:51 +01:00
committed by Greg Kroah-Hartman
parent b439f7addd
commit 95000ae680
1 changed files with 1 additions and 0 deletions
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arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
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@@ -141,6 +141,7 @@
compatible = "snps,dwmac-mdio"; compatible = "snps,dwmac-mdio";
reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>; reset-delay-us = <1000>;
reset-post-delay-us = <1000>;
phy0: ethernet-phy@7 { phy0: ethernet-phy@7 {
reg = <7>; reg = <7>;