Merge tag 'tty-3.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull TTY updates from Greg Kroah-Hartman: "Here's the big TTY/serial driver pull request for the 3.5-rc1 merge window. Nothing major in here, just lots of incremental changes from Alan and Jiri reworking some tty core things to behave better and to get a more solid grasp on some of the nasty tty locking issues. There are a few tty and serial driver updates in here as well. All of this has been in the linux-next releases for a while with no problems. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>" * tag 'tty-3.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (115 commits) serial: bfin_uart: Make MMR access compatible with 32 bits bf609 style controller. serial: bfin_uart: RTS and CTS MMRs can be either 16-bit width or 32-bit width. serial: bfin_uart: narrow the reboot condition in DMA tx interrupt serial: bfin_uart: Adapt bf5xx serial driver to bf60x serial4 controller. Revert "serial_core: Update buffer overrun statistics." tty: hvc_xen: NULL dereference on allocation failure tty: Fix LED error return tty: Allow uart_register/unregister/register tty: move global ldisc idle waitqueue to the individual ldisc serial8250-em: Add DT support serial8250-em: clk_get() IS_ERR() error handling fix serial_core: Update buffer overrun statistics. tty: drop the pty lock during hangup cris: fix missing tty arg in wait_event_interruptible_tty call tty/amiserial: Add missing argument for tty_unlock() tty_lock: Localise the lock pty: Lock the devpts bits privately tty_lock: undo the old tty_lock use on the ctty serial8250-em: Emma Mobile UART driver V2 Add missing call to uart_update_timeout() ...
This commit is contained in:
@@ -68,30 +68,6 @@
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#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
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#define UART_DUMMY_DR_RX (1 << 16)
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#define UART_WA_SAVE_NR 14
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static void pl011_lockup_wa(unsigned long data);
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static const u32 uart_wa_reg[UART_WA_SAVE_NR] = {
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ST_UART011_DMAWM,
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ST_UART011_TIMEOUT,
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ST_UART011_LCRH_RX,
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UART011_IBRD,
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UART011_FBRD,
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ST_UART011_LCRH_TX,
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UART011_IFLS,
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ST_UART011_XFCR,
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ST_UART011_XON1,
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ST_UART011_XON2,
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ST_UART011_XOFF1,
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ST_UART011_XOFF2,
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UART011_CR,
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UART011_IMSC
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};
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static u32 uart_wa_regdata[UART_WA_SAVE_NR];
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static DECLARE_TASKLET(pl011_lockup_tlet, pl011_lockup_wa, 0);
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/* There is by now at least one vendor with differing details, so handle it */
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struct vendor_data {
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unsigned int ifls;
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@@ -101,6 +77,7 @@ struct vendor_data {
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bool oversampling;
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bool interrupt_may_hang; /* vendor-specific */
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bool dma_threshold;
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bool cts_event_workaround;
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};
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static struct vendor_data vendor_arm = {
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@@ -110,6 +87,7 @@ static struct vendor_data vendor_arm = {
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.lcrh_rx = UART011_LCRH,
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.oversampling = false,
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.dma_threshold = false,
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.cts_event_workaround = false,
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};
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static struct vendor_data vendor_st = {
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@@ -120,6 +98,7 @@ static struct vendor_data vendor_st = {
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.oversampling = true,
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.interrupt_may_hang = true,
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.dma_threshold = true,
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.cts_event_workaround = true,
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};
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static struct uart_amba_port *amba_ports[UART_NR];
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@@ -1055,69 +1034,6 @@ static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
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#define pl011_dma_flush_buffer NULL
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#endif
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/*
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* pl011_lockup_wa
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* This workaround aims to break the deadlock situation
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* when after long transfer over uart in hardware flow
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* control, uart interrupt registers cannot be cleared.
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* Hence uart transfer gets blocked.
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*
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* It is seen that during such deadlock condition ICR
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* don't get cleared even on multiple write. This leads
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* pass_counter to decrease and finally reach zero. This
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* can be taken as trigger point to run this UART_BT_WA.
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*
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*/
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static void pl011_lockup_wa(unsigned long data)
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{
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struct uart_amba_port *uap = amba_ports[0];
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void __iomem *base = uap->port.membase;
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struct circ_buf *xmit = &uap->port.state->xmit;
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struct tty_struct *tty = uap->port.state->port.tty;
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int buf_empty_retries = 200;
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int loop;
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/* Stop HCI layer from submitting data for tx */
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tty->hw_stopped = 1;
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while (!uart_circ_empty(xmit)) {
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if (buf_empty_retries-- == 0)
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break;
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udelay(100);
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}
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/* Backup registers */
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for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
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uart_wa_regdata[loop] = readl(base + uart_wa_reg[loop]);
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/* Disable UART so that FIFO data is flushed out */
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writew(0x00, uap->port.membase + UART011_CR);
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/* Soft reset UART module */
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if (uap->port.dev->platform_data) {
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struct amba_pl011_data *plat;
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plat = uap->port.dev->platform_data;
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if (plat->reset)
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plat->reset();
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}
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/* Restore registers */
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for (loop = 0; loop < UART_WA_SAVE_NR; loop++)
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writew(uart_wa_regdata[loop] ,
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uap->port.membase + uart_wa_reg[loop]);
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/* Initialise the old status of the modem signals */
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uap->old_status = readw(uap->port.membase + UART01x_FR) &
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UART01x_FR_MODEM_ANY;
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if (readl(base + UART011_MIS) & 0x2)
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printk(KERN_EMERG "UART_BT_WA: ***FAILED***\n");
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/* Start Tx/Rx */
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tty->hw_stopped = 0;
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}
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static void pl011_stop_tx(struct uart_port *port)
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{
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struct uart_amba_port *uap = (struct uart_amba_port *)port;
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@@ -1246,12 +1162,26 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
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unsigned long flags;
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unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
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int handled = 0;
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unsigned int dummy_read;
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spin_lock_irqsave(&uap->port.lock, flags);
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status = readw(uap->port.membase + UART011_MIS);
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if (status) {
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do {
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if (uap->vendor->cts_event_workaround) {
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/* workaround to make sure that all bits are unlocked.. */
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writew(0x00, uap->port.membase + UART011_ICR);
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/*
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* WA: introduce 26ns(1 uart clk) delay before W1C;
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* single apb access will incur 2 pclk(133.12Mhz) delay,
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* so add 2 dummy reads
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*/
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dummy_read = readw(uap->port.membase + UART011_ICR);
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dummy_read = readw(uap->port.membase + UART011_ICR);
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}
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writew(status & ~(UART011_TXIS|UART011_RTIS|
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UART011_RXIS),
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uap->port.membase + UART011_ICR);
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@@ -1268,11 +1198,8 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
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if (status & UART011_TXIS)
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pl011_tx_chars(uap);
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if (pass_counter-- == 0) {
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if (uap->interrupt_may_hang)
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tasklet_schedule(&pl011_lockup_tlet);
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if (pass_counter-- == 0)
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break;
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}
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status = readw(uap->port.membase + UART011_MIS);
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} while (status != 0);
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