Merge tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie: "This is the main pull request for drm for 4.10 kernel. New drivers: - ZTE VOU display driver (zxdrm) - Amlogic Meson Graphic Controller GXBB/GXL/GXM SoCs (meson) - MXSFB support (mxsfb) Core: - Format handling has been reworked - Better atomic state debugging - drm_mm leak debugging - Atomic explicit fencing support - fbdev helper ops - Documentation updates - MST fbcon fixes Bridge: - Silicon Image SiI8620 driver Panel: - Add support for new simple panels i915: - GVT Device model - Better HDMI2.0 support on skylake - More watermark fixes - GPU idling rework for suspend/resume - DP Audio workarounds - Scheduler prep-work - Opregion CADL handling - GPU scheduler and priority boosting amdgfx/radeon: - Support for virtual devices - New VM manager for non-contig VRAM buffers - UVD powergating - SI register header cleanup - Cursor fixes - Powermanagement fixes nouveau: - Powermangement reworks for better voltage/clock changes - Atomic modesetting support - Displayport Multistream (MST) support. - GP102/104 hang and cursor fixes - GP106 support hisilicon: - hibmc support (BMC chip for aarch64 servers) armada: - add tracing support for overlay change - refactor plane support - de-midlayer the driver omapdrm: - Timing code cleanups rcar-du: - R8A7792/R8A7796 support - Misc fixes. sunxi: - A31 SoC display engine support imx-drm: - YUV format support - Cleanup plane atomic update mali-dp: - Misc fixes dw-hdmi: - Add support for HDMI i2c master controller tegra: - IOMMU support fixes - Error handling fixes tda998x: - Fix connector registration - Improved robustness - Fix infoframe/audio compliance virtio: - fix busid issues - allocate more vbufs qxl: - misc fixes and cleanups. vc4: - Fragment shader threading - ETC1 support - VEC (tv-out) support msm: - A5XX GPU support - Lots of atomic changes tilcdc: - Misc fixes and cleanups. etnaviv: - Fix dma-buf export path - DRAW_INSTANCED support - fix driver on i.MX6SX exynos: - HDMI refactoring fsl-dcu: - fbdev changes" * tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux: (1343 commits) drm/nouveau/kms/nv50: fix atomic regression on original G80 drm/nouveau/bl: Do not register interface if Apple GMUX detected drm/nouveau/bl: Assign different names to interfaces drm/nouveau/bios/dp: fix handling of LevelEntryTableIndex on DP table 4.2 drm/nouveau/ltc: protect clearing of comptags with mutex drm/nouveau/gr/gf100-: handle GPC/TPC/MPC trap drm/nouveau/core: recognise GP106 chipset drm/nouveau/ttm: wait for bo fence to signal before unmapping vmas drm/nouveau/gr/gf100-: FECS intr handling is not relevant on proprietary ucode drm/nouveau/gr/gf100-: properly ack all FECS error interrupts drm/nouveau/fifo/gf100-: recover from host mmu faults drm: Add fake controlD* symlinks for backwards compat drm/vc4: Don't use drm_put_dev drm/vc4: Document VEC DT binding drm/vc4: Add support for the VEC (Video Encoder) IP drm: Add TV connector states to drm_connector_state drm: Turn DRM_MODE_SUBCONNECTOR_xx definitions into an enum drm/vc4: Fix ->clock_select setting for the VEC encoder drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well drm/amdgpu: use pin rather than pin_restricted in a few cases ...
This commit is contained in:
Linus Torvalds
@@ -50,6 +50,7 @@ extern "C" {
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#define DRM_AMDGPU_WAIT_CS 0x09
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#define DRM_AMDGPU_GEM_OP 0x10
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#define DRM_AMDGPU_GEM_USERPTR 0x11
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#define DRM_AMDGPU_WAIT_FENCES 0x12
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#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
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#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
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@@ -63,6 +64,7 @@ extern "C" {
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#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
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#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
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#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
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#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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@@ -81,6 +83,8 @@ extern "C" {
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#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
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/* Flag that create shadow bo(GTT) while allocating vram bo */
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#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
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/* Flag that allocating the BO should use linear VRAM */
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#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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@@ -305,6 +309,32 @@ union drm_amdgpu_wait_cs {
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struct drm_amdgpu_wait_cs_out out;
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};
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struct drm_amdgpu_fence {
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__u32 ctx_id;
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__u32 ip_type;
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__u32 ip_instance;
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__u32 ring;
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__u64 seq_no;
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};
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struct drm_amdgpu_wait_fences_in {
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/** This points to uint64_t * which points to fences */
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__u64 fences;
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__u32 fence_count;
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__u32 wait_all;
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__u64 timeout_ns;
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};
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struct drm_amdgpu_wait_fences_out {
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__u32 status;
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__u32 first_signaled;
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};
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union drm_amdgpu_wait_fences {
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struct drm_amdgpu_wait_fences_in in;
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struct drm_amdgpu_wait_fences_out out;
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};
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#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
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#define AMDGPU_GEM_OP_SET_PLACEMENT 1
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@@ -436,6 +466,7 @@ struct drm_amdgpu_cs_chunk_data {
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*
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*/
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#define AMDGPU_IDS_FLAGS_FUSION 0x1
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#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
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/* indicate if acceleration can be working */
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#define AMDGPU_INFO_ACCEL_WORKING 0x00
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@@ -487,6 +518,16 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
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/* number of TTM buffer evictions */
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#define AMDGPU_INFO_NUM_EVICTIONS 0x18
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/* Query memory about VRAM and GTT domains */
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#define AMDGPU_INFO_MEMORY 0x19
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/* Query vce clock table */
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#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
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/* Query vbios related information */
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#define AMDGPU_INFO_VBIOS 0x1B
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/* Subquery id: Query vbios size */
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#define AMDGPU_INFO_VBIOS_SIZE 0x1
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/* Subquery id: Query vbios image */
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#define AMDGPU_INFO_VBIOS_IMAGE 0x2
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@@ -545,6 +586,11 @@ struct drm_amdgpu_info {
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} read_mmr_reg;
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struct drm_amdgpu_query_fw query_fw;
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struct {
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__u32 type;
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__u32 offset;
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} vbios_info;
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};
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};
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@@ -572,6 +618,34 @@ struct drm_amdgpu_info_vram_gtt {
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__u64 gtt_size;
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};
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struct drm_amdgpu_heap_info {
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/** max. physical memory */
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__u64 total_heap_size;
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/** Theoretical max. available memory in the given heap */
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__u64 usable_heap_size;
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/**
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* Number of bytes allocated in the heap. This includes all processes
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* and private allocations in the kernel. It changes when new buffers
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* are allocated, freed, and moved. It cannot be larger than
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* heap_size.
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*/
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__u64 heap_usage;
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/**
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* Theoretical possible max. size of buffer which
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* could be allocated in the given heap
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*/
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__u64 max_allocation;
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};
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struct drm_amdgpu_memory_info {
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struct drm_amdgpu_heap_info vram;
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struct drm_amdgpu_heap_info cpu_accessible_vram;
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struct drm_amdgpu_heap_info gtt;
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};
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struct drm_amdgpu_info_firmware {
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__u32 ver;
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__u32 feature;
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@@ -645,6 +719,24 @@ struct drm_amdgpu_info_hw_ip {
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__u32 _pad;
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};
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#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
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struct drm_amdgpu_info_vce_clock_table_entry {
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/** System clock */
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__u32 sclk;
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/** Memory clock */
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__u32 mclk;
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/** VCE clock */
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__u32 eclk;
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__u32 pad;
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};
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struct drm_amdgpu_info_vce_clock_table {
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struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
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__u32 num_valid_entries;
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__u32 pad;
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};
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/*
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* Supported GPU families
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*/
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@@ -47,7 +47,15 @@ extern "C" {
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#define DRM_MODE_TYPE_DRIVER (1<<6)
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/* Video mode flags */
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/* bit compatible with the xorg definitions. */
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/* bit compatible with the xrandr RR_ definitions (bits 0-13)
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*
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* ABI warning: Existing userspace really expects
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* the mode flags to match the xrandr definitions. Any
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* changes that don't match the xrandr definitions will
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* likely need a new client cap or some other mechanism
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* to avoid breaking existing userspace. This includes
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* allocating new flags in the previously unused bits!
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*/
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#define DRM_MODE_FLAG_PHSYNC (1<<0)
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#define DRM_MODE_FLAG_NHSYNC (1<<1)
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#define DRM_MODE_FLAG_PVSYNC (1<<2)
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@@ -77,6 +85,19 @@ extern "C" {
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#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
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#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
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/* Picture aspect ratio options */
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#define DRM_MODE_PICTURE_ASPECT_NONE 0
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#define DRM_MODE_PICTURE_ASPECT_4_3 1
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#define DRM_MODE_PICTURE_ASPECT_16_9 2
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/* Aspect ratio flag bitmask (4 bits 22:19) */
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#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)
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#define DRM_MODE_FLAG_PIC_AR_NONE \
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(DRM_MODE_PICTURE_ASPECT_NONE<<19)
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#define DRM_MODE_FLAG_PIC_AR_4_3 \
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(DRM_MODE_PICTURE_ASPECT_4_3<<19)
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#define DRM_MODE_FLAG_PIC_AR_16_9 \
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(DRM_MODE_PICTURE_ASPECT_16_9<<19)
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/* DPMS flags */
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/* bit compatible with the xorg definitions. */
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@@ -92,11 +113,6 @@ extern "C" {
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#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
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#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
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/* Picture aspect ratio options */
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#define DRM_MODE_PICTURE_ASPECT_NONE 0
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#define DRM_MODE_PICTURE_ASPECT_4_3 1
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#define DRM_MODE_PICTURE_ASPECT_16_9 2
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/* Dithering mode options */
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#define DRM_MODE_DITHERING_OFF 0
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#define DRM_MODE_DITHERING_ON 1
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@@ -220,14 +236,16 @@ struct drm_mode_get_encoder {
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/* This is for connectors with multiple signal types. */
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/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
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#define DRM_MODE_SUBCONNECTOR_Automatic 0
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#define DRM_MODE_SUBCONNECTOR_Unknown 0
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#define DRM_MODE_SUBCONNECTOR_DVID 3
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#define DRM_MODE_SUBCONNECTOR_DVIA 4
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#define DRM_MODE_SUBCONNECTOR_Composite 5
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#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
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#define DRM_MODE_SUBCONNECTOR_Component 8
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#define DRM_MODE_SUBCONNECTOR_SCART 9
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enum drm_mode_subconnector {
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DRM_MODE_SUBCONNECTOR_Automatic = 0,
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DRM_MODE_SUBCONNECTOR_Unknown = 0,
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DRM_MODE_SUBCONNECTOR_DVID = 3,
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DRM_MODE_SUBCONNECTOR_DVIA = 4,
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DRM_MODE_SUBCONNECTOR_Composite = 5,
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DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
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DRM_MODE_SUBCONNECTOR_Component = 8,
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DRM_MODE_SUBCONNECTOR_SCART = 9,
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};
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#define DRM_MODE_CONNECTOR_Unknown 0
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#define DRM_MODE_CONNECTOR_VGA 1
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@@ -392,17 +410,20 @@ struct drm_mode_fb_cmd2 {
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* offsets[1]. Note that offsets[0] will generally
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* be 0 (but this is not required).
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*
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* To accommodate tiled, compressed, etc formats, a per-plane
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* To accommodate tiled, compressed, etc formats, a
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* modifier can be specified. The default value of zero
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* indicates "native" format as specified by the fourcc.
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* Vendor specific modifier token. This allows, for example,
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* different tiling/swizzling pattern on different planes.
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* See discussion above of DRM_FORMAT_MOD_xxx.
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* Vendor specific modifier token. Note that even though
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* it looks like we have a modifier per-plane, we in fact
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* do not. The modifier for each plane must be identical.
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* Thus all combinations of different data layouts for
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* multi plane formats must be enumerated as separate
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* modifiers.
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*/
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__u32 handles[4];
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__u32 pitches[4]; /* pitch for each plane */
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__u32 offsets[4]; /* offset of each plane */
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__u64 modifier[4]; /* ie, tiling, compressed (per plane) */
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__u64 modifier[4]; /* ie, tiling, compress */
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};
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#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
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@@ -389,6 +389,11 @@ typedef struct drm_i915_irq_wait {
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#define I915_PARAM_MIN_EU_IN_POOL 39
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#define I915_PARAM_MMAP_GTT_VERSION 40
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/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
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* priorities and the driver will attempt to execute batches in priority order.
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*/
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#define I915_PARAM_HAS_SCHEDULER 41
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typedef struct drm_i915_getparam {
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__s32 param;
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/*
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@@ -2,17 +2,24 @@
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __MSM_DRM_H__
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@@ -286,6 +286,8 @@ struct drm_vc4_get_hang_state {
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#define DRM_VC4_PARAM_V3D_IDENT1 1
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#define DRM_VC4_PARAM_V3D_IDENT2 2
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#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
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#define DRM_VC4_PARAM_SUPPORTS_ETC1 4
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#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5
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struct drm_vc4_get_param {
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__u32 param;
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Block a user