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Merge tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/drivers

Browse Source 
soc: amlogic: driver updates for v5.8
- support GX SoCs in the EE power-controller driver

* tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  soc: amlogic: meson-ee-pwrc: add support for the Meson GX SoCs
  soc: amlogic: meson-ee-pwrc: add support for Meson8/Meson8b/Meson8m2
  dt-bindings: power: meson-ee-pwrc: add support for the Meson GX SoCs
  dt-bindings: power: meson-ee-pwrc: add support for Meson8/8b/8m2

Link: https://lore.kernel.org/r/5ec6f570.1c69fb81.a3753.711b@mx.google.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2020-05-25 16:57:24 +02:00
parent 6d83d800b2 53773f2dfd
commit 93f9fb1e4a
4 changed files with 214 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

102
Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
View File

@@ -23,33 +23,31 @@ description: |+
properties: properties:
compatible: compatible:
enum: enum:
- amlogic,meson8-pwrc
- amlogic,meson8b-pwrc
- amlogic,meson8m2-pwrc
- amlogic,meson-gxbb-pwrc
- amlogic,meson-g12a-pwrc - amlogic,meson-g12a-pwrc
- amlogic,meson-sm1-pwrc - amlogic,meson-sm1-pwrc
clocks: clocks:
minItems: 2 minItems: 1
maxItems: 2
clock-names: clock-names:
minItems: 1
maxItems: 2
items: items:
- const: vpu - const: vpu
- const: vapb - const: vapb
resets: resets:
minItems: 11 minItems: 11
maxItems: 12
reset-names: reset-names:
items: minItems: 11
- const: viu maxItems: 12
- const: venc
- const: vcbus
- const: bt656
- const: rdma
- const: venci
- const: vencp
- const: vdac
- const: vdi6
- const: vencl
- const: vid_lock
"#power-domain-cells": "#power-domain-cells":
const: 1 const: 1
@@ -59,12 +57,86 @@ properties:
allOf: allOf:
- $ref: /schemas/types.yaml#/definitions/phandle - $ref: /schemas/types.yaml#/definitions/phandle
allOf:
- if:
properties:
compatible:
enum:
- amlogic,meson8b-pwrc
- amlogic,meson8m2-pwrc
then:
properties:
reset-names:
items:
- const: dblk
- const: pic_dc
- const: hdmi_apb
- const: hdmi_system
- const: venci
- const: vencp
- const: vdac
- const: vencl
- const: viu
- const: venc
- const: rdma
required:
- resets
- reset-names
- if:
properties:
compatible:
enum:
- amlogic,meson-gxbb-pwrc
then:
properties:
reset-names:
items:
- const: viu
- const: venc
- const: vcbus
- const: bt656
- const: dvin
- const: rdma
- const: venci
- const: vencp
- const: vdac
- const: vdi6
- const: vencl
- const: vid_lock
required:
- resets
- reset-names
- if:
properties:
compatible:
enum:
- amlogic,meson-g12a-pwrc
- amlogic,meson-sm1-pwrc
then:
properties:
reset-names:
items:
- const: viu
- const: venc
- const: vcbus
- const: bt656
- const: rdma
- const: venci
- const: vencp
- const: vdac
- const: vdi6
- const: vencl
- const: vid_lock
required:
- resets
- reset-names
required: required:
- compatible - compatible
- clocks - clocks
- clock-names - clock-names
- resets
- reset-names
- "#power-domain-cells" - "#power-domain-cells"
- amlogic,ao-sysctrl - amlogic,ao-sysctrl

112
drivers/soc/amlogic/meson-ee-pwrc.c
View File

@@ -14,13 +14,23 @@
#include <linux/reset-controller.h> #include <linux/reset-controller.h>
#include <linux/reset.h> #include <linux/reset.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <dt-bindings/power/meson8-power.h>
#include <dt-bindings/power/meson-g12a-power.h> #include <dt-bindings/power/meson-g12a-power.h>
#include <dt-bindings/power/meson-gxbb-power.h>
#include <dt-bindings/power/meson-sm1-power.h> #include <dt-bindings/power/meson-sm1-power.h>
/* AO Offsets */ /* AO Offsets */
#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2) #define GX_AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
#define AO_RTI_GEN_PWR_ISO0 (0x3b << 2) #define GX_AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
/*
* Meson8/Meson8b/Meson8m2 only expose the power management registers of the
* AO-bus as syscon. 0x3a from GX translates to 0x02, 0x3b translates to 0x03
* and so on.
*/
#define MESON8_AO_RTI_GEN_PWR_SLEEP0 (0x02 << 2)
#define MESON8_AO_RTI_GEN_PWR_ISO0 (0x03 << 2)
/* HHI Offsets */ /* HHI Offsets */
@@ -66,18 +76,25 @@ struct meson_ee_pwrc_domain_data {
/* TOP Power Domains */ /* TOP Power Domains */
static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = { static struct meson_ee_pwrc_top_domain gx_pwrc_vpu = {
.sleep_reg = AO_RTI_GEN_PWR_SLEEP0, .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
.sleep_mask = BIT(8), .sleep_mask = BIT(8),
.iso_reg = AO_RTI_GEN_PWR_SLEEP0, .iso_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
.iso_mask = BIT(9),
};
static struct meson_ee_pwrc_top_domain meson8_pwrc_vpu = {
.sleep_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
.sleep_mask = BIT(8),
.iso_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
.iso_mask = BIT(9), .iso_mask = BIT(9),
}; };
#define SM1_EE_PD(__bit) \ #define SM1_EE_PD(__bit) \
{ \ { \
.sleep_reg = AO_RTI_GEN_PWR_SLEEP0, \ .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \
.sleep_mask = BIT(__bit), \ .sleep_mask = BIT(__bit), \
.iso_reg = AO_RTI_GEN_PWR_ISO0, \ .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \
.iso_mask = BIT(__bit), \ .iso_mask = BIT(__bit), \
} }
@@ -124,10 +141,26 @@ static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
VPU_HHI_MEMPD(HHI_MEM_PD_REG0), VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
}; };
static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = { static struct meson_ee_pwrc_mem_domain gxbb_pwrc_mem_vpu[] = {
VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
};
static struct meson_ee_pwrc_mem_domain meson_pwrc_mem_eth[] = {
{ HHI_MEM_PD_REG0, GENMASK(3, 2) }, { HHI_MEM_PD_REG0, GENMASK(3, 2) },
}; };
static struct meson_ee_pwrc_mem_domain meson8_pwrc_audio_dsp_mem[] = {
{ HHI_MEM_PD_REG0, GENMASK(1, 0) },
};
static struct meson_ee_pwrc_mem_domain meson8_pwrc_mem_vpu[] = {
VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
};
static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = { static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
VPU_MEMPD(HHI_VPU_MEM_PD_REG0), VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
VPU_MEMPD(HHI_VPU_MEM_PD_REG1), VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
@@ -199,9 +232,35 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain); static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain);
static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
[PWRC_G12A_VPU_ID] = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu, [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
pwrc_ee_get_power, 11, 2), pwrc_ee_get_power, 11, 2),
[PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth), [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
};
static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
[PWRC_GXBB_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu,
pwrc_ee_get_power, 12, 2),
[PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
};
static struct meson_ee_pwrc_domain_desc meson8_pwrc_domains[] = {
[PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu,
meson8_pwrc_mem_vpu, pwrc_ee_get_power,
0, 1),
[PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
meson_pwrc_mem_eth),
[PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
meson8_pwrc_audio_dsp_mem),
};
static struct meson_ee_pwrc_domain_desc meson8b_pwrc_domains[] = {
[PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu,
meson8_pwrc_mem_vpu, pwrc_ee_get_power,
11, 1),
[PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
meson_pwrc_mem_eth),
[PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
meson8_pwrc_audio_dsp_mem),
}; };
static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = { static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
@@ -216,7 +275,7 @@ static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
[PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d, [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
pwrc_ee_get_power), pwrc_ee_get_power),
[PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio), [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
[PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth), [PWRC_SM1_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
}; };
struct meson_ee_pwrc_domain { struct meson_ee_pwrc_domain {
@@ -470,12 +529,43 @@ static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
.domains = g12a_pwrc_domains, .domains = g12a_pwrc_domains,
}; };
static struct meson_ee_pwrc_domain_data meson_ee_gxbb_pwrc_data = {
.count = ARRAY_SIZE(gxbb_pwrc_domains),
.domains = gxbb_pwrc_domains,
};
static struct meson_ee_pwrc_domain_data meson_ee_m8_pwrc_data = {
.count = ARRAY_SIZE(meson8_pwrc_domains),
.domains = meson8_pwrc_domains,
};
static struct meson_ee_pwrc_domain_data meson_ee_m8b_pwrc_data = {
.count = ARRAY_SIZE(meson8b_pwrc_domains),
.domains = meson8b_pwrc_domains,
};
static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = { static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
.count = ARRAY_SIZE(sm1_pwrc_domains), .count = ARRAY_SIZE(sm1_pwrc_domains),
.domains = sm1_pwrc_domains, .domains = sm1_pwrc_domains,
}; };
static const struct of_device_id meson_ee_pwrc_match_table[] = { static const struct of_device_id meson_ee_pwrc_match_table[] = {
{
.compatible = "amlogic,meson8-pwrc",
.data = &meson_ee_m8_pwrc_data,
},
{
.compatible = "amlogic,meson8b-pwrc",
.data = &meson_ee_m8b_pwrc_data,
},
{
.compatible = "amlogic,meson8m2-pwrc",
.data = &meson_ee_m8b_pwrc_data,
},
{
.compatible = "amlogic,meson-gxbb-pwrc",
.data = &meson_ee_gxbb_pwrc_data,
},
{ {
.compatible = "amlogic,meson-g12a-pwrc", .compatible = "amlogic,meson-g12a-pwrc",
.data = &meson_ee_g12a_pwrc_data, .data = &meson_ee_g12a_pwrc_data,

13
include/dt-bindings/power/meson-gxbb-power.h Normal file
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@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (c) 2019 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*/
#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H
#define _DT_BINDINGS_MESON_GXBB_POWER_H
#define PWRC_GXBB_VPU_ID 0
#define PWRC_GXBB_ETHERNET_MEM_ID 1
#endif

13
include/dt-bindings/power/meson8-power.h Normal file
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@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (c) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
*/
#ifndef _DT_BINDINGS_MESON8_POWER_H
#define _DT_BINDINGS_MESON8_POWER_H
#define PWRC_MESON8_VPU_ID 0
#define PWRC_MESON8_ETHERNET_MEM_ID 1
#define PWRC_MESON8_AUDIO_DSP_MEM_ID 2
#endif /* _DT_BINDINGS_MESON8_POWER_H */