clk: hi3660: add clocks for video encoder, decoder and ISP

This patch adds more clocks for hi3660, including:
 - video encoder and decoder
 - ISP (Image Signal Processing)

Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Chen Jun
2017-05-26 15:38:20 +08:00
committed by Stephen Boyd
parent 73908acb1e
commit 9357c150e6
2 changed files with 57 additions and 0 deletions

View File

@@ -154,6 +154,23 @@
#define HI3660_CLK_DIV_UFSPERI 137
#define HI3660_CLK_DIV_AOMM 138
#define HI3660_CLK_DIV_IOPERI 139
#define HI3660_VENC_VOLT_HOLD 140
#define HI3660_PERI_VOLT_HOLD 141
#define HI3660_CLK_GATE_VENC 142
#define HI3660_CLK_GATE_VDEC 143
#define HI3660_CLK_ANDGT_VENC 144
#define HI3660_CLK_ANDGT_VDEC 145
#define HI3660_CLK_MUX_VENC 146
#define HI3660_CLK_MUX_VDEC 147
#define HI3660_CLK_DIV_VENC 148
#define HI3660_CLK_DIV_VDEC 149
#define HI3660_CLK_FAC_ISP_SNCLK 150
#define HI3660_CLK_GATE_ISP_SNCLK0 151
#define HI3660_CLK_GATE_ISP_SNCLK1 152
#define HI3660_CLK_GATE_ISP_SNCLK2 153
#define HI3660_CLK_ANGT_ISP_SNCLK 154
#define HI3660_CLK_MUX_ISP_SNCLK 155
#define HI3660_CLK_DIV_ISP_SNCLK 156
/* clk in pmuctrl */
#define HI3660_GATE_ABB_192 0