IB/ipath: Add support for 7220 receive queue changes
Newer HCAs have a HW option to write a sequence number to each receive queue entry and avoid a separate DMA of the tail register to memory. This patch adds support for these changes. Signed-off-by: Ralph Campbell <ralph.campbell@qlogic.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
这个提交包含在：
Ralph Campbell
@@ -41,7 +41,6 @@
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#include "ipath_kernel.h"
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#include "ipath_verbs.h"
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#include "ipath_common.h"
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static void ipath_update_pio_bufs(struct ipath_devdata *);
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@@ -720,6 +719,8 @@ static void __devexit cleanup_device(struct ipath_devdata *dd)
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tmpp = dd->ipath_pageshadow;
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dd->ipath_pageshadow = NULL;
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vfree(tmpp);
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dd->ipath_egrtidbase = NULL;
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}
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/*
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@@ -1078,18 +1079,17 @@ static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
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u32 eflags,
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u32 l,
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u32 etail,
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u64 *rc)
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__le32 *rhf_addr,
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struct ipath_message_header *hdr)
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{
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char emsg[128];
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struct ipath_message_header *hdr;
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get_rhf_errstring(eflags, emsg, sizeof emsg);
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hdr = (struct ipath_message_header *)&rc[1];
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ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
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"tlen=%x opcode=%x egridx=%x: %s\n",
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eflags, l,
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ipath_hdrget_rcv_type((__le32 *) rc),
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ipath_hdrget_length_in_bytes((__le32 *) rc),
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ipath_hdrget_rcv_type(rhf_addr),
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ipath_hdrget_length_in_bytes(rhf_addr),
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be32_to_cpu(hdr->bth[0]) >> 24,
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etail, emsg);
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@@ -1114,55 +1114,52 @@ static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
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*/
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void ipath_kreceive(struct ipath_portdata *pd)
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{
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u64 *rc;
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struct ipath_devdata *dd = pd->port_dd;
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__le32 *rhf_addr;
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void *ebuf;
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const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
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const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
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u32 etail = -1, l, hdrqtail;
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struct ipath_message_header *hdr;
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u32 eflags, i, etype, tlen, pkttot = 0, updegr=0, reloop=0;
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u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0;
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static u64 totcalls; /* stats, may eventually remove */
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if (!dd->ipath_hdrqtailptr) {
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ipath_dev_err(dd,
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"hdrqtailptr not set, can't do receives\n");
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goto bail;
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}
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int last;
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l = pd->port_head;
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hdrqtail = ipath_get_rcvhdrtail(pd);
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if (l == hdrqtail)
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goto bail;
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rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset;
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if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
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u32 seq = ipath_hdrget_seq(rhf_addr);
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if (seq != pd->port_seq_cnt)
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goto bail;
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hdrqtail = 0;
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} else {
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hdrqtail = ipath_get_rcvhdrtail(pd);
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if (l == hdrqtail)
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goto bail;
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smp_rmb();
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}
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reloop:
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for (i = 0; l != hdrqtail; i++) {
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u32 qp;
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u8 *bthbytes;
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rc = (u64 *) (pd->port_rcvhdrq + (l << 2));
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hdr = (struct ipath_message_header *)&rc[1];
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/*
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* could make a network order version of IPATH_KD_QP, and
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* do the obvious shift before masking to speed this up.
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*/
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qp = ntohl(hdr->bth[1]) & 0xffffff;
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bthbytes = (u8 *) hdr->bth;
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eflags = ipath_hdrget_err_flags((__le32 *) rc);
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etype = ipath_hdrget_rcv_type((__le32 *) rc);
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for (last = 0, i = 1; !last; i++) {
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hdr = dd->ipath_f_get_msgheader(dd, rhf_addr);
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eflags = ipath_hdrget_err_flags(rhf_addr);
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etype = ipath_hdrget_rcv_type(rhf_addr);
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/* total length */
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tlen = ipath_hdrget_length_in_bytes((__le32 *) rc);
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tlen = ipath_hdrget_length_in_bytes(rhf_addr);
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ebuf = NULL;
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if (etype != RCVHQ_RCV_TYPE_EXPECTED) {
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if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ?
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ipath_hdrget_use_egr_buf(rhf_addr) :
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(etype != RCVHQ_RCV_TYPE_EXPECTED)) {
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/*
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* it turns out that the chips uses an eager buffer
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* It turns out that the chip uses an eager buffer
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* for all non-expected packets, whether it "needs"
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* one or not. So always get the index, but don't
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* set ebuf (so we try to copy data) unless the
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* length requires it.
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*/
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etail = ipath_hdrget_index((__le32 *) rc);
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etail = ipath_hdrget_index(rhf_addr);
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updegr = 1;
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if (tlen > sizeof(*hdr) ||
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etype == RCVHQ_RCV_TYPE_NON_KD)
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ebuf = ipath_get_egrbuf(dd, etail);
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@@ -1173,75 +1170,91 @@ reloop:
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* packets; only ipathhdrerr should be set.
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*/
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if (etype != RCVHQ_RCV_TYPE_NON_KD && etype !=
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RCVHQ_RCV_TYPE_ERROR && ipath_hdrget_ipath_ver(
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hdr->iph.ver_port_tid_offset) !=
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IPS_PROTO_VERSION) {
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if (etype != RCVHQ_RCV_TYPE_NON_KD &&
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etype != RCVHQ_RCV_TYPE_ERROR &&
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ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) !=
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IPS_PROTO_VERSION)
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ipath_cdbg(PKT, "Bad InfiniPath protocol version "
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"%x\n", etype);
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}
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if (unlikely(eflags))
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ipath_rcv_hdrerr(dd, eflags, l, etail, rc);
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ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr);
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else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
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ipath_ib_rcv(dd->verbs_dev, rc + 1, ebuf, tlen);
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ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen);
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if (dd->ipath_lli_counter)
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dd->ipath_lli_counter--;
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} else if (etype == RCVHQ_RCV_TYPE_EAGER) {
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u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24;
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u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff;
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ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
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"qp=%x), len %x; ignored\n",
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etype, bthbytes[0], qp, tlen);
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etype, opcode, qp, tlen);
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}
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else if (etype == RCVHQ_RCV_TYPE_EAGER)
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ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
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"qp=%x), len %x; ignored\n",
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etype, bthbytes[0], qp, tlen);
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else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
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ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
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be32_to_cpu(hdr->bth[0]) & 0xff);
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be32_to_cpu(hdr->bth[0]) >> 24);
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else {
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/*
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* error packet, type of error unknown.
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* Probably type 3, but we don't know, so don't
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* even try to print the opcode, etc.
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* Usually caused by a "bad packet", that has no
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* BTH, when the LRH says it should.
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*/
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ipath_dbg("Error Pkt, but no eflags! egrbuf %x, "
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"len %x\nhdrq@%lx;hdrq+%x rhf: %llx; "
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"hdr %llx %llx %llx %llx %llx\n",
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etail, tlen, (unsigned long) rc, l,
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(unsigned long long) rc[0],
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(unsigned long long) rc[1],
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(unsigned long long) rc[2],
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(unsigned long long) rc[3],
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(unsigned long long) rc[4],
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(unsigned long long) rc[5]);
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ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
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" %x, len %x hdrq+%x rhf: %Lx\n",
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etail, tlen, l,
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le64_to_cpu(*(__le64 *) rhf_addr));
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if (ipath_debug & __IPATH_ERRPKTDBG) {
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u32 j, *d, dw = rsize-2;
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if (rsize > (tlen>>2))
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dw = tlen>>2;
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d = (u32 *)hdr;
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printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n",
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dw);
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for (j = 0; j < dw; j++)
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printk(KERN_DEBUG "%8x%s", d[j],
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(j%8) == 7 ? "\n" : " ");
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printk(KERN_DEBUG ".\n");
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}
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}
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l += rsize;
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if (l >= maxcnt)
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l = 0;
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if (etype != RCVHQ_RCV_TYPE_EXPECTED)
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updegr = 1;
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rhf_addr = (__le32 *) pd->port_rcvhdrq +
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l + dd->ipath_rhf_offset;
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if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
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u32 seq = ipath_hdrget_seq(rhf_addr);
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if (++pd->port_seq_cnt > 13)
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pd->port_seq_cnt = 1;
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if (seq != pd->port_seq_cnt)
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last = 1;
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} else if (l == hdrqtail)
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last = 1;
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/*
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* update head regs on last packet, and every 16 packets.
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* Reduce bus traffic, while still trying to prevent
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* rcvhdrq overflows, for when the queue is nearly full
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*/
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if (l == hdrqtail || (i && !(i&0xf))) {
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u64 lval;
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if (l == hdrqtail)
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/* request IBA6120 interrupt only on last */
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lval = dd->ipath_rhdrhead_intr_off | l;
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else
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lval = l;
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ipath_write_ureg(dd, ur_rcvhdrhead, lval, 0);
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if (last || !(i & 0xf)) {
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u64 lval = l;
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/* request IBA6120 and 7220 interrupt only on last */
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if (last)
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lval |= dd->ipath_rhdrhead_intr_off;
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ipath_write_ureg(dd, ur_rcvhdrhead, lval,
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pd->port_port);
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if (updegr) {
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ipath_write_ureg(dd, ur_rcvegrindexhead,
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etail, 0);
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etail, pd->port_port);
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updegr = 0;
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}
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}
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}
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if (!dd->ipath_rhdrhead_intr_off && !reloop) {
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if (!dd->ipath_rhdrhead_intr_off && !reloop &&
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!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
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/* IBA6110 workaround; we can have a race clearing chip
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* interrupt with another interrupt about to be delivered,
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* and can clear it before it is delivered on the GPIO
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@@ -1638,19 +1651,27 @@ int ipath_create_rcvhdrq(struct ipath_devdata *dd,
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ret = -ENOMEM;
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goto bail;
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}
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pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
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&dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail, GFP_KERNEL);
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if (!pd->port_rcvhdrtail_kvaddr) {
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ipath_dev_err(dd, "attempt to allocate 1 page "
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"for port %u rcvhdrqtailaddr failed\n",
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pd->port_port);
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ret = -ENOMEM;
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dma_free_coherent(&dd->pcidev->dev, amt,
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pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
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pd->port_rcvhdrq = NULL;
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goto bail;
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if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
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pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
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&dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
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GFP_KERNEL);
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if (!pd->port_rcvhdrtail_kvaddr) {
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ipath_dev_err(dd, "attempt to allocate 1 page "
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"for port %u rcvhdrqtailaddr "
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"failed\n", pd->port_port);
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ret = -ENOMEM;
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dma_free_coherent(&dd->pcidev->dev, amt,
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pd->port_rcvhdrq,
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pd->port_rcvhdrq_phys);
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pd->port_rcvhdrq = NULL;
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goto bail;
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}
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pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
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ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx "
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"physical\n", pd->port_port,
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(unsigned long long) phys_hdrqtail);
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}
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pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
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pd->port_rcvhdrq_size = amt;
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@@ -1660,10 +1681,6 @@ int ipath_create_rcvhdrq(struct ipath_devdata *dd,
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(unsigned long) pd->port_rcvhdrq_phys,
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(unsigned long) pd->port_rcvhdrq_size,
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pd->port_port);
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ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx physical\n",
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pd->port_port,
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(unsigned long long) phys_hdrqtail);
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}
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else
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ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
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@@ -1687,7 +1704,6 @@ int ipath_create_rcvhdrq(struct ipath_devdata *dd,
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ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
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pd->port_port, pd->port_rcvhdrq_phys);
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ret = 0;
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bail:
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return ret;
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}
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@@ -2222,7 +2238,7 @@ void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
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ipath_cdbg(VERBOSE, "free closed port %d "
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"ipath_port0_skbinfo @ %p\n", pd->port_port,
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skbinfo);
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for (e = 0; e < dd->ipath_rcvegrcnt; e++)
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for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++)
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if (skbinfo[e].skb) {
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pci_unmap_single(dd->pcidev, skbinfo[e].phys,
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dd->ipath_ibmaxlen,
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