dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit
Intel iDMA 32-bit doesn't have a concept of bus masters and thus there is no need to setup any kind of masters in the CTL_LO register. Moreover, the burst size for memory-to-memory transfer is not what is says, we need to have a corrected list of possible sizes. Note, that the size of 8 items, each of that up to 4 bytes, is chosen because of maximum of 1/2 FIFO, which is 64 bytes on Intel Merrifield. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
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revīziju iesūtīja
Vinod Koul

vecāks
91f0ff883e
revīzija
934891b0a1
@@ -4,6 +4,7 @@
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// Copyright (C) 2013,2018 Intel Corporation
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#include <linux/bitops.h>
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#include <linux/dmaengine.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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@@ -63,6 +64,22 @@ static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
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return DWC_CTLH_BLOCK_TS(block) << width;
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}
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static u32 dw_dma_prepare_ctllo(struct dw_dma_chan *dwc)
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{
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struct dma_slave_config *sconfig = &dwc->dma_sconfig;
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bool is_slave = is_slave_direction(dwc->direction);
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u8 smsize = is_slave ? sconfig->src_maxburst : DW_DMA_MSIZE_16;
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u8 dmsize = is_slave ? sconfig->dst_maxburst : DW_DMA_MSIZE_16;
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u8 p_master = dwc->dws.p_master;
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u8 m_master = dwc->dws.m_master;
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u8 dms = (dwc->direction == DMA_MEM_TO_DEV) ? p_master : m_master;
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u8 sms = (dwc->direction == DMA_DEV_TO_MEM) ? p_master : m_master;
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return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
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DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize) |
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DWC_CTLL_DMS(dms) | DWC_CTLL_SMS(sms);
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}
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static void dw_dma_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
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{
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/*
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@@ -99,6 +116,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
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dw->initialize_chan = dw_dma_initialize_chan;
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dw->suspend_chan = dw_dma_suspend_chan;
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dw->resume_chan = dw_dma_resume_chan;
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dw->prepare_ctllo = dw_dma_prepare_ctllo;
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dw->encode_maxburst = dw_dma_encode_maxburst;
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dw->bytes2block = dw_dma_bytes2block;
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dw->block2bytes = dw_dma_block2bytes;
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