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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull ARM SoC device tree updates from Arnd Bergmann:
 "There are close to 800 indivudal changesets in this branch again,
  which feels like a lot. There are particularly many changes for the
  NVIDIA Tegra platform this time, in fact more than it has seen in the
  two years since the v4.9 merge window. Aside from this, it's been
  fairly normal, with lots of changes going into Renesas R-CAR, NXP
  i.MX, Allwinner Sunxi, Samsung Exynos, and TI OMAP.

  Most of the changes are for adding new features into existing boards,
  for brevity I'm only mentioning completely new machines and SoCs here.
  For the first time I think we have (slightly) more new 64-bit hardware
  than 32-bit:

  Two boards get added for TI OMAP: Moxa UC-2101 is an industrial
  computer, see https://www.moxa.com/product/UC-2100.htm; GTA04A5 is a
  minor variation of the motherboards of the GTA04 phone, see
  https://shop.goldelico.com/wiki.php?page=GTA04A5

  Clearfog is a nice little board for quad-core Marvell Armada 8040
  network processor, see
  https://www.solid-run.com/marvell-armada-family/clearfog-gt-8k/

  Two additional server boards come with the Aspeed baseboard management
  controllers: Stardragon4800 is an arm64 reference platform made by HXT
  (based on Qualcomm's server chips), and TiogaPass is an Open Compute
  mainboard with x86 CPUs. Both use the ARM11 based AST2500 chips in the
  BMC.

  NXP i.MX usually sees a lot of new boards each release. This time
  there we only add one minor variant: ConnectCore 6UL SBC Pro uses the
  same SoM design as the ConnectCore 6UL SBC Express added later.
  However, there is a new chip, the i.MX6ULZ, which is an even smaller
  variant of the i.MX6ULL, with features removed. There is also support
  for the reference board design, the i.MX6ULZ 14x14 EVK.

  A new Raspberry Pi variant gets added, this one is the CM3 compute
  module based on bcm2837, it was launched in early 2017 but only now
  added to the kernel, both as 32-bit and as 64-bit files, as we tend to
  do for Raspberry Pi.

  On the Allwinner side, everything is again about cheap development
  boards, usually of the "Fruit Pi" variety. The new ones this time are:
   - Orange Pi Zero Plus2: http://www.orangepi.org/OrangePiZeroPlus2/
   - Orange Pi One Plus: http://www.orangepi.org/OrangePiOneplus/
   - Pine64 LTS: https://www.pine64.org/?product=pine-a64-lts
   - Banana Pi M2+ H5: http://www.banana-pi.org/m2plus.html
  The last one of these is now a 64-bit version of the earlier Banana Pi
  M2+ H3, with the same board layout.

  Similarly, for Rockchips, get get another variant of the 32-bit Asus
  Tinker board, the model 'S' based on rk3288, and three now boards
  based on the popular RK3399 chip:
   - ROC-RK3399-PC: https://libre.computer/products/boards/roc-rk3399-pc/
   - Rock960: https://www.96boards.org/product/rock960/
   - RockPro64: https://www.pine64.org/?page_id=61454
  These are all quite powerful boards with lots of RAM and I/O, and the
  RK3399 is the same chip used in several Chromebooks. Finally, we get
  support for the PX30 (aka rk3326) chip, which is based on the low-end
  64-bit Cortex-A35 CPU core. So far, only the evaluation board is
  supported.

  One more Banana Pi is added with a Mediatek chip: Banana Pi R64 is
  based on the MT7622 WiFi router platform, and the first product I've
  seen with a 64-bit Mediatek chip in that market:
  http://www.banana-pi.org/r64.html

  For HiSilicon, we gain support for the Hi3670 SoC and HiKey 370
  development board, which are similar to the Hi3660 and Hikey 360
  respectively, but add support for an NPU.

  Amlogic gets initial support for the Meson-G12A chip (S905D2), another
  quad-core Cortex-A53 SoC, and its evaluation platform. On the 32-bit
  side, we gain support for an actual end-user product, the Endless
  Computers Endless Mini based on Meson8b (S805), see
  https://endlessos.com/computers/

  Qualcomm adds support for their MSM8998 SoC and evaluation platform.
  This chip is commonly known as the Snapdragon 835, and is used in
  high-end phones as well as low-end laptops.

  For Renesas, a very bare support for the r8a774a1 (RZ/G2M) is added,
  but no boards for this one. However, we do add boards for the
  previously added r8a77965 (R-Car M3-N): the M3NULCB Kingfisher and the
  M3NULCB Starter Kit Pro.

  While we have lots of DT changes for NVIDIA to update the existing
  files, the only board that gets added is the Toradex Colibri T20 on
  Colibri Evaluation Board for the old Tegra2.

  Synaptics add support for their AS370 SoC, which is part of the
  (formerly Marvell) Berlin line of set-top-box chips used e.g. in the
  various Google Chromecast. Only the .dtsi gets added at this point, no
  actual machines"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (721 commits)
  ARM: dts: socfgpa: remove ethernet aliases from dtsi
  arm64: dts: stratix10: add ethernet aliases
  dt-bindings: mediatek: Add bindig for MT7623 IOMMU and SMI
  dt-bindings: mediatek: Add JPEG Decoder binding for MT7623
  dt-bindings: iommu: mediatek: Add binding for MT7623
  dt-bindings: clock: mediatek: add support for MT7623
  ARM: dts: mvebu: armada-385-db-88f6820-amc: auto-detect nand ECC properites
  ARM: dts: da850-lego-ev3: slow down A/DC as much as possible
  ARM: dts: da850-evm: Enable tca6416 on baseboard
  arm64: dts: uniphier: Add USB2 PHY nodes
  arm64: dts: uniphier: Add USB3 controller nodes
  ARM: dts: uniphier: Add USB2 PHY nodes
  ARM: dts: uniphier: Add USB3 controller nodes
  arm64: dts: meson-axg: s400: disable emmc
  arm64: dts: meson-axg: s400: add missing emmc pwrseq
  arm64: dts: clearfog-gt-8k: add PCIe slot description
  ARM: dts: at91: sama5d4_xplained: even nand memory partitions
  ARM: dts: at91: sama5d3_xplained: even nand memory partitions
  ARM: dts: at91: at91sam9x5cm: even nand memory partitions
  ARM: dts: at91: sama5d2_ptc_ek: fix bootloader env offsets
  ...
This commit is contained in:
Linus Torvalds
2018-10-29 15:05:20 -07:00
parent c38239b4be be59a3282c
commit 93335e5911
509 changed files with 29255 additions and 6396 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/actions/Makefile
View File

@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_ARCH_ACTIONS) += s700-cubieboard7.dtb
dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb

7
arch/arm64/boot/dts/actions/s700-cubieboard7.dts
View File

@@ -28,12 +28,6 @@
device_type = "memory";
reg = <0x1 0xe0000000 0x0 0x0>;
};
uart3_clk: uart3-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
};
};
&timer {
@@ -42,5 +36,4 @@
&uart3 {
status = "okay";
clocks = <&uart3_clk>;
};

21
arch/arm64/boot/dts/actions/s700.dtsi
View File

@@ -3,6 +3,7 @@
* Copyright (c) 2017 Andreas Färber
*/
#include <dt-bindings/clock/actions,s700-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -87,6 +88,12 @@
#clock-cells = <0>;
};
losc: losc {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -107,6 +114,7 @@
uart0: serial@e0120000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0120000 0x0 0x2000>;
clocks = <&cmu CLK_UART0>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -114,6 +122,7 @@
uart1: serial@e0122000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0122000 0x0 0x2000>;
clocks = <&cmu CLK_UART1>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -121,6 +130,7 @@
uart2: serial@e0124000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0124000 0x0 0x2000>;
clocks = <&cmu CLK_UART2>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -128,6 +138,7 @@
uart3: serial@e0126000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0126000 0x0 0x2000>;
clocks = <&cmu CLK_UART3>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -135,6 +146,7 @@
uart4: serial@e0128000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0128000 0x0 0x2000>;
clocks = <&cmu CLK_UART4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -142,6 +154,7 @@
uart5: serial@e012a000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012a000 0x0 0x2000>;
clocks = <&cmu CLK_UART5>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -149,10 +162,18 @@
uart6: serial@e012c000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012c000 0x0 0x2000>;
clocks = <&cmu CLK_UART6>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
cmu: clock-controller@e0168000 {
compatible = "actions,s700-cmu";
reg = <0x0 0xe0168000 0x0 0x1000>;
clocks = <&hosc>, <&losc>;
#clock-cells = <1>;
};
sps: power-controller@e01b0100 {
compatible = "actions,s700-sps";
reg = <0x0 0xe01b0100 0x0 0x100>;

224
arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
View File

@@ -1,7 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
/dts-v1/;
@@ -24,11 +23,223 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
uart5_clk: uart5-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
&i2c0 {
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_default>;
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_default>;
};
&i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_default>;
};
/*
* GPIO name legend: proper name = the GPIO line is used as GPIO
* NC = not connected (pin out but not routed from the chip to
* anything the board)
* "[PER]" = pin is muxed for [peripheral] (not GPIO)
* LSEC = Low Speed External Connector
* HSEC = High Speed External Connector
*
* Line names are taken from the schematic "Schematics Bubblegum96"
* version v1.0
*
* For the lines routed to the external connectors the
* lines are named after the 96Boards CE Specification 1.0,
* Appendix "Expansion Connector Signal Description".
*
* When the 96Boards naming of a line and the schematic name of
* the same line are in conflict, the 96Boards specification
* takes precedence, which means that the external UART on the
* LSEC is named UART0 while the schematic and SoC names this
* UART2. Only exception is the I2C lines for which the schematic
* naming has been preferred. This is only for the informational
* lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
* are the only ones actually used for GPIO.
*/
&pinctrl {
gpio-line-names =
"GPIO-A", /* GPIO_0, LSEC pin 23 */
"GPIO-B", /* GPIO_1, LSEC pin 24 */
"GPIO-C", /* GPIO_2, LSEC pin 25 */
"GPIO-D", /* GPIO_3, LSEC pin 26 */
"GPIO-E", /* GPIO_4, LSEC pin 27 */
"GPIO-F", /* GPIO_5, LSEC pin 28 */
"GPIO-G", /* GPIO_6, LSEC pin 29 */
"GPIO-H", /* GPIO_7, LSEC pin 30 */
"GPIO-I", /* GPIO_8, LSEC pin 31 */
"GPIO-J", /* GPIO_9, LSEC pin 32 */
"NC", /* GPIO_10 */
"NC", /* GPIO_11 */
"SIRQ2_1V8", /* GPIO_12 */
"PCM0_OUT", /* GPIO_13 */
"WIFI_LED", /* GPIO_14 */
"PCM0_SYNC", /* GPIO_15 */
"PCM0_CLK", /* GPIO_16 */
"PCM0_IN", /* GPIO_17 */
"BT_LED", /* GPIO_18 */
"LED0", /* GPIO_19 */
"LED1", /* GPIO_20 */
"JTAG_TCK", /* GPIO_21 */
"JTAG_TMS", /* GPIO_22 */
"JTAG_TDI", /* GPIO_23 */
"JTAG_TDO", /* GPIO_24 */
"[UART1_RxD]", /* GPIO_25, LSEC pin 13 */
"NC", /* GPIO_26 */
"[UART1_TxD]", /* GPIO_27, LSEC pin 11 */
"SD0_D0", /* GPIO_28 */
"SD0_D1", /* GPIO_29 */
"SD0_D2", /* GPIO_30 */
"SD0_D3", /* GPIO_31 */
"SD1_D0", /* GPIO_32 */
"SD1_D1", /* GPIO_33 */
"SD1_D2", /* GPIO_34 */
"SD1_D3", /* GPIO_35 */
"SD0_CMD", /* GPIO_36 */
"SD0_CLK", /* GPIO_37 */
"SD1_CMD", /* GPIO_38 */
"SD1_CLK", /* GPIO_39 */
"SPI0_SCLK", /* GPIO_40, LSEC pin 8 */
"SPI0_CS", /* GPIO_41, LSEC pin 12 */
"SPI0_DIN", /* GPIO_42, LSEC pin 10 */
"SPI0_DOUT", /* GPIO_43, LSEC pin 14 */
"I2C5_SDATA", /* GPIO_44, HSEC pin 36 */
"I2C5_SCLK", /* GPIO_45, HSEC pin 38 */
"UART0_RX", /* GPIO_46, LSEC pin 7 */
"UART0_TX", /* GPIO_47, LSEC pin 5 */
"UART0_RTSB", /* GPIO_48, LSEC pin 9 */
"UART0_CTSB", /* GPIO_49, LSEC pin 3 */
"I2C4_SCLK", /* GPIO_50, HSEC pin 32 */
"I2C4_SDATA", /* GPIO_51, HSEC pin 34 */
"I2C0_SCLK", /* GPIO_52 */
"I2C0_SDATA", /* GPIO_53 */
"I2C1_SCLK", /* GPIO_54, LSEC pin 15 */
"I2C1_SDATA", /* GPIO_55, LSEC pin 17 */
"I2C2_SCLK", /* GPIO_56, LSEC pin 19 */
"I2C2_SDATA", /* GPIO_57, LSEC pin 21 */
"CSI0_DN0", /* GPIO_58, HSEC pin 10 */
"CSI0_DP0", /* GPIO_59, HSEC pin 8 */
"CSI0_DN1", /* GPIO_60, HSEC pin 16 */
"CSI0_DP1", /* GPIO_61, HSEC pin 14 */
"CSI0_CN", /* GPIO_62, HSEC pin 4 */
"CSI0_CP", /* GPIO_63, HSEC pin 2 */
"CSI0_DN2", /* GPIO_64, HSEC pin 22 */
"CSI0_DP2", /* GPIO_65, HSEC pin 20 */
"CSI0_DN3", /* GPIO_66, HSEC pin 28 */
"CSI0_DP3", /* GPIO_67, HSEC pin 26 */
"[CLK0]", /* GPIO_68, HSEC pin 15 */
"CSI1_DN0", /* GPIO_69, HSEC pin 44 */
"CSI1_DP0", /* GPIO_70, HSEC pin 42 */
"CSI1_DN1", /* GPIO_71, HSEC pin 50 */
"CSI1_DP1", /* GPIO_72, HSEC pin 48 */
"CSI1_CN", /* GPIO_73, HSEC pin 56 */
"CSI1_CP", /* GPIO_74, HSEC pin 54 */
"[CLK1]", /* GPIO_75, HSEC pin 17 */
"[GPIOD0]", /* GPIO_76 */
"[GPIOD1]", /* GPIO_77 */
"BT_RST_N", /* GPIO_78 */
"EXT_DC_EN", /* GPIO_79 */
"[PCM_DI]", /* GPIO_80, LSEC pin 22 */
"[PCM_DO]", /* GPIO_81, LSEC pin 20 */
"[PCM_CLK]", /* GPIO_82, LSEC pin 18 */
"[PCM_FS]", /* GPIO_83, LSEC pin 16 */
"WAKE_BT", /* GPIO_84 */
"WL_REG_ON", /* GPIO_85 */
"NC", /* GPIO_86 */
"NC", /* GPIO_87 */
"NC", /* GPIO_88 */
"NC", /* GPIO_89 */
"NC", /* GPIO_90 */
"WIFI_WAKE", /* GPIO_91 */
"BT_WAKE", /* GPIO_92 */
"NC", /* GPIO_93 */
"OTG_EN2", /* GPIO_94 */
"OTG_EN", /* GPIO_95 */
"DSI_DP3", /* GPIO_96, HSEC pin 45 */
"DSI_DN3", /* GPIO_97, HSEC pin 47 */
"DSI_DP1", /* GPIO_98, HSEC pin 33 */
"DSI_DN1", /* GPIO_99, HSEC pin 35 */
"DSI_CP", /* GPIO_100, HSEC pin 21 */
"DSI_CN", /* GPIO_101, HSEC pin 23 */
"DSI_DP0", /* GPIO_102, HSEC pin 27 */
"DSI_DN0", /* GPIO_103, HSEC pin 29 */
"DSI_DP2", /* GPIO_104, HSEC pin 39 */
"DSI_DN2", /* GPIO_105, HSEC pin 41 */
"N0_D0", /* GPIO_106 */
"N0_D1", /* GPIO_107 */
"N0_D2", /* GPIO_108 */
"N0_D3", /* GPIO_109 */
"N0_D4", /* GPIO_110 */
"N0_D5", /* GPIO_111 */
"N0_D6", /* GPIO_112 */
"N0_D7", /* GPIO_113 */
"N0_DQS", /* GPIO_114 */
"N0_DQSN", /* GPIO_115 */
"NC", /* GPIO_116 */
"NC", /* GPIO_117 */
"NC", /* GPIO_118 */
"N0_CEB1", /* GPIO_119 */
"CARD_DT", /* GPIO_120 */
"N0_CEB3", /* GPIO_121 */
"SD_DAT0", /* GPIO_122, HSEC pin 1 */
"SD_DAT1", /* GPIO_123, HSEC pin 3 */
"SD_DAT2", /* GPIO_124, HSEC pin 5 */
"SD_DAT3", /* GPIO_125, HSEC pin 7 */
"NC", /* GPIO_126 */
"NC", /* GPIO_127 */
"[PWR_BTN_N]", /* GPIO_128, LSEC pin 4 */
"[RST_BTN_N]", /* GPIO_129, LSEC pin 6 */
"NC", /* GPIO_130 */
"SD_CMD", /* GPIO_131 */
"GPIO-L", /* GPIO_132, LSEC pin 34 */
"GPIO-K", /* GPIO_133, LSEC pin 33 */
"NC", /* GPIO_134 */
"SD_SCLK", /* GPIO_135 */
"NC", /* GPIO_136 */
"JTAG_TRST", /* GPIO_137 */
"I2C3_SCLK", /* GPIO_138 */
"LED2", /* GPIO_139 */
"LED3", /* GPIO_140 */
"I2C3_SDATA", /* GPIO_141 */
"UART3_RX", /* GPIO_142 */
"UART3_TX", /* GPIO_143 */
"UART3_RTSB", /* GPIO_144 */
"UART3_CTSB"; /* GPIO_145 */
i2c0_default: i2c0-default {
pinmux {
groups = "i2c0_mfp";
function = "i2c0";
};
pinconf {
pins = "i2c0_sclk", "i2c0_sdata";
bias-pull-up;
};
};
i2c1_default: i2c1-default {
pinconf {
pins = "i2c1_sclk", "i2c1_sdata";
bias-pull-up;
};
};
i2c2_default: i2c2-default {
pinconf {
pins = "i2c2_sclk", "i2c2_sdata";
bias-pull-up;
};
};
};
@@ -38,5 +249,4 @@
&uart5 {
status = "okay";
clocks = <&uart5_clk>;
};

118
arch/arm64/boot/dts/actions/s900.dtsi
View File

@@ -1,9 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Andreas Färber
*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/clock/actions,s900-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -88,6 +88,18 @@
#clock-cells = <0>;
};
losc: losc {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
diff24M: diff24M {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -108,6 +120,7 @@
uart0: serial@e0120000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0120000 0x0 0x2000>;
clocks = <&cmu CLK_UART0>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -115,6 +128,7 @@
uart1: serial@e0122000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0122000 0x0 0x2000>;
clocks = <&cmu CLK_UART1>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -122,6 +136,7 @@
uart2: serial@e0124000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0124000 0x0 0x2000>;
clocks = <&cmu CLK_UART2>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -129,6 +144,7 @@
uart3: serial@e0126000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0126000 0x0 0x2000>;
clocks = <&cmu CLK_UART3>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -136,6 +152,7 @@
uart4: serial@e0128000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe0128000 0x0 0x2000>;
clocks = <&cmu CLK_UART4>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -143,6 +160,7 @@
uart5: serial@e012a000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012a000 0x0 0x2000>;
clocks = <&cmu CLK_UART5>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -150,15 +168,111 @@
uart6: serial@e012c000 {
compatible = "actions,s900-uart", "actions,owl-uart";
reg = <0x0 0xe012c000 0x0 0x2000>;
clocks = <&cmu CLK_UART6>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
sps: power-controller@e012e000 {
compatible = "actions,s900-sps";
reg = <0x0 0xe012e000 0x0 0x2000>;
#power-domain-cells = <1>;
};
cmu: clock-controller@e0160000 {
compatible = "actions,s900-cmu";
reg = <0x0 0xe0160000 0x0 0x1000>;
clocks = <&hosc>, <&losc>;
#clock-cells = <1>;
};
i2c0: i2c@e0170000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0170000 0 0x1000>;
clocks = <&cmu CLK_I2C0>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@e0172000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0172000 0 0x1000>;
clocks = <&cmu CLK_I2C1>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e0174000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0174000 0 0x1000>;
clocks = <&cmu CLK_I2C2>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@e0176000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0176000 0 0x1000>;
clocks = <&cmu CLK_I2C3>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@e0178000 {
compatible = "actions,s900-i2c";
reg = <0 0xe0178000 0 0x1000>;
clocks = <&cmu CLK_I2C4>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@e017a000 {
compatible = "actions,s900-i2c";
reg = <0 0xe017a000 0 0x1000>;
clocks = <&cmu CLK_I2C5>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pinctrl: pinctrl@e01b0000 {
compatible = "actions,s900-pinctrl";
reg = <0x0 0xe01b0000 0x0 0x1000>;
clocks = <&cmu CLK_GPIO>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 146>;
#gpio-cells = <2>;
};
timer: timer@e0228000 {
compatible = "actions,s900-timer";
reg = <0x0 0xe0228000 0x0 0x8000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "timer1";
};
dma: dma-controller@e0260000 {
compatible = "actions,s900-dma";
reg = <0x0 0xe0260000 0x0 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <12>;
dma-requests = <46>;
clocks = <&cmu CLK_DMAC>;
};
};
};

4
arch/arm64/boot/dts/allwinner/Makefile
View File

@@ -4,10 +4,13 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
@@ -15,4 +18,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb

2
arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
View File

@@ -203,7 +203,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

30
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
View File

@@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
@@ -86,6 +97,10 @@
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
@@ -103,6 +118,17 @@
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -151,7 +177,7 @@
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
@@ -302,7 +328,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

85
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
View File

@@ -51,12 +51,44 @@
compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
blue {
label = "nanopi-a64:blue:status";
gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
};
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rtc 1>;
clock-names = "ext_clock";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};
&de {
status = "okay";
};
&ehci0 {
@@ -67,6 +99,26 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dcdc1>;
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
/* i2c1 connected with gpio headers like pine64, bananapi */
&i2c1 {
pinctrl-names = "default";
@@ -78,6 +130,13 @@
bias-pull-up;
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -88,6 +147,24 @@
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dldo4>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
rtl8189etv: wifi@1 {
reg = <1>;
interrupt-parent = <&r_pio>;
interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
interrupt-names = "host-wake";
};
};
&ohci0 {
status = "okay";
};
@@ -125,9 +202,9 @@
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
@@ -201,7 +278,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

99
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
View File

@@ -51,6 +51,7 @@
compatible = "olimex,a64-olinuxino", "allwinner,sun50i-a64";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@@ -58,12 +59,74 @@
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
status = "okay";
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_dcdc1>;
allwinner,tx-delay-ps = <600>;
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -92,6 +155,14 @@
};
};
&ohci0 {
status = "okay";
};
&ohci1 {
status = "okay";
};
&r_rsb {
status = "okay";
@@ -100,6 +171,7 @@
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};
@@ -142,10 +214,14 @@
/* DCDC3 is polyphased with DCDC2 */
/*
* The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal
* 1.35V that the PMIC can drive.
*/
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-min-microvolt = <1360000>;
regulator-max-microvolt = <1360000>;
regulator-name = "vcc-ddr3";
};
@@ -180,6 +256,11 @@
regulator-name = "vcc-wifi-io";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_eldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -220,6 +301,18 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
status = "okay";
usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
};

175
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
View File

@@ -1,5 +1,6 @@
/*
* Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
* Copyright (C) 2017-2018 Samuel Holland <samuel@sholland.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -51,23 +52,127 @@
compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
status {
label = "orangepi:green:status";
gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
};
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 3 14 GPIO_ACTIVE_HIGH>; /* PD14 */
status = "okay";
};
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 3 7 GPIO_ACTIVE_HIGH>; /* PD7 */
status = "okay";
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
&ehci1 {
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <&reg_gmac_3v3>;
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
disable-wp;
bus-width = <4>;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_dldo2>;
vqmmc-supply = <&reg_dldo4>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&ohci0 {
status = "okay";
};
@@ -89,9 +194,8 @@
#include "axp803.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "afvcc-csi";
};
@@ -163,12 +267,23 @@
regulator-name = "vcc-wifi-io";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_eldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "cpvdd";
};
&reg_eldo3 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi";
};
&reg_fldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
@@ -195,13 +310,61 @@
vcc-hdmi-supply = <&reg_dldo1>;
};
&spi0 {
status = "okay";
spi-flash@0 {
compatible = "mxicy,mx25l1606e", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
m25p,fast-read;
status = "okay";
};
};
/* On debug connector */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
/* Bluetooth */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
/* On Pi-2 connector, RTS/CTS optional */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "disabled";
};
/* On Pi-2 connector, RTS/CTS optional */
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
status = "disabled";
};
/* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
status = "disabled";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

13
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts Normal file
View File

@@ -0,0 +1,13 @@
/*
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*
* Copyright (c) 2018 ARM Ltd.
*/
#include "sun50i-a64-sopine-baseboard.dts"
/ {
model = "Pine64 LTS";
compatible = "pine64,pine64-lts", "allwinner,sun50i-r18",
"allwinner,sun50i-a64";
};

28
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
View File

@@ -62,6 +62,21 @@
chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
};
&de {
status = "okay";
};
&ehci0 {
@@ -82,6 +97,17 @@
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -241,7 +267,7 @@
/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

9
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
View File

@@ -80,8 +80,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
cd-inverted;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
disable-wp;
bus-width = <4>;
status = "okay";
@@ -104,7 +103,7 @@
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_eldo1>;
bus-width = <8>;
@@ -143,7 +142,7 @@
&r_i2c {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&r_i2c_pins_a>;
pinctrl-0 = <&r_i2c_pl89_pins>;
status = "okay";
};
@@ -270,7 +269,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

28
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
View File

@@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
reg_vcc1v8: vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
@@ -69,6 +80,10 @@
};
};
&de {
status = "okay";
};
&ehci0 {
status = "okay";
};
@@ -86,6 +101,17 @@
status = "okay";
};
&hdmi {
hvcc-supply = <&reg_dldo1>;
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -140,7 +166,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

2
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
View File

@@ -260,7 +260,7 @@
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

193
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@@ -88,6 +88,7 @@
device_type = "cpu";
reg = <0>;
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu1: cpu@1 {
@@ -95,6 +96,7 @@
device_type = "cpu";
reg = <1>;
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu2: cpu@2 {
@@ -102,6 +104,7 @@
device_type = "cpu";
reg = <2>;
enable-method = "psci";
next-level-cache = <&L2>;
};
cpu3: cpu@3 {
@@ -109,7 +112,20 @@
device_type = "cpu";
reg = <3>;
enable-method = "psci";
next-level-cache = <&L2>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
de: display-engine {
compatible = "allwinner,sun50i-a64-display-engine";
allwinner,pipelines = <&mixer0>,
<&mixer1>;
status = "disabled";
};
osc24M: osc24M_clk {
@@ -194,6 +210,52 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
mixer0: mixer@100000 {
compatible = "allwinner,sun50i-a64-de2-mixer-0";
reg = <0x100000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER0>,
<&display_clocks CLK_MIXER0>;
clock-names = "bus",
"mod";
resets = <&display_clocks RST_MIXER0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer0_out: port@1 {
reg = <1>;
mixer0_out_tcon0: endpoint {
remote-endpoint = <&tcon0_in_mixer0>;
};
};
};
};
mixer1: mixer@200000 {
compatible = "allwinner,sun50i-a64-de2-mixer-1";
reg = <0x200000 0x100000>;
clocks = <&display_clocks CLK_BUS_MIXER1>,
<&display_clocks CLK_MIXER1>;
clock-names = "bus",
"mod";
resets = <&display_clocks RST_MIXER1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
mixer1_out: port@1 {
reg = <1>;
mixer1_out_tcon1: endpoint {
remote-endpoint = <&tcon1_in_mixer1>;
};
};
};
};
};
syscon: syscon@1c00000 {
@@ -228,6 +290,75 @@
#dma-cells = <1>;
};
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun50i-a64-tcon-lcd",
"allwinner,sun8i-a83t-tcon-lcd";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-pixel-clock";
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tcon0_in_mixer0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mixer0_out_tcon0>;
};
};
tcon0_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
tcon1: lcd-controller@1c0d000 {
compatible = "allwinner,sun50i-a64-tcon-tv",
"allwinner,sun8i-a83t-tcon-tv";
reg = <0x01c0d000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
clock-names = "ahb", "tcon-ch1";
resets = <&ccu RST_BUS_TCON1>;
reset-names = "lcd";
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon1_in: port@0 {
reg = <0>;
tcon1_in_mixer1: endpoint {
remote-endpoint = <&mixer1_out_tcon1>;
};
};
tcon1_out: port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tcon1_out_hdmi: endpoint@1 {
reg = <1>;
remote-endpoint = <&hdmi_in_tcon1>;
};
};
};
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
@@ -270,6 +401,11 @@
#size-cells = <0>;
};
sid: eeprom@1c14000 {
compatible = "allwinner,sun50i-a64-sid";
reg = <0x1c14000 0x400>;
};
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
@@ -399,7 +535,7 @@
};
mmc2_pins: mmc2-pins {
pins = "PC1", "PC5", "PC6", "PC8", "PC9",
pins = "PC5", "PC6", "PC8", "PC9",
"PC10","PC11", "PC12", "PC13",
"PC14", "PC15", "PC16";
function = "mmc2";
@@ -407,6 +543,13 @@
bias-pull-up;
};
mmc2_ds_pin: mmc2-ds-pin {
pins = "PC1";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
pwm_pin: pwm_pin {
pins = "PD22";
function = "pwm";
@@ -442,7 +585,7 @@
function = "spi1";
};
uart0_pins_a: uart0 {
uart0_pb_pins: uart0-pb-pins {
pins = "PB8", "PB9";
function = "uart0";
};
@@ -686,6 +829,50 @@
status = "disabled";
};
hdmi: hdmi@1ee0000 {
compatible = "allwinner,sun50i-a64-dw-hdmi",
"allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee0000 0x10000>;
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu CLK_HDMI>;
clock-names = "iahb", "isfr", "tmds";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
phy-names = "hdmi-phy";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
hdmi_in_tcon1: endpoint {
remote-endpoint = <&tcon1_out_hdmi>;
};
};
hdmi_out: port@1 {
reg = <1>;
};
};
};
hdmi_phy: hdmi-phy@1ef0000 {
compatible = "allwinner,sun50i-a64-hdmi-phy";
reg = <0x01ef0000 0x10000>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu 7>;
clock-names = "bus", "mod", "pll-0";
resets = <&ccu RST_BUS_HDMI0>;
reset-names = "phy";
#phy-cells = <0>;
};
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
@@ -749,7 +936,7 @@
interrupt-controller;
#interrupt-cells = <3>;
r_i2c_pins_a: i2c-a {
r_i2c_pl89_pins: r-i2c-pl89-pins {
pins = "PL8", "PL9";
function = "s_i2c";
};

11
arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus-v1.2.dts Normal file
View File

@@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
/dts-v1/;
#include "sun50i-h5.dtsi"
#include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
/ {
model = "Banana Pi BPI-M2-Plus v1.2 H5";
compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
};

11
arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts Normal file
View File

@@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
// Copyright (C) 2018 Chen-Yu Tsai <wens@csie.org>
/dts-v1/;
#include "sun50i-h5.dtsi"
#include <arm/sunxi-bananapi-m2-plus.dtsi>
/ {
model = "Banana Pi BPI-M2-Plus H5";
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun50i-h5";
};

43
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
View File

@@ -92,6 +92,49 @@
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
mali: gpu@1e80000 {
compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
reg = <0x01e80000 0x30000>;
/*
* While the datasheet lists an interrupt for the
* PMU, the actual silicon does not have the PMU
* block. Reads all return zero, and writes are
* ignored.
*/
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pp2",
"ppmmu2",
"pp3",
"ppmmu3",
"pmu";
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
clock-names = "bus", "core";
resets = <&ccu RST_BUS_GPU>;
assigned-clocks = <&ccu CLK_GPU>;
assigned-clock-rates = <384000000>;
};
};
};
&ccu {

150
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts Normal file
View File

@@ -0,0 +1,150 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2018 Amarula Solutions
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
/dts-v1/;
#include "sun50i-h6.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "OrangePi One Plus";
compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&r_i2c {
status = "okay";
axp805: pmic@36 {
compatible = "x-powers,axp805", "x-powers,axp806";
reg = <0x36>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <1>;
x-powers,self-working-mode;
regulators {
reg_aldo1: aldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pl";
};
reg_aldo2: aldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-ac200";
};
reg_aldo3: aldo3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc25-dram";
};
reg_bldo1: bldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-bias-pll";
};
reg_bldo2: bldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-efuse-pcie-hdmi-io";
};
reg_bldo3: bldo3 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-dcxoio";
};
bldo4 {
/* unused */
};
reg_cldo1: cldo1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
reg_cldo2: cldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-1";
};
reg_cldo3: cldo3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-2";
};
reg_dcdca: dcdca {
regulator-always-on;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-cpu";
};
reg_dcdcc: dcdcc {
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-gpu";
};
reg_dcdcd: dcdcd {
regulator-always-on;
regulator-min-microvolt = <960000>;
regulator-max-microvolt = <960000>;
regulator-name = "vdd-sys";
};
reg_dcdce: dcdce {
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-dram";
};
sw {
/* unused */
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};

23
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
View File

@@ -92,6 +92,29 @@
#size-cells = <1>;
ranges;
syscon: syscon@3000000 {
compatible = "allwinner,sun50i-h6-system-control",
"allwinner,sun50i-a64-system-control";
reg = <0x03000000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_c: sram@28000 {
compatible = "mmio-sram";
reg = <0x00028000 0x1e000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00028000 0x1e000>;
de2_sram: sram-section@0 {
compatible = "allwinner,sun50i-h6-sram-c",
"allwinner,sun50i-a64-sram-c";
reg = <0x0000 0x1e000>;
};
};
};
ccu: clock@3001000 {
compatible = "allwinner,sun50i-h6-ccu";
reg = <0x03001000 0x1000>;

2
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View File

@@ -341,7 +341,7 @@
sysmgr: sysmgr@ffd12000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd12000 0x1000>;
reg = <0xffd12000 0x228>;
};
/* Local timer */

5
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
View File

@@ -21,6 +21,9 @@
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
@@ -124,6 +127,8 @@
&i2c1 {
status = "okay";
clock-frequency = <100000>;
i2c-sda-falling-time-ns = <890>; /* hcnt */
i2c-sdl-falling-time-ns = <890>; /* lcnt */
adc@14 {
compatible = "lltc,ltc2497";

4
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
View File

@@ -107,7 +107,7 @@
clock-names = "uartclk", "apb_pclk";
};
spi0: ssp@e1020000 {
spi0: spi@e1020000 {
status = "disabled";
compatible = "arm,pl022", "arm,primecell";
reg = <0 0xe1020000 0 0x1000>;
@@ -117,7 +117,7 @@
clock-names = "apb_pclk";
};
spi1: ssp@e1030000 {
spi1: spi@e1030000 {
status = "disabled";
compatible = "arm,pl022", "arm,primecell";
reg = <0 0xe1030000 0 0x1000>;

1
arch/arm64/boot/dts/amlogic/Makefile
View File

@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb

390
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
View File

@@ -60,6 +60,55 @@
serial1 = &uart_A;
};
linein: audio-codec@0 {
#sound-dai-cells = <0>;
compatible = "everest,es7241";
VDDA-supply = <&vcc_3v3>;
VDDP-supply = <&vcc_3v3>;
VDDD-supply = <&vcc_3v3>;
status = "okay";
sound-name-prefix = "Linein";
};
lineout: audio-codec@1 {
#sound-dai-cells = <0>;
compatible = "everest,es7154";
VDD-supply = <&vcc_3v3>;
PVDD-supply = <&vcc_5v>;
status = "okay";
sound-name-prefix = "Lineout";
};
spdif_dit: audio-codec@2 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
status = "okay";
sound-name-prefix = "DIT";
};
dmics: audio-codec@3 {
#sound-dai-cells = <0>;
compatible = "dmic-codec";
num-channels = <7>;
wakeup-delay-ms = <50>;
status = "okay";
sound-name-prefix = "MIC";
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
@@ -68,33 +117,6 @@
regulator-always-on;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&main_12v>;
regulator-always-on;
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
@@ -115,6 +137,33 @@
enable-active-high;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&main_12v>;
regulator-always-on;
};
vddio_ao18: regulator-vddio_ao18 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_AO18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
usb_pwr: regulator-usb_pwr {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
@@ -126,11 +175,6 @@
enable-active-high;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
@@ -138,13 +182,6 @@
clock-names = "ext_clock";
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
};
speaker-leds {
compatible = "gpio-leds";
@@ -179,30 +216,129 @@
};
};
linein: audio-codec@0 {
#sound-dai-cells = <0>;
compatible = "everest,es7241";
VDDA-supply = <&vcc_3v3>;
VDDP-supply = <&vcc_3v3>;
VDDD-supply = <&vcc_3v3>;
sound {
compatible = "amlogic,axg-sound-card";
model = "AXG-S400";
audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>,
<&tdmin_lb>, <&tdmout_c>;
audio-widgets = "Line", "Lineout",
"Line", "Linein",
"Speaker", "Speaker1 Left",
"Speaker", "Speaker1 Right";
audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
"SPDIFOUT IN 0", "FRDDR_A OUT 3",
"TDMOUT_C IN 1", "FRDDR_B OUT 2",
"SPDIFOUT IN 1", "FRDDR_B OUT 3",
"TDMOUT_C IN 2", "FRDDR_C OUT 2",
"SPDIFOUT IN 2", "FRDDR_C OUT 3",
"TDM_C Playback", "TDMOUT_C OUT",
"TDMIN_A IN 2", "TDM_C Capture",
"TDMIN_A IN 5", "TDM_C Loopback",
"TDMIN_B IN 2", "TDM_C Capture",
"TDMIN_B IN 5", "TDM_C Loopback",
"TDMIN_C IN 2", "TDM_C Capture",
"TDMIN_C IN 5", "TDM_C Loopback",
"TDMIN_LB IN 2", "TDM_C Loopback",
"TDMIN_LB IN 5", "TDM_C Capture",
"TODDR_A IN 0", "TDMIN_A OUT",
"TODDR_B IN 0", "TDMIN_A OUT",
"TODDR_C IN 0", "TDMIN_A OUT",
"TODDR_A IN 1", "TDMIN_B OUT",
"TODDR_B IN 1", "TDMIN_B OUT",
"TODDR_C IN 1", "TDMIN_B OUT",
"TODDR_A IN 2", "TDMIN_C OUT",
"TODDR_B IN 2", "TDMIN_C OUT",
"TODDR_C IN 2", "TDMIN_C OUT",
"TODDR_A IN 4", "PDM Capture",
"TODDR_B IN 4", "PDM Capture",
"TODDR_C IN 4", "PDM Capture",
"TODDR_A IN 6", "TDMIN_LB OUT",
"TODDR_B IN 6", "TDMIN_LB OUT",
"TODDR_C IN 6", "TDMIN_LB OUT",
"Lineout", "Lineout AOUTL",
"Lineout", "Lineout AOUTR",
"Speaker1 Left", "SPK1 OUT_A",
"Speaker1 Left", "SPK1 OUT_B",
"Speaker1 Right", "SPK1 OUT_C",
"Speaker1 Right", "SPK1 OUT_D",
"Linein AINL", "Linein",
"Linein AINR", "Linein";
assigned-clocks = <&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <589824000>,
<270950400>,
<393216000>;
status = "okay";
sound-name-prefix = "Linein";
dai-link@0 {
sound-dai = <&frddr_a>;
};
dai-link@1 {
sound-dai = <&frddr_b>;
};
dai-link@2 {
sound-dai = <&frddr_c>;
};
dai-link@3 {
sound-dai = <&toddr_a>;
};
dai-link@4 {
sound-dai = <&toddr_b>;
};
dai-link@5 {
sound-dai = <&toddr_c>;
};
dai-link@6 {
sound-dai = <&tdmif_c>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-rx-mask-1 = <1 1>;
mclk-fs = <256>;
codec@0 {
sound-dai = <&lineout>;
};
codec@1 {
sound-dai = <&speaker_amp1>;
};
codec@2 {
sound-dai = <&linein>;
};
};
dai-link@7 {
sound-dai = <&spdifout>;
codec {
sound-dai = <&spdif_dit>;
};
};
dai-link@8 {
sound-dai = <&pdm>;
codec {
sound-dai = <&dmics>;
};
};
};
lineout: audio-codec@1 {
#sound-dai-cells = <0>;
compatible = "everest,es7154";
VDD-supply = <&vcc_3v3>;
PVDD-supply = <&vcc_5v>;
status = "okay";
sound-name-prefix = "Lineout";
};
spdif_dit: audio-codec@2 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
status = "okay";
sound-name-prefix = "DIT";
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
};
};
@@ -226,16 +362,16 @@
};
};
&uart_A {
&frddr_a {
status = "okay";
pinctrl-0 = <&uart_a_pins>;
pinctrl-names = "default";
};
&uart_AO {
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ir {
@@ -260,6 +396,7 @@
PVDD_B-supply = <&main_12v>;
PVDD_C-supply = <&main_12v>;
PVDD_D-supply = <&main_12v>;
sound-name-prefix = "SPK1";
};
};
@@ -277,30 +414,22 @@
};
};
&pdm {
pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
<&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm_ab {
status = "okay";
pinctrl-0 = <&pwm_a_x20_pins>;
pinctrl-names = "default";
};
/* emmc storage */
&sd_emmc_c {
&saradc {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <180000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
vref-supply = <&vddio_ao18>;
};
/* wifi module */
@@ -330,7 +459,96 @@
};
};
&saradc {
status = "okay";
vref-supply = <&vddio_ao18>;
/* emmc storage */
&sd_emmc_c {
status = "disabled";
pinctrl-0 = <&emmc_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <180000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&spdifout {
pinctrl-0 = <&spdif_out_a20_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmif_a {
pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
<&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmif_b {
pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
<&tdmb_din3_pins>, <&mclk_b_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmif_c {
pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
<&tdmc_din1_pins>, <&tdmc_dout2_pins>,
<&mclk_c_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmin_a {
status = "okay";
};
&tdmin_b {
status = "okay";
};
&tdmin_c {
status = "okay";
};
&tdmin_lb {
status = "okay";
};
&tdmout_c {
status = "okay";
};
&toddr_a {
status = "okay";
};
&toddr_b {
status = "okay";
};
&toddr_c {
status = "okay";
};
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>;
pinctrl-names = "default";
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};

1721
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View File

File diff suppressed because it is too large Load Diff

29
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts Normal file
View File

@@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
/dts-v1/;
#include "meson-g12a.dtsi"
/ {
compatible = "amlogic,u200", "amlogic,g12a";
model = "Amlogic Meson G12A U200 Development Board";
aliases {
serial0 = &uart_AO;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
};
&uart_AO {
status = "okay";
};

172
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi Normal file
View File

@@ -0,0 +1,172 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "amlogic,g12a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@5000000 {
reg = <0x0 0x05000000 0x0 0x300000>;
no-map;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
periphs: periphs@ff634000 {
compatible = "simple-bus";
reg = <0x0 0xff634000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
};
hiubus: bus@ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x1c00>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
};
aobus: bus@ff800000 {
compatible = "simple-bus";
reg = <0x0 0xff800000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
uart_AO_B: serial@4000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x4000 0x0 0x18>;
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
<0x0 0xffc02000 0 0x2000>,
<0x0 0xffc04000 0 0x2000>,
<0x0 0xffc06000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
cbus: bus@ffd00000 {
compatible = "simple-bus";
reg = <0x0 0xffd00000 0x0 0x25000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
};
apb: apb@ffe00000 {
compatible = "simple-bus";
reg = <0x0 0xffe00000 0x0 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
};

19
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View File

@@ -44,7 +44,7 @@
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0xbc00000>;
size = <0x0 0x10000000>;
alignment = <0x0 0x400000>;
linux,cma-default;
};
@@ -344,7 +344,7 @@
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
sysctrl_AO: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x100>;
pwrc_vpu: power-controller-vpu {
@@ -423,6 +423,19 @@
};
};
dmcbus: bus@c8838000 {
compatible = "simple-bus";
reg = <0x0 0xc8838000 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
canvas: video-lut@48 {
compatible = "amlogic,canvas";
reg = <0x0 0x48 0x0 0x14>;
};
};
hiubus: bus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
@@ -431,7 +444,7 @@
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
reg = <0 0 0 0x400>;
};

2
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@@ -390,7 +390,7 @@
};
};
spi_pins: spi {
spi_pins: spi-pins {
mux {
groups = "spi_miso",
"spi_mosi",

2
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
View File

@@ -13,7 +13,7 @@
/ {
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
model = "Libre Technology CC";
model = "Libre Computer Board AML-S905X-CC";
aliases {
serial0 = &uart_AO;

2
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@@ -337,7 +337,7 @@
};
};
spi_pins: spi {
spi_pins: spi-pins {
mux {
groups = "spi_miso",
"spi_mosi",

166
arch/arm64/boot/dts/arm/juno-base.dtsi
View File

@@ -115,22 +115,17 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* input port */
port@0 {
reg = <0>;
in-ports {
port {
etf0_in_port: endpoint {
slave-mode;
remote-endpoint = <&main_funnel_out_port>;
};
};
};
/* output port */
port@1 {
reg = <0>;
out-ports {
port {
etf0_out_port: endpoint {
};
};
@@ -144,10 +139,11 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
tpiu_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port0>;
in-ports {
port {
tpiu_in_port: endpoint {
remote-endpoint = <&replicator_out_port0>;
};
};
};
};
@@ -160,31 +156,29 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* output port */
port@0 {
reg = <0>;
out-ports {
port {
main_funnel_out_port: endpoint {
remote-endpoint = <&etf0_in_port>;
};
};
};
/* input ports */
port@1 {
main_funnel_in_ports: in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
main_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster0_funnel_out_port>;
};
};
port@2 {
port@1 {
reg = <1>;
main_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster1_funnel_out_port>;
};
};
@@ -199,10 +193,12 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
etr_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port1>;
arm,scatter-gather;
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&replicator_out_port1>;
};
};
};
};
@@ -216,8 +212,10 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
stm_out_port: endpoint {
out-ports {
port {
stm_out_port: endpoint {
};
};
};
};
@@ -238,9 +236,11 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster0_etm0_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port0>;
out-ports {
port {
cluster0_etm0_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port0>;
};
};
};
};
@@ -252,29 +252,28 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
out-ports {
port {
cluster0_funnel_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port0>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cluster0_funnel_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port0>;
};
};
port@1 {
reg = <0>;
cluster0_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster0_etm0_out_port>;
};
};
port@2 {
port@1 {
reg = <1>;
cluster0_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster0_etm1_out_port>;
};
};
@@ -297,9 +296,11 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster0_etm1_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port1>;
out-ports {
port {
cluster0_etm1_out_port: endpoint {
remote-endpoint = <&cluster0_funnel_in_port1>;
};
};
};
};
@@ -320,9 +321,11 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm0_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port0>;
out-ports {
port {
cluster1_etm0_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port0>;
};
};
};
};
@@ -334,43 +337,40 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
out-ports {
port {
cluster1_funnel_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port1>;
};
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cluster1_funnel_out_port: endpoint {
remote-endpoint = <&main_funnel_in_port1>;
};
};
port@1 {
reg = <0>;
cluster1_funnel_in_port0: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm0_out_port>;
};
};
port@2 {
port@1 {
reg = <1>;
cluster1_funnel_in_port1: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm1_out_port>;
};
};
port@3 {
port@2 {
reg = <2>;
cluster1_funnel_in_port2: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm2_out_port>;
};
};
port@4 {
port@3 {
reg = <3>;
cluster1_funnel_in_port3: endpoint {
slave-mode;
remote-endpoint = <&cluster1_etm3_out_port>;
};
};
@@ -393,9 +393,11 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm1_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port1>;
out-ports {
port {
cluster1_etm1_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port1>;
};
};
};
};
@@ -416,9 +418,11 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm2_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port2>;
out-ports {
port {
cluster1_etm2_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port2>;
};
};
};
};
@@ -439,9 +443,11 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
port {
cluster1_etm3_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port3>;
out-ports {
port {
cluster1_etm3_out_port: endpoint {
remote-endpoint = <&cluster1_funnel_in_port3>;
};
};
};
};
@@ -454,7 +460,7 @@
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
out-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -472,12 +478,10 @@
remote-endpoint = <&etr_in_port>;
};
};
/* replicator input port */
port@2 {
reg = <0>;
};
in-ports {
port {
replicator_in_port0: endpoint {
slave-mode;
};
};
};

52
arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi
View File

@@ -7,23 +7,16 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* output port */
port@0 {
reg = <0>;
out-ports {
port {
csys1_funnel_out_port: endpoint {
remote-endpoint = <&etf1_in_port>;
};
};
/* input port */
port@1 {
reg = <0>;
};
in-ports {
port {
csys1_funnel_in_port0: endpoint {
slave-mode;
};
};
@@ -37,22 +30,15 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* input port */
port@0 {
reg = <0>;
in-ports {
port {
etf1_in_port: endpoint {
slave-mode;
remote-endpoint = <&csys1_funnel_out_port>;
};
};
/* output port */
port@1 {
reg = <0>;
};
out-ports {
port {
etf1_out_port: endpoint {
remote-endpoint = <&csys2_funnel_in_port1>;
};
@@ -67,20 +53,18 @@
clocks = <&soc_smc50mhz>;
clock-names = "apb_pclk";
power-domains = <&scpi_devpd 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* output port */
port@0 {
reg = <0>;
out-ports {
port {
csys2_funnel_out_port: endpoint {
remote-endpoint = <&replicator_in_port0>;
};
};
};
/* input ports */
port@1 {
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csys2_funnel_in_port0: endpoint {
slave-mode;
@@ -88,7 +72,7 @@
};
};
port@2 {
port@1 {
reg = <1>;
csys2_funnel_in_port1: endpoint {
slave-mode;

13
arch/arm64/boot/dts/arm/juno.dts
View File

@@ -257,14 +257,11 @@
remote-endpoint = <&main_funnel_in_port2>;
};
&main_funnel {
ports {
port@3 {
reg = <2>;
main_funnel_in_port2: endpoint {
slave-mode;
remote-endpoint = <&stm_out_port>;
};
&main_funnel_in_ports {
port@2 {
reg = <2>;
main_funnel_in_port2: endpoint {
remote-endpoint = <&stm_out_port>;
};
};
};

3
arch/arm64/boot/dts/broadcom/Makefile
View File

@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb
subdir-y += northstar2
subdir-y += stingray

2
arch/arm64/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts Normal file
View File

@@ -0,0 +1,2 @@
// SPDX-License-Identifier: GPL-2.0
#include "arm/bcm2837-rpi-cm3-io3.dts"

4
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View File

@@ -639,7 +639,7 @@
status = "disabled";
};
ssp0: ssp@66180000 {
ssp0: spi@66180000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x66180000 0x1000>;
interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
@@ -650,7 +650,7 @@
status = "disabled";
};
ssp1: ssp@66190000 {
ssp1: spi@66190000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x66190000 0x1000>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
View File

@@ -138,7 +138,7 @@
&i2c1 {
status = "okay";
pcf8574: pcf8574@20 {
pcf8574: pcf8574@27 {
compatible = "nxp,pcf8574a";
gpio-controller;
#gpio-cells = <2>;

4
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View File

@@ -521,7 +521,7 @@
status = "disabled";
};
ssp0: ssp@180000 {
ssp0: spi@180000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00180000 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
@@ -533,7 +533,7 @@
status = "disabled";
};
ssp1: ssp@190000 {
ssp1: spi@190000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x00190000 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;

18
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
View File

@@ -868,6 +868,14 @@
};
};
};
ports {
port {
muic_to_usb: endpoint {
remote-endpoint = <&usb_to_muic>;
};
};
};
};
regulators {
@@ -939,8 +947,7 @@
status = "okay";
cap-sd-highspeed;
disable-wp;
cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
cd-inverted;
cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>;
@@ -1283,12 +1290,17 @@
&usbdrd_dwc3 {
dr_mode = "otg";
extcon = <&muic>;
};
&usbdrd30_phy {
vbus-supply = <&safeout1_reg>;
status = "okay";
port {
usb_to_muic: endpoint {
remote-endpoint = <&muic_to_usb>;
};
};
};
&xxti {

2
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@@ -337,7 +337,7 @@
status = "disabled";
};
dspi: dspi@2100000 {
dspi: spi@2100000 {
compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
View File

@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*/
@@ -50,6 +51,7 @@
nor@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
big-endian;
bank-width = <2>;
device-width = <1>;
};

2
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
View File

@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*/
@@ -65,6 +66,7 @@
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x8000000>;
big-endian;
bank-width = <2>;
device-width = <1>;
};

8
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*/
@@ -280,11 +281,10 @@
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
big-endian;
interrupts = <0 43 0x4>;
};
qspi: quadspi@1550000 {
qspi: spi@1550000 {
compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -382,7 +382,7 @@
ranges = <0x0 0x5 0x00000000 0x8000000>;
};
dspi0: dspi@2100000 {
dspi0: spi@2100000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -395,7 +395,7 @@
status = "disabled";
};
dspi1: dspi@2110000 {
dspi1: spi@2110000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
View File

@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* Shaohui Xie <Shaohui.Xie@nxp.com>
*/
@@ -141,6 +142,7 @@
nor@0,0 {
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
big-endian;
bank-width = <2>;
device-width = <1>;
};

4
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
View File

@@ -57,12 +57,12 @@
reg = <0x4c>;
};
eeprom@56 {
eeprom@52 {
compatible = "atmel,24c512";
reg = <0x52>;
};
eeprom@57 {
eeprom@53 {
compatible = "atmel,24c512";
reg = <0x53>;
};

6
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@@ -198,11 +199,10 @@
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
big-endian;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
};
qspi: quadspi@1550000 {
qspi: spi@1550000 {
compatible = "fsl,ls1021a-qspi";
#address-cells = <1>;
#size-cells = <0>;
@@ -361,7 +361,7 @@
#thermal-sensor-cells = <1>;
};
dspi: dspi@2100000 {
dspi: spi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;

20
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@@ -22,6 +22,8 @@
crypto = &crypto;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
};
cpu: cpus {
@@ -222,6 +224,20 @@
interrupts = <0 32 0x4>; /* Level high type */
};
serial2: serial@21d0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0500 0x0 0x100>;
clocks = <&clockgen 4 3>;
interrupts = <0 33 0x4>; /* Level high type */
};
serial3: serial@21d0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0600 0x0 0x100>;
clocks = <&clockgen 4 3>;
interrupts = <0 33 0x4>; /* Level high type */
};
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
@@ -474,7 +490,7 @@
<0 208 4>, <0 209 4>;
};
dspi: dspi@2100000 {
dspi: spi@2100000 {
status = "disabled";
compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
#address-cells = <1>;
@@ -600,7 +616,7 @@
3 0 0x5 0x20000000 0x00010000>;
};
qspi: quadspi@20c0000 {
qspi: spi@20c0000 {
status = "disabled";
compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
#address-cells = <1>;

1
arch/arm64/boot/dts/hisilicon/Makefile
View File

@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
dtb-$(CONFIG_ARCH_HISI) += hi3670-hikey970.dtb
dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb
dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb

35
arch/arm64/boot/dts/hisilicon/hi3670-hikey970.dts Normal file
View File

@@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Hisilicon HiKey970 Development Board
*
* Copyright (C) 2016, Hisilicon Ltd.
* Copyright (C) 2018, Linaro Ltd.
*
*/
/dts-v1/;
#include "hi3670.dtsi"
/ {
model = "HiKey970";
compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
aliases {
serial6 = &uart6; /* console UART */
};
chosen {
stdout-path = "serial6:115200n8";
};
memory@0 {
device_type = "memory";
/* expect bootloader to fill in this region */
reg = <0x0 0x0 0x0 0x0>;
};
};
&uart6 {
status = "okay";
};

162
arch/arm64/boot/dts/hisilicon/hi3670.dtsi Normal file
View File

@@ -0,0 +1,162 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Hisilicon Hi3670 SoC
*
* Copyright (C) 2016, Hisilicon Ltd.
* Copyright (C) 2018, Linaro Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "hisilicon,hi3670";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
cpu4: cpu@100 {
compatible = "arm,cortex-a73", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu5: cpu@101 {
compatible = "arm,cortex-a73", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
};
cpu6: cpu@102 {
compatible = "arm,cortex-a73", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
};
cpu7: cpu@103 {
compatible = "arm,cortex-a73", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
};
};
gic: interrupt-controller@e82b0000 {
compatible = "arm,gic-400";
reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
<0x0 0xe82b2000 0 0x2000>, /* GICC */
<0x0 0xe82b4000 0 0x2000>, /* GICH */
<0x0 0xe82b6000 0 0x2000>; /* GICV */
#interrupt-cells = <3>;
#address-cells = <0>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <1920000>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
uart6_clk: clk_19_2M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
uart6: serial@fff32000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfff32000 0x0 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart6_clk &uart6_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};

181
arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
View File

@@ -20,22 +20,18 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
out-ports {
port {
soc_funnel_out: endpoint {
remote-endpoint =
<&etf_in>;
};
};
};
port@1 {
reg = <0>;
in-ports {
port {
soc_funnel_in: endpoint {
slave-mode;
remote-endpoint =
<&acpu_funnel_out>;
};
@@ -49,21 +45,17 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
in-ports {
port {
etf_in: endpoint {
slave-mode;
remote-endpoint =
<&soc_funnel_out>;
};
};
};
port@1 {
reg = <0>;
out-ports {
port {
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
@@ -77,20 +69,20 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
in-ports {
port {
replicator_in: endpoint {
slave-mode;
remote-endpoint =
<&etf_out>;
};
};
};
port@1 {
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint =
@@ -98,7 +90,7 @@
};
};
port@2 {
port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint =
@@ -114,14 +106,9 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
in-ports {
port {
etr_in: endpoint {
slave-mode;
remote-endpoint =
<&replicator_out0>;
};
@@ -135,14 +122,9 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
in-ports {
port {
tpiu_in: endpoint {
slave-mode;
remote-endpoint =
<&replicator_out1>;
};
@@ -156,85 +138,78 @@
clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
out-ports {
port {
acpu_funnel_out: endpoint {
remote-endpoint =
<&soc_funnel_in>;
};
};
};
port@1 {
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
acpu_funnel_in0: endpoint {
slave-mode;
remote-endpoint =
<&etm0_out>;
};
};
port@2 {
port@1 {
reg = <1>;
acpu_funnel_in1: endpoint {
slave-mode;
remote-endpoint =
<&etm1_out>;
};
};
port@3 {
port@2 {
reg = <2>;
acpu_funnel_in2: endpoint {
slave-mode;
remote-endpoint =
<&etm2_out>;
};
};
port@4 {
port@3 {
reg = <3>;
acpu_funnel_in3: endpoint {
slave-mode;
remote-endpoint =
<&etm3_out>;
};
};
port@5 {
port@4 {
reg = <4>;
acpu_funnel_in4: endpoint {
slave-mode;
remote-endpoint =
<&etm4_out>;
};
};
port@6 {
port@5 {
reg = <5>;
acpu_funnel_in5: endpoint {
slave-mode;
remote-endpoint =
<&etm5_out>;
};
};
port@7 {
port@6 {
reg = <6>;
acpu_funnel_in6: endpoint {
slave-mode;
remote-endpoint =
<&etm6_out>;
};
};
port@8 {
port@7 {
reg = <7>;
acpu_funnel_in7: endpoint {
slave-mode;
remote-endpoint =
<&etm7_out>;
};
@@ -251,10 +226,12 @@
cpu = <&cpu0>;
port {
etm0_out: endpoint {
remote-endpoint =
<&acpu_funnel_in0>;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&acpu_funnel_in0>;
};
};
};
};
@@ -268,10 +245,12 @@
cpu = <&cpu1>;
port {
etm1_out: endpoint {
remote-endpoint =
<&acpu_funnel_in1>;
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&acpu_funnel_in1>;
};
};
};
};
@@ -285,10 +264,12 @@
cpu = <&cpu2>;
port {
etm2_out: endpoint {
remote-endpoint =
<&acpu_funnel_in2>;
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&acpu_funnel_in2>;
};
};
};
};
@@ -302,10 +283,12 @@
cpu = <&cpu3>;
port {
etm3_out: endpoint {
remote-endpoint =
<&acpu_funnel_in3>;
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&acpu_funnel_in3>;
};
};
};
};
@@ -319,10 +302,12 @@
cpu = <&cpu4>;
port {
etm4_out: endpoint {
remote-endpoint =
<&acpu_funnel_in4>;
out-ports {
port {
etm4_out: endpoint {
remote-endpoint =
<&acpu_funnel_in4>;
};
};
};
};
@@ -336,10 +321,12 @@
cpu = <&cpu5>;
port {
etm5_out: endpoint {
remote-endpoint =
<&acpu_funnel_in5>;
out-ports {
port {
etm5_out: endpoint {
remote-endpoint =
<&acpu_funnel_in5>;
};
};
};
};
@@ -353,10 +340,12 @@
cpu = <&cpu6>;
port {
etm6_out: endpoint {
remote-endpoint =
<&acpu_funnel_in6>;
out-ports {
port {
etm6_out: endpoint {
remote-endpoint =
<&acpu_funnel_in6>;
};
};
};
};
@@ -370,10 +359,12 @@
cpu = <&cpu7>;
port {
etm7_out: endpoint {
remote-endpoint =
<&acpu_funnel_in7>;
out-ports {
port {
etm7_out: endpoint {
remote-endpoint =
<&acpu_funnel_in7>;
};
};
};
};

7
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@@ -99,6 +99,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -111,6 +112,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -123,6 +125,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -135,6 +138,7 @@
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -147,6 +151,7 @@
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -159,6 +164,7 @@
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */
@@ -171,6 +177,7 @@
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
clocks = <&stub_clock 0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
#cooling-cells = <2>; /* min followed by max */

4
arch/arm64/boot/dts/lg/lg1312.dtsi
View File

@@ -168,14 +168,14 @@
clock-names = "apb_pclk";
status="disabled";
};
spi0: ssp@fe800000 {
spi0: spi@fe800000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xfe800000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
spi1: ssp@fe900000 {
spi1: spi@fe900000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xfe900000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

4
arch/arm64/boot/dts/lg/lg1313.dtsi
View File

@@ -168,14 +168,14 @@
clock-names = "apb_pclk";
status="disabled";
};
spi0: ssp@fe800000 {
spi0: spi@fe800000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xfe800000 0x1000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_bus>;
clock-names = "apb_pclk";
};
spi1: ssp@fe900000 {
spi1: spi@fe900000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xfe900000 0x1000>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

1
arch/arm64/boot/dts/marvell/Makefile
View File

@@ -3,6 +3,7 @@
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb

2
arch/arm64/boot/dts/marvell/armada-372x.dtsi
View File

@@ -16,7 +16,7 @@
compatible = "marvell,armada3720", "marvell,armada3710";
cpus {
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x1>;

15
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@@ -40,7 +40,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>;
@@ -80,6 +80,19 @@
/* 32M internal register @ 0xd000_0000 */
ranges = <0x0 0x0 0xd0000000 0x2000000>;
wdt: watchdog@8300 {
compatible = "marvell,armada-3700-wdt";
reg = <0x8300 0x40>;
marvell,system-controller = <&cpu_misc>;
clocks = <&xtalclk>;
};
cpu_misc: system-controller@d000 {
compatible = "marvell,armada-3700-cpu-misc",
"syscon";
reg = <0xd000 0x1000>;
};
spi0: spi@10600 {
compatible = "marvell,armada-3700-spi";
#address-cells = <1>;

441
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts Normal file
View File

@@ -0,0 +1,441 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 SolidRun ltd.
* Based on Marvell MACCHIATOBin board
*
* Device Tree file for SolidRun's ClearFog GT 8K
*/
#include "armada-8040.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "SolidRun ClearFog GT 8K";
compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
aliases {
ethernet0 = &cp1_eth1;
ethernet1 = &cp0_eth0;
ethernet2 = &cp1_eth2;
};
v_3_3: regulator-3-3v {
compatible = "regulator-fixed";
regulator-name = "v_3_3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
compatible = "regulator-fixed";
gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "v_5v0_usb3_hst_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
status = "okay";
};
usb3h0_phy: usb3_phy0 {
compatible = "usb-nop-xceiv";
vcc-supply = <&v_5v0_usb3_hst_vbus>;
};
sfp_cp0_eth0: sfp-cp0-eth0 {
compatible = "sff,sfp";
i2c-bus = <&cp0_i2c1>;
mod-def0-gpio = <&cp0_gpio2 17 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_sfp_present_pins &cp1_sfp_tx_disable_pins>;
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&cp0_led0_pins
&cp0_led1_pins>;
pinctrl-names = "default";
/* No designated function for these LEDs at the moment */
led0 {
label = "clearfog-gt-8k:green:led0";
gpios = <&cp0_gpio2 8 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led1 {
label = "clearfog-gt-8k:green:led1";
gpios = <&cp0_gpio2 9 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&cp0_gpio_reset_pins &cp1_wps_button_pins>;
pinctrl-names = "default";
button_0 {
/* The rear button */
label = "Rear Button";
gpios = <&cp0_gpio2 7 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_0>;
};
button_1 {
/* The wps button */
label = "WPS Button";
gpios = <&cp1_gpio1 30 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <KEY_WPS_BUTTON>;
};
};
};
&uart0 {
status = "okay";
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
&ap_sdhci0 {
bus-width = <8>;
no-1-8-v;
no-sd;
no-sdio;
non-removable;
status = "okay";
vqmmc-supply = <&v_3_3>;
};
&cp0_i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
};
&cp0_i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
};
&cp0_pinctrl {
/*
* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
* [11] CLKOUT_MPP_11 (out)
* [23] LINK_RD_IN_CP2CP (in)
* [25] CLKOUT_MPP_25 (out)
* [29] AVS_FB_IN_CP2CP (in)
* [32, 33, 34] pci0/1/2 reset
* [35-38] CP0 I2C1 and I2C0
* [39] GPIO reset button
* [40,41] LED0 and LED1
* [43] 1512 phy reset
* [47] USB VBUS EN (active low)
* [48] FAN PWM
* [49] SFP+ present signal
* [50] TPM interrupt
* [51] WLAN0 disable
* [52] WLAN1 disable
* [53] LTE disable
* [54] NFC reset
* [55] Micro SD card detect
* [56-61] Micro SD
*/
cp0_pci0_reset_pins: pci0-reset-pins {
marvell,pins = "mpp32";
marvell,function = "gpio";
};
cp0_pci1_reset_pins: pci1-reset-pins {
marvell,pins = "mpp33";
marvell,function = "gpio";
};
cp0_pci2_reset_pins: pci2-reset-pins {
marvell,pins = "mpp34";
marvell,function = "gpio";
};
cp0_i2c1_pins: i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
cp0_i2c0_pins: i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
cp0_gpio_reset_pins: gpio-reset-pins {
marvell,pins = "mpp39";
marvell,function = "gpio";
};
cp0_led0_pins: led0-pins {
marvell,pins = "mpp40";
marvell,function = "gpio";
};
cp0_led1_pins: led1-pins {
marvell,pins = "mpp41";
marvell,function = "gpio";
};
cp0_copper_eth_phy_reset: copper-eth-phy-reset {
marvell,pins = "mpp43";
marvell,function = "gpio";
};
cp0_xhci_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cp0_fan_pwm_pins: fan-pwm-pins {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
cp0_sfp_present_pins: sfp-present-pins {
marvell,pins = "mpp49";
marvell,function = "gpio";
};
cp0_tpm_irq_pins: tpm-irq-pins {
marvell,pins = "mpp50";
marvell,function = "gpio";
};
cp0_sdhci_pins: sdhci-pins {
marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
"mpp60", "mpp61";
marvell,function = "sdio";
};
};
&cp0_pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&cp0_pci0_reset_pins>;
reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&cp0_gpio2 {
sata_reset {
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&cp0_ethernet {
status = "okay";
};
/* SFP */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
managed = "in-band-status";
phys = <&cp0_comphy2 0>;
sfp = <&sfp_cp0_eth0>;
};
&cp0_sdhci0 {
broken-cd;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cp0_sdhci_pins>;
status = "okay";
vqmmc-supply = <&v_3_3>;
};
&cp1_pinctrl {
/*
* MPP Bus:
* [0-5] TDM
* [6] VHV Enable
* [7] CP1 SPI0 CSn1 (FXS)
* [8] CP1 SPI0 CSn0 (TPM)
* [9.11]CP1 SPI0 MOSI/MISO/CLK
* [13] CP1 SPI1 MISO (TDM and SPI ROM shared)
* [14] CP1 SPI1 CS0n (64Mb SPI ROM)
* [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)
* [16] CP1 SPI1 CLK (TDM and SPI ROM shared)
* [24] Topaz switch reset
* [26] Buzzer
* [27] CP1 SMI MDIO
* [28] CP1 SMI MDC
* [29] CP0 10G SFP TX Disable
* [30] WPS button
* [31] Front panel button
*/
cp1_spi1_pins: spi1-pins {
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
cp1_switch_reset_pins: switch-reset-pins {
marvell,pins = "mpp24";
marvell,function = "gpio";
};
cp1_ge_mdio_pins: ge-mdio-pins {
marvell,pins = "mpp27", "mpp28";
marvell,function = "ge";
};
cp1_sfp_tx_disable_pins: sfp-tx-disable-pins {
marvell,pins = "mpp29";
marvell,function = "gpio";
};
cp1_wps_button_pins: wps-button-pins {
marvell,pins = "mpp30";
marvell,function = "gpio";
};
};
&cp1_sata0 {
pinctrl-0 = <&cp0_pci1_reset_pins>;
status = "okay";
};
&cp1_mdio {
pinctrl-names = "default";
pinctrl-0 = <&cp1_ge_mdio_pins>;
status = "okay";
ge_phy: ethernet-phy@0 {
/* LED0 - GB link
* LED1 - on: link, blink: activity
*/
marvell,reg-init = <3 16 0 0x1017>;
reg = <0>;
};
switch0: switch0@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cp1_switch_reset_pins>;
reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp1_eth2>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
switch0phy3: switch0phy3@14 {
reg = <0x14>;
};
};
};
};
&cp1_ethernet {
status = "okay";
};
/* 1G copper */
&cp1_eth1 {
status = "okay";
phy-mode = "sgmii";
phy = <&ge_phy>;
phys = <&cp1_comphy3 1>;
};
/* Switch uplink */
&cp1_eth2 {
status = "okay";
phy-mode = "2500base-x";
phys = <&cp1_comphy5 2>;
fixed-link {
speed = <2500>;
full-duplex;
};
};
&cp1_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
compatible = "st,w25q32";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&cp1_usb3_0 {
usb-phy = <&usb3h0_phy>;
status = "okay";
};

4
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
View File

@@ -15,13 +15,13 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;

12
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
View File

@@ -15,29 +15,33 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu@100 {
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
cpu@101 {
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
};
};
};

110
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View File

@@ -6,6 +6,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/dts-v1/;
@@ -27,6 +28,33 @@
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
idle_states {
entry_method = "arm,pcsi";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <80>;
exit-latency-us = <160>;
min-residency-us = <320>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <500>;
exit-latency-us = <1000>;
min-residency-us = <2500>;
};
};
};
ap806 {
#address-cells = <2>;
#size-cells = <2>;
@@ -124,6 +152,15 @@
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
sei: interrupt-controller@3f0200 {
compatible = "marvell,ap806-sei";
reg = <0x3f0200 0x40>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-controller;
msi-controller;
};
xor@400000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>,
@@ -247,11 +284,76 @@
};
};
ap_thermal: thermal@6f808c {
compatible = "marvell,armada-ap806-thermal";
reg = <0x6f808c 0x4>,
<0x6f8084 0x8>;
ap_syscon1: system-controller@6f8000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f8000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ap_thermal: thermal-sensor@80 {
compatible = "marvell,armada-ap806-thermal";
reg = <0x80 0x10>;
#thermal-sensor-cells = <1>;
};
};
};
};
/*
* The thermal IP features one internal sensor plus, if applicable, one
* remote channel wired to one sensor per CPU.
*
* The cooling maps are always empty as there are no cooling devices.
*/
thermal-zones {
ap_thermal_ic: ap-thermal-ic {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 0>;
trips { };
cooling-maps { };
};
ap_thermal_cpu1: ap-thermal-cpu1 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 1>;
trips { };
cooling-maps { };
};
ap_thermal_cpu2: ap-thermal-cpu2 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 2>;
trips { };
cooling-maps { };
};
ap_thermal_cpu3: ap-thermal-cpu3 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 3>;
trips { };
cooling-maps { };
};
ap_thermal_cpu4: ap-thermal-cpu4 {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&ap_thermal 4>;
trips { };
cooling-maps { };
};
};
};

16
arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
View File

@@ -13,49 +13,49 @@
#size-cells = <0>;
compatible = "marvell,armada-ap810-octa";
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x000>;
enable-method = "psci";
};
cpu@1 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x001>;
enable-method = "psci";
};
cpu@100 {
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x100>;
enable-method = "psci";
};
cpu@101 {
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x101>;
enable-method = "psci";
};
cpu@200 {
cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x200>;
enable-method = "psci";
};
cpu@201 {
cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x201>;
enable-method = "psci";
};
cpu@300 {
cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x300>;
enable-method = "psci";
};
cpu@301 {
cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
reg = <0x301>;

1
arch/arm64/boot/dts/marvell/armada-common.dtsi
View File

@@ -7,4 +7,5 @@
#define PASTER(x, y) x ## y
#define EVALUATOR(x, y) PASTER(x, y)
#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
#define CP110_NODE_NAME(name) EVALUATOR(CP110_NAME, EVALUATOR(-, name))
#define ADDRESSIFY(addr) EVALUATOR(0x, addr)

189
arch/arm64/boot/dts/marvell/armada-cp110.dtsi
View File

@@ -6,6 +6,7 @@
*/
#include <dt-bindings/interrupt-controller/mvebu-icu.h>
#include <dt-bindings/thermal/thermal.h>
#include "armada-common.dtsi"
@@ -19,13 +20,30 @@
* save one indentation level
*/
CP110_NAME: CP110_NAME { };
/*
* CPs only have one sensor in the thermal IC.
*
* The cooling maps are empty as there are no cooling devices.
*/
thermal-zones {
CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&CP110_LABEL(thermal) 0>;
trips { };
cooling-maps { };
};
};
};
&CP110_NAME {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&CP110_LABEL(icu)>;
interrupt-parent = <&CP110_LABEL(icu_nsr)>;
ranges;
config-space@CP110_BASE {
@@ -47,42 +65,57 @@
dma-coherent;
CP110_LABEL(eth0): eth0 {
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<51 IRQ_TYPE_LEVEL_HIGH>,
<55 IRQ_TYPE_LEVEL_HIGH>,
<59 IRQ_TYPE_LEVEL_HIGH>,
<63 IRQ_TYPE_LEVEL_HIGH>,
<67 IRQ_TYPE_LEVEL_HIGH>,
<71 IRQ_TYPE_LEVEL_HIGH>,
<129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
CP110_LABEL(eth1): eth1 {
interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>,
<52 IRQ_TYPE_LEVEL_HIGH>,
<56 IRQ_TYPE_LEVEL_HIGH>,
<60 IRQ_TYPE_LEVEL_HIGH>,
<64 IRQ_TYPE_LEVEL_HIGH>,
<68 IRQ_TYPE_LEVEL_HIGH>,
<72 IRQ_TYPE_LEVEL_HIGH>,
<128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
CP110_LABEL(eth2): eth2 {
interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
"tx-cpu3", "rx-shared", "link";
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
<45 IRQ_TYPE_LEVEL_HIGH>,
<49 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>,
<57 IRQ_TYPE_LEVEL_HIGH>,
<61 IRQ_TYPE_LEVEL_HIGH>,
<65 IRQ_TYPE_LEVEL_HIGH>,
<69 IRQ_TYPE_LEVEL_HIGH>,
<73 IRQ_TYPE_LEVEL_HIGH>,
<127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hif0", "hif1", "hif2",
"hif3", "hif4", "hif5", "hif6", "hif7",
"hif8", "link";
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
@@ -150,22 +183,31 @@
CP110_LABEL(icu): interrupt-controller@1e0000 {
compatible = "marvell,cp110-icu";
reg = <0x1e0000 0x440>;
#interrupt-cells = <3>;
interrupt-controller;
msi-parent = <&gicp>;
#address-cells = <1>;
#size-cells = <1>;
CP110_LABEL(icu_nsr): interrupt-controller@10 {
compatible = "marvell,cp110-icu-nsr";
reg = <0x10 0x20>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&gicp>;
};
CP110_LABEL(icu_sei): interrupt-controller@50 {
compatible = "marvell,cp110-icu-sei";
reg = <0x50 0x10>;
#interrupt-cells = <2>;
interrupt-controller;
msi-parent = <&sei>;
};
};
CP110_LABEL(rtc): rtc@284000 {
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
CP110_LABEL(thermal): thermal@400078 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x400078 0x4>,
<0x400070 0x8>;
interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
};
CP110_LABEL(syscon0): system-controller@440000 {
@@ -185,10 +227,10 @@
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
<85 IRQ_TYPE_LEVEL_HIGH>,
<84 IRQ_TYPE_LEVEL_HIGH>,
<83 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -200,20 +242,33 @@
#gpio-cells = <2>;
gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
interrupt-controller;
interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
<81 IRQ_TYPE_LEVEL_HIGH>,
<80 IRQ_TYPE_LEVEL_HIGH>,
<79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
CP110_LABEL(syscon1): system-controller@400000 {
compatible = "syscon", "simple-mfd";
reg = <0x400000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
CP110_LABEL(thermal): thermal-sensor@70 {
compatible = "marvell,armada-cp110-thermal";
reg = <0x70 0x10>;
#thermal-sensor-cells = <1>;
};
};
CP110_LABEL(usb3_0): usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 22>,
<&CP110_LABEL(clk) 1 16>;
@@ -225,7 +280,7 @@
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 23>,
<&CP110_LABEL(clk) 1 16>;
@@ -237,7 +292,7 @@
"generic-ahci";
reg = <0x540000 0x30000>;
dma-coherent;
interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 15>,
<&CP110_LABEL(clk) 1 16>;
status = "disabled";
@@ -290,7 +345,7 @@
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
@@ -302,7 +357,7 @@
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 21>,
<&CP110_LABEL(clk) 1 17>;
@@ -313,7 +368,7 @@
compatible = "snps,dw-apb-uart";
reg = <0x702000 0x100>;
reg-shift = <2>;
interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@@ -325,7 +380,7 @@
compatible = "snps,dw-apb-uart";
reg = <0x702100 0x100>;
reg-shift = <2>;
interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@@ -337,7 +392,7 @@
compatible = "snps,dw-apb-uart";
reg = <0x702200 0x100>;
reg-shift = <2>;
interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@@ -349,7 +404,7 @@
compatible = "snps,dw-apb-uart";
reg = <0x702300 0x100>;
reg-shift = <2>;
interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <1>;
clock-names = "baudclk", "apb_pclk";
clocks = <&CP110_LABEL(clk) 1 21>,
@@ -368,7 +423,7 @@
reg = <0x720000 0x54>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 2>,
<&CP110_LABEL(clk) 1 17>;
@@ -380,7 +435,7 @@
compatible = "marvell,armada-8k-rng",
"inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 25>,
<&CP110_LABEL(clk) 1 17>;
@@ -390,7 +445,7 @@
CP110_LABEL(sdhci0): sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "axi";
clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
dma-coherent;
@@ -400,12 +455,12 @@
CP110_LABEL(crypto): crypto@800000 {
compatible = "inside-secure,safexcel-eip197b";
reg = <0x800000 0x200000>;
interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
<88 IRQ_TYPE_LEVEL_HIGH>,
<89 IRQ_TYPE_LEVEL_HIGH>,
<90 IRQ_TYPE_LEVEL_HIGH>,
<91 IRQ_TYPE_LEVEL_HIGH>,
<92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clock-names = "core", "reg";
@@ -434,8 +489,8 @@
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
@@ -461,8 +516,8 @@
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";
@@ -489,8 +544,8 @@
/* non-prefetchable memory */
0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clock-names = "core", "reg";

1
arch/arm64/boot/dts/mediatek/Makefile
View File

@@ -5,4 +5,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb

11
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View File

@@ -301,6 +301,17 @@
status = "disabled";
};
spis1: spi@10013000 {
compatible = "mediatek,mt2712-spi-slave";
reg = <0 0x10013000 0 0x100>;
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_AO_SPI1>;
clock-names = "spi";
assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
status = "disabled";
};
apmixedsys: syscon@10209000 {
compatible = "mediatek,mt2712-apmixedsys", "syscon";
reg = <0 0x10209000 0 0x1000>;

530
arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts Normal file
View File

@@ -0,0 +1,530 @@
/*
* Copyright (c) 2018 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include "mt7622.dtsi"
#include "mt6380.dtsi"
/ {
model = "Bananapi BPI-R64";
compatible = "bananapi,bpi-r64", "mediatek,mt7622";
chosen {
bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
};
cpus {
cpu@0 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
cpu@1 {
proc-supply = <&mt6380_vcpu_reg>;
sram-supply = <&mt6380_vm_reg>;
};
};
gpio-keys {
compatible = "gpio-keys";
factory {
label = "factory";
linux,code = <BTN_0>;
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
};
};
leds {
compatible = "gpio-leds";
green {
label = "bpi-r64:pio:green";
gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
red {
label = "bpi-r64:pio:red";
gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
memory {
reg = <0 0x40000000 0 0x40000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
};
&bch {
status = "disabled";
};
&btif {
status = "okay";
};
&cir {
pinctrl-names = "default";
pinctrl-0 = <&irrx_pins>;
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
status = "okay";
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-handle = <&phy5>;
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
phy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "sgmii";
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_uhs>;
status = "okay";
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
non-removable;
};
&mmc1 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&sd0_pins_default>;
pinctrl-1 = <&sd0_pins_uhs>;
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <1>;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};
&nandc {
pinctrl-names = "default";
pinctrl-0 = <&parallel_nand_pins>;
status = "disabled";
};
&nor_flash {
pinctrl-names = "default";
pinctrl-0 = <&spi_nor_pins>;
status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
status = "okay";
pcie@0,0 {
status = "okay";
};
pcie@1,0 {
status = "okay";
};
};
&pio {
/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
* SATA functions. i.e. output-high: PCIe, output-low: SATA
*/
asm_sel {
gpio-hog;
gpios = <90 GPIO_ACTIVE_HIGH>;
output-high;
};
/* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default {
mux {
function = "emmc", "emmc_rst";
groups = "emmc";
};
/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
* "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
* DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
*/
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
bias-pull-down;
};
};
emmc_pins_uhs: emmc-pins-uhs {
mux {
function = "emmc";
groups = "emmc";
};
conf-cmd-dat {
pins = "NDL0", "NDL1", "NDL2",
"NDL3", "NDL4", "NDL5",
"NDL6", "NDL7", "NRB";
input-enable;
drive-strength = <4>;
bias-pull-up;
};
conf-clk {
pins = "NCLE";
drive-strength = <4>;
bias-pull-down;
};
};
eth_pins: eth-pins {
mux {
function = "eth";
groups = "mdc_mdio", "rgmii_via_gmac2";
};
};
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
groups = "i2c2_0";
};
};
i2s1_pins: i2s1-pins {
mux {
function = "i2s";
groups = "i2s_out_mclk_bclk_ws",
"i2s1_in_data",
"i2s1_out_data";
};
conf {
pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
"I2S_WS", "I2S_MCLK";
drive-strength = <12>;
bias-pull-down;
};
};
irrx_pins: irrx-pins {
mux {
function = "ir";
groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
groups = "ir_1_tx";
};
};
/* Parallel nand is shared pin with eMMC */
parallel_nand_pins: parallel-nand-pins {
mux {
function = "flash";
groups = "par_nand";
};
};
pcie0_pins: pcie0-pins {
mux {
function = "pcie";
groups = "pcie0_pad_perst",
"pcie0_1_waken",
"pcie0_1_clkreq";
};
};
pcie1_pins: pcie1-pins {
mux {
function = "pcie";
groups = "pcie1_pad_perst",
"pcie1_0_waken",
"pcie1_0_clkreq";
};
};
pmic_bus_pins: pmic-bus-pins {
mux {
function = "pmic";
groups = "pmic_bus";
};
};
pwm7_pins: pwm1-2-pins {
mux {
function = "pwm";
groups = "pwm_ch7_2";
};
};
wled_pins: wled-pins {
mux {
function = "led";
groups = "wled";
};
};
sd0_pins_default: sd0-pins-default {
mux {
function = "sd";
groups = "sd_0";
};
/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
* "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
* DAT2, DAT3, CMD, CLK for SD respectively.
*/
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
drive-strength = <8>;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
drive-strength = <12>;
bias-pull-down;
};
conf-cd {
pins = "TXD3";
bias-pull-up;
};
};
sd0_pins_uhs: sd0-pins-uhs {
mux {
function = "sd";
groups = "sd_0";
};
conf-cmd-data {
pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
"I2S2_IN","I2S4_OUT";
input-enable;
bias-pull-up;
};
conf-clk {
pins = "I2S3_OUT";
bias-pull-down;
};
};
/* Serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
spic0_pins: spic0-pins {
mux {
function = "spi";
groups = "spic0_0";
};
};
spic1_pins: spic1-pins {
mux {
function = "spi";
groups = "spic1_0";
};
};
/* SPI-NOR is shared pin with serial NAND */
spi_nor_pins: spi-nor-pins {
mux {
function = "flash";
groups = "spi_nor";
};
};
/* serial NAND is shared pin with SPI-NOR */
serial_nand_pins: serial-nand-pins {
mux {
function = "flash";
groups = "snfi";
};
};
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0_0_tx_rx" ;
};
};
uart2_pins: uart2-pins {
mux {
function = "uart";
groups = "uart2_1_tx_rx" ;
};
};
watchdog_pins: watchdog-pins {
mux {
function = "watchdog";
groups = "watchdog";
};
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm7_pins>;
status = "okay";
};
&pwrap {
pinctrl-names = "default";
pinctrl-0 = <&pmic_bus_pins>;
status = "okay";
};
&sata {
status = "disable";
};
&sata_phy {
status = "disable";
};
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spic0_pins>;
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spic1_pins>;
status = "okay";
};
&ssusb {
vusb33-supply = <&reg_3p3v>;
vbus-supply = <&reg_5v>;
status = "okay";
};
&u3phy {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&watchdog {
pinctrl-names = "default";
pinctrl-0 = <&watchdog_pins>;
status = "okay";
};

196
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
View File

@@ -51,7 +51,7 @@
};
memory {
reg = <0 0x40000000 0 0x3F000000>;
reg = <0 0x40000000 0 0x20000000>;
};
reg_1p8v: regulator-1p8v {
@@ -81,6 +81,103 @@
};
};
&bch {
status = "disabled";
};
&btif {
status = "okay";
};
&cir {
pinctrl-names = "default";
pinctrl-0 = <&irrx_pins>;
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
status = "okay";
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-handle = <&phy5>;
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
phy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "sgmii";
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_uhs>;
status = "okay";
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
non-removable;
};
&mmc1 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&sd0_pins_default>;
pinctrl-1 = <&sd0_pins_uhs>;
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <1>;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};
&nandc {
pinctrl-names = "default";
pinctrl-0 = <&parallel_nand_pins>;
status = "disabled";
};
&nor_flash {
pinctrl-names = "default";
pinctrl-0 = <&spi_nor_pins>;
status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins>;
@@ -344,103 +441,6 @@
};
};
&bch {
status = "disabled";
};
&btif {
status = "okay";
};
&cir {
pinctrl-names = "default";
pinctrl-0 = <&irrx_pins>;
status = "okay";
};
&eth {
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
status = "okay";
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
phy-handle = <&phy5>;
};
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
phy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "sgmii";
};
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
status = "okay";
};
&mmc0 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_uhs>;
status = "okay";
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
non-removable;
};
&mmc1 {
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&sd0_pins_default>;
pinctrl-1 = <&sd0_pins_uhs>;
status = "okay";
bus-width = <4>;
max-frequency = <50000000>;
cap-sd-highspeed;
r_smpl = <1>;
cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
};
&nandc {
pinctrl-names = "default";
pinctrl-0 = <&parallel_nand_pins>;
status = "disabled";
};
&nor_flash {
pinctrl-names = "default";
pinctrl-0 = <&spi_nor_pins>;
status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm7_pins>;

62
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View File

@@ -79,6 +79,7 @@
#cooling-cells = <2>;
enable-method = "psci";
clock-frequency = <1300000000>;
cci-control-port = <&cci_control2>;
};
cpu1: cpu@1 {
@@ -92,6 +93,7 @@
#cooling-cells = <2>;
enable-method = "psci";
clock-frequency = <1300000000>;
cci-control-port = <&cci_control2>;
};
};
@@ -113,6 +115,13 @@
method = "smc";
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -218,6 +227,16 @@
#reset-cells = <1>;
};
timer: timer@10004000 {
compatible = "mediatek,mt7622-timer",
"mediatek,mt6577-timer";
reg = <0 0x10004000 0 0x80>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_APXGPT_PD>,
<&topckgen CLK_TOP_RTC>;
clock-names = "system-clk", "rtc-clk";
};
scpsys: scpsys@10006000 {
compatible = "mediatek,mt7622-scpsys",
"syscon";
@@ -325,6 +344,42 @@
<0 0x10360000 0 0x2000>;
};
cci: cci@10390000 {
compatible = "arm,cci-400";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0x10390000 0 0x1000>;
ranges = <0 0 0x10390000 0x10000>;
cci_control0: slave-if@1000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace-lite";
reg = <0x1000 0x1000>;
};
cci_control1: slave-if@4000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x4000 0x1000>;
};
cci_control2: slave-if@5000 {
compatible = "arm,cci-400-ctrl-if";
interface-type = "ace";
reg = <0x5000 0x1000>;
};
pmu@9000 {
compatible = "arm,cci-400-pmu,r1";
reg = <0x9000 0x5000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
};
auxadc: adc@11001000 {
compatible = "mediatek,mt7622-auxadc";
reg = <0 0x11001000 0 0x1000>;
@@ -475,6 +530,13 @@
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
bluetooth {
compatible = "mediatek,mt7622-bluetooth";
power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
clocks = <&clk25m>;
clock-names = "ref";
};
};
nandc: nfi@1100d000 {

76
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View File

@@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/power/tegra186-powergate.h>
#include <dt-bindings/reset/tegra186-reset.h>
#include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
@@ -236,6 +237,20 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
nvidia,default-tap = <0x5>;
nvidia,default-trim = <0xb>;
assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
<&bpmp TEGRA186_CLK_PLLP_OUT0>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
status = "disabled";
};
@@ -247,6 +262,15 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA186_RESET_SDMMC2>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc2_3v3>;
pinctrl-1 = <&sdmmc2_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
nvidia,default-tap = <0x5>;
nvidia,default-trim = <0xb>;
status = "disabled";
};
@@ -258,6 +282,17 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA186_RESET_SDMMC3>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc3_3v3>;
pinctrl-1 = <&sdmmc3_1v8>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
nvidia,default-tap = <0x5>;
nvidia,default-trim = <0xb>;
status = "disabled";
};
@@ -267,8 +302,19 @@
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
clock-names = "sdhci";
assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
<&bpmp TEGRA186_CLK_PLLC4_VCO>;
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
resets = <&bpmp TEGRA186_RESET_SDMMC4>;
reset-names = "sdhci";
nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
nvidia,default-tap = <0x5>;
nvidia,default-trim = <0x9>;
nvidia,dqs-trim = <63>;
mmc-hs400-1_8v;
status = "disabled";
};
@@ -368,6 +414,36 @@
<0 0x0c380000 0 0x10000>,
<0 0x0c390000 0 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch";
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
sdmmc2_3v3: sdmmc2-3v3 {
pins = "sdmmc2-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc2_1v8: sdmmc2-1v8 {
pins = "sdmmc2-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
sdmmc3_3v3: sdmmc3-3v3 {
pins = "sdmmc3-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc3_1v8: sdmmc3-1v8 {
pins = "sdmmc3-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
};
ccplex@e000000 {

16
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@@ -118,7 +118,7 @@
};
gen1_i2c: i2c@3160000 {
compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra194-i2c";
reg = <0x03160000 0x10000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -143,7 +143,7 @@
};
cam_i2c: i2c@3180000 {
compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra194-i2c";
reg = <0x03180000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -157,7 +157,7 @@
/* shares pads with dpaux1 */
dp_aux_ch1_i2c: i2c@3190000 {
compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra194-i2c";
reg = <0x03190000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -171,7 +171,7 @@
/* shares pads with dpaux0 */
dp_aux_ch0_i2c: i2c@31b0000 {
compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra194-i2c";
reg = <0x031b0000 0x10000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -184,7 +184,7 @@
};
gen7_i2c: i2c@31c0000 {
compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra194-i2c";
reg = <0x031c0000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -197,7 +197,7 @@
};
gen9_i2c: i2c@31e0000 {
compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra194-i2c";
reg = <0x031e0000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -264,7 +264,7 @@
};
gen2_i2c: i2c@c240000 {
compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra194-i2c";
reg = <0x0c240000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -277,7 +277,7 @@
};
gen8_i2c: i2c@c250000 {
compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
compatible = "nvidia,tegra194-i2c";
reg = <0x0c250000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;

12
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
View File

@@ -178,16 +178,7 @@
vddio_sdmmc: ldo2 {
regulator-name = "VDDIO_SDMMC";
/*
* Technically this supply should have
* a supported range from 1.8 - 3.3 V.
* However, that would cause the SDHCI
* driver to request 2.7 V upon access
* and that in turn will cause traffic
* to be broken. Leave it at 3.3 V for
* now.
*/
regulator-min-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
@@ -282,6 +273,7 @@
status = "okay";
bus-width = <8>;
non-removable;
vqmmc-supply = <&vdd_1v8>;
};
clocks {

1
arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi
View File

@@ -1452,7 +1452,6 @@
sdhci@700b0000 {
status = "okay";
bus-width = <4>;
no-1-8-v;
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;

57
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View File

@@ -3,6 +3,7 @@
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra210-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
@@ -776,6 +777,26 @@
#power-domain-cells = <0>;
};
};
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
sdmmc3_3v3: sdmmc3-3v3 {
pins = "sdmmc3";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc3_1v8: sdmmc3-1v8 {
pins = "sdmmc3";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
};
fuse@7000f800 {
@@ -1027,6 +1048,20 @@
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
nvidia,default-tap = <0x2>;
nvidia,default-trim = <0x4>;
assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_C4>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
status = "disabled";
};
@@ -1038,6 +1073,10 @@
clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
nvidia,default-tap = <0x8>;
nvidia,default-trim = <0x0>;
status = "disabled";
};
@@ -1049,6 +1088,15 @@
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc3_3v3>;
pinctrl-1 = <&sdmmc3_1v8>;
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
nvidia,default-tap = <0x3>;
nvidia,default-trim = <0x3>;
status = "disabled";
};
@@ -1060,6 +1108,15 @@
clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
nvidia,default-tap = <0x8>;
nvidia,default-trim = <0x0>;
assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
nvidia,dqs-trim = <40>;
mmc-hs400-1_8v;
status = "disabled";
};

1
arch/arm64/boot/dts/qcom/Makefile
View File

@@ -6,4 +6,5 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb

14
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View File

@@ -545,6 +545,20 @@
};
};
&spmi_bus {
pm8916_0: pm8916@0 {
pon@800 {
resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
};
&wcd_codec {
status = "okay";
clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;

2
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
View File

@@ -17,5 +17,5 @@
/ {
model = "Qualcomm Technologies, Inc. DB820c";
compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
};

14
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
View File

@@ -623,3 +623,17 @@
};
};
};
&spmi_bus {
pmic@0 {
pon@800 {
resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
};

98
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@@ -18,9 +18,6 @@
#include <dt-bindings/thermal/thermal.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8916";
compatible = "qcom,msm8916";
interrupt-parent = <&intc>;
#address-cells = <2>;
@@ -1099,10 +1096,11 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
port {
tpiu_in: endpoint {
slave-mode;
remote-endpoint = <&replicator_out1>;
in-ports {
port {
tpiu_in: endpoint {
remote-endpoint = <&replicator_out1>;
};
};
};
};
@@ -1114,7 +1112,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
ports {
in-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1132,12 +1130,13 @@
port@4 {
reg = <4>;
funnel0_in4: endpoint {
slave-mode;
remote-endpoint = <&funnel1_out>;
};
};
port@8 {
reg = <0>;
};
out-ports {
port {
funnel0_out: endpoint {
remote-endpoint = <&etf_in>;
};
@@ -1152,7 +1151,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
ports {
out-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1168,10 +1167,11 @@
remote-endpoint = <&tpiu_in>;
};
};
port@2 {
reg = <0>;
};
in-ports {
port {
replicator_in: endpoint {
slave-mode;
remote-endpoint = <&etf_out>;
};
};
@@ -1185,19 +1185,16 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
in-ports {
port {
etf_in: endpoint {
slave-mode;
remote-endpoint = <&funnel0_out>;
};
};
port@1 {
reg = <0>;
};
out-ports {
port {
etf_out: endpoint {
remote-endpoint = <&replicator_in>;
};
@@ -1212,10 +1209,11 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
port {
etr_in: endpoint {
slave-mode;
remote-endpoint = <&replicator_out0>;
in-ports {
port {
etr_in: endpoint {
remote-endpoint = <&replicator_out0>;
};
};
};
};
@@ -1227,40 +1225,38 @@
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
ports {
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
funnel1_in0: endpoint {
slave-mode;
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
funnel1_in1: endpoint {
slave-mode;
remote-endpoint = <&etm1_out>;
};
};
port@2 {
reg = <2>;
funnel1_in2: endpoint {
slave-mode;
remote-endpoint = <&etm2_out>;
};
};
port@3 {
reg = <3>;
funnel1_in3: endpoint {
slave-mode;
remote-endpoint = <&etm3_out>;
};
};
port@4 {
reg = <0>;
};
out-ports {
port {
funnel1_out: endpoint {
remote-endpoint = <&funnel0_in4>;
};
@@ -1309,9 +1305,11 @@
cpu = <&CPU0>;
port {
etm0_out: endpoint {
remote-endpoint = <&funnel1_in0>;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint = <&funnel1_in0>;
};
};
};
};
@@ -1325,9 +1323,11 @@
cpu = <&CPU1>;
port {
etm1_out: endpoint {
remote-endpoint = <&funnel1_in1>;
out-ports {
port {
etm1_out: endpoint {
remote-endpoint = <&funnel1_in1>;
};
};
};
};
@@ -1341,9 +1341,11 @@
cpu = <&CPU2>;
port {
etm2_out: endpoint {
remote-endpoint = <&funnel1_in2>;
out-ports {
port {
etm2_out: endpoint {
remote-endpoint = <&funnel1_in2>;
};
};
};
};
@@ -1357,9 +1359,11 @@
cpu = <&CPU3>;
port {
etm3_out: endpoint {
remote-endpoint = <&funnel1_in3>;
out-ports {
port {
etm3_out: endpoint {
remote-endpoint = <&funnel1_in3>;
};
};
};
};

15
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@@ -16,8 +16,6 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8996";
interrupt-parent = <&intc>;
#address-cells = <2>;
@@ -409,11 +407,6 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
apcs: syscon@9820000 {
compatible = "syscon";
reg = <0x9820000 0x1000>;
};
apcs_glb: mailbox@9820000 {
compatible = "qcom,msm8996-apcs-hmss-global";
reg = <0x9820000 0x1000>;
@@ -1140,7 +1133,7 @@
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
label = "lpass";
qcom,ipc = <&apcs 16 8>;
mboxes = <&apcs_glb 8>;
qcom,smd-edge = <1>;
qcom,remote-pid = <2>;
};
@@ -1152,7 +1145,7 @@
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 16 10>;
mboxes = <&apcs_glb 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
@@ -1176,7 +1169,7 @@
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 16 14>;
mboxes = <&apcs_glb 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
@@ -1200,7 +1193,7 @@
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 16 26>;
mboxes = <&apcs_glb 26>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;

13
arch/arm64/boot/dts/qcom/msm8998-mtp.dts Normal file
View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
/dts-v1/;
#include "msm8998-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP";
compatible = "qcom,msm8998-mtp";
qcom,board-id = <8 0>;
};

243
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi Normal file
View File

@@ -0,0 +1,243 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
#include "msm8998.dtsi"
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
#include "pm8005.dtsi"
/ {
aliases {
serial0 = &blsp2_uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
thermal-zones {
battery-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 0>;
trips {
battery_crit: trip0 {
temperature = <60000>;
hysteresis = <2000>;
type = "critical";
};
};
};
skin-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 5>;
trips {
skin_alert: trip0 {
temperature = <44000>;
hysteresis = <2000>;
type = "passive";
};
skip_crit: trip1 {
temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-always-on;
regulator-boot-on;
};
};
&blsp2_uart1 {
status = "okay";
};
&rpm_requests {
pm8998-regulators {
compatible = "qcom,rpm-pm8998-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_s8-supply = <&vph_pwr>;
vdd_s9-supply = <&vph_pwr>;
vdd_s10-supply = <&vph_pwr>;
vdd_s11-supply = <&vph_pwr>;
vdd_s12-supply = <&vph_pwr>;
vdd_s13-supply = <&vph_pwr>;
vdd_l1_l27-supply = <&vreg_s7a_1p025>;
vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>;
vdd_l3_l11-supply = <&vreg_s7a_1p025>;
vdd_l4_l5-supply = <&vreg_s7a_1p025>;
vdd_l6-supply = <&vreg_s5a_2p04>;
vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>;
vdd_l9-supply = <&vreg_bob>;
vdd_l10_l23_l25-supply = <&vreg_bob>;
vdd_l13_l19_l21-supply = <&vreg_bob>;
vdd_l16_l28-supply = <&vreg_bob>;
vdd_l18_l22-supply = <&vreg_bob>;
vdd_l20_l24-supply = <&vreg_bob>;
vdd_l26-supply = <&vreg_s3a_1p35>;
vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>;
vreg_s3a_1p35: s3 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_s4a_1p8: s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_s5a_2p04: s5 {
regulator-min-microvolt = <1904000>;
regulator-max-microvolt = <2040000>;
};
vreg_s7a_1p025: s7 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1028000>;
};
vreg_l1a_0p875: l1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
};
vreg_l2a_1p2: l2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l3a_1p0: l3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l5a_0p8: l5 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
vreg_l6a_1p8: l6 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <1808000>;
};
vreg_l7a_1p8: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l8a_1p2: l8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l9a_1p8: l9 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
vreg_l10a_1p8: l10 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
vreg_l11a_1p0: l11 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l12a_1p8: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l13a_2p95: l13 {
regulator-min-microvolt = <1808000>;
regulator-max-microvolt = <2960000>;
};
vreg_l14a_1p88: l14 {
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <1880000>;
};
vreg_15a_1p8: l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l16a_2p7: l16 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
};
vreg_l17a_1p3: l17 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
};
vreg_l18a_2p7: l18 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
};
vreg_l19a_3p0: l19 {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
vreg_l20a_2p95: l20 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
};
vreg_l21a_2p95: l21 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
};
vreg_l22a_2p85: l22 {
regulator-min-microvolt = <2864000>;
regulator-max-microvolt = <2864000>;
};
vreg_l23a_3p3: l23 {
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3312000>;
};
vreg_l24a_3p075: l24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
};
vreg_l25a_3p3: l25 {
regulator-min-microvolt = <3104000>;
regulator-max-microvolt = <3312000>;
};
vreg_l26a_1p2: l26 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l28_3p0: l28 {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
};
vreg_lvs1a_1p8: lvs1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs2a_1p8: lvs2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
pmi8998-regulators {
compatible = "qcom,rpm-pmi8998-regulators";
vdd_bob-supply = <&vph_pwr>;
vreg_bob: bob {
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3600000>;
};
};
};

690
arch/arm64/boot/dts/qcom/msm8998.dtsi Normal file
View File

@@ -0,0 +1,690 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
/ {
interrupt-parent = <&intc>;
qcom,msm-id = <292 0x0>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
memory@85800000 {
reg = <0x0 0x85800000 0x0 0x800000>;
no-map;
};
smem_mem: smem-mem@86000000 {
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
};
memory@86200000 {
reg = <0x0 0x86200000 0x0 0x2600000>;
no-map;
};
rmtfs {
compatible = "qcom,rmtfs-mem";
size = <0x0 0x200000>;
alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
};
clocks {
xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_1: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_2: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
efficiency = <1024>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_3: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
};
L1_I_100: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_100: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
L1_I_101: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_101: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
L1_I_102: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_102: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
efficiency = <1536>;
next-level-cache = <&L2_1>;
L1_I_103: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_103: l1-dcache {
compatible = "arm,arch-cache";
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
};
firmware {
scm {
compatible = "qcom,scm-msm8998";
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8998";
qcom,glink-channels = "rpm_requests";
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
smp2p-lpass {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-mpss {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apcs_glb 26>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
slpi_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
slpi_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
thermal-zones {
cpu-thermal0 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
trips {
cpu_alert0: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
trips {
cpu_alert1: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit1: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
trips {
cpu_alert2: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit2: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
trips {
cpu_alert3: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit3: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal4 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
trips {
cpu_alert4: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit4: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal5 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
trips {
cpu_alert5: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit5: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal6 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 0>;
trips {
cpu_alert6: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit6: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal7 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
trips {
cpu_alert7: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit7: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
gpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
rpm_msg_ram: memory@68000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x778000 0x7000>;
};
qfprom: qfprom@780000 {
compatible = "qcom,qfprom";
reg = <0x780000 0x621c>;
#address-cells = <1>;
#size-cells = <1>;
};
gcc: clock-controller@100000 {
compatible = "qcom,gcc-msm8998";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x100000 0xb0000>;
};
tlmm: pinctrl@3400000 {
compatible = "qcom,msm8998-pinctrl";
reg = <0x3400000 0xc00000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
interrupt-controller;
#interrupt-cells = <0x2>;
};
spmi_bus: spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x800f000 0x1000>,
<0x8400000 0x1000000>,
<0x9400000 0x1000000>,
<0xa400000 0x220000>,
<0x800a000 0x3000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
tsens0: thermal@10aa000 {
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
reg = <0x10aa000 0x2000>;
#qcom,sensors = <12>;
#thermal-sensor-cells = <1>;
};
tsens1: thermal@10ad000 {
compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
reg = <0x10ad000 0x2000>;
#qcom,sensors = <8>;
#thermal-sensor-cells = <1>;
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
};
apcs_glb: mailbox@9820000 {
compatible = "qcom,msm8998-apcs-hmss-global";
reg = <0x17911000 0x1000>;
#mbox-cells = <1>;
};
blsp2_uart1: serial@c1b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xc1b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
timer@17920000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17920000 0x1000>;
frame@17921000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17921000 0x1000>,
<0x17922000 0x1000>;
};
frame@17923000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17923000 0x1000>;
status = "disabled";
};
frame@17924000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17924000 0x1000>;
status = "disabled";
};
frame@17925000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17925000 0x1000>;
status = "disabled";
};
frame@17926000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17926000 0x1000>;
status = "disabled";
};
frame@17927000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17927000 0x1000>;
status = "disabled";
};
frame@17928000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17928000 0x1000>;
status = "disabled";
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x17a00000 0x10000>, /* GICD */
<0x17b00000 0x100000>; /* GICR * 8 */
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
};

18
arch/arm64/boot/dts/qcom/pm8916.dtsi
View File

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
@@ -18,12 +19,19 @@
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pwrkey@800 {
compatible = "qcom,pm8941-pwrkey";
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
};
pm8916_gpios: gpios@c000 {

18
arch/arm64/boot/dts/qcom/pm8994.dtsi
View File

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/input/linux-event-codes.h>
&spmi_bus {
@@ -17,6 +18,23 @@
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
};
pm8994_gpios: gpios@c000 {
compatible = "qcom,pm8994-gpio";
reg = <0xc000>;

75
arch/arm64/boot/dts/qcom/pm8998.dtsi
View File

@@ -1,8 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* Copyright 2018 Google LLC. */
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/thermal/thermal.h>
/ {
thermal-zones {
pm8998 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&pm8998_temp>;
trips {
pm8998_alert0: pm8998-alert0 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
pm8998_crit: pm8998-crit {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pm8998_lsid0: pmic@0 {
@@ -11,6 +38,52 @@
#address-cells = <1>;
#size-cells = <0>;
pm8998_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
};
pm8998_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
#thermal-sensor-cells = <0>;
};
pm8998_coincell: coincell@2800 {
compatible = "qcom,pm8941-coincell";
reg = <0x2800>;
status = "disabled";
};
pm8998_adc: adc@3100 {
compatible = "qcom,spmi-adc-rev2";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
pm8998_gpio: gpios@c000 {
compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;

40
arch/arm64/boot/dts/qcom/pmi8998.dtsi Normal file
View File

@@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmi8998_lsid0: pmic@2 {
compatible = "qcom,pmi8998", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmi8998_gpio: gpios@c000 {
compatible = "qcom,pmi8998-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
<0 0xc1 0 IRQ_TYPE_NONE>,
<0 0xc2 0 IRQ_TYPE_NONE>,
<0 0xc3 0 IRQ_TYPE_NONE>,
<0 0xc4 0 IRQ_TYPE_NONE>,
<0 0xc5 0 IRQ_TYPE_NONE>,
<0 0xc6 0 IRQ_TYPE_NONE>,
<0 0xc7 0 IRQ_TYPE_NONE>,
<0 0xc8 0 IRQ_TYPE_NONE>,
<0 0xc9 0 IRQ_TYPE_NONE>,
<0 0xca 0 IRQ_TYPE_NONE>,
<0 0xcb 0 IRQ_TYPE_NONE>,
<0 0xcc 0 IRQ_TYPE_NONE>,
<0 0xcd 0 IRQ_TYPE_NONE>;
};
};
pmi8998_lsid1: pmic@3 {
compatible = "qcom,pmi8998", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};

382
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View File

@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sdm845.dtsi"
/ {
@@ -20,6 +21,326 @@
chosen {
stdout-path = "serial0:115200n8";
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
/*
* Apparently RPMh does not provide support for PM8998 S4 because it
* is always-on; model it as a fixed regulator.
*/
vreg_s4a_1p8: pm8998-smps4 {
compatible = "regulator-fixed";
regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vph_pwr>;
};
};
&apps_rsc {
pm8998-rpmh-regulators {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-s11-supply = <&vph_pwr>;
vdd-s12-supply = <&vph_pwr>;
vdd-s13-supply = <&vph_pwr>;
vdd-l1-l27-supply = <&vreg_s7a_1p025>;
vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
vdd-l3-l11-supply = <&vreg_s7a_1p025>;
vdd-l4-l5-supply = <&vreg_s7a_1p025>;
vdd-l6-supply = <&vph_pwr>;
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
vdd-l9-supply = <&vreg_bob>;
vdd-l10-l23-l25-supply = <&vreg_bob>;
vdd-l13-l19-l21-supply = <&vreg_bob>;
vdd-l16-l28-supply = <&vreg_bob>;
vdd-l18-l22-supply = <&vreg_bob>;
vdd-l20-l24-supply = <&vreg_bob>;
vdd-l26-supply = <&vreg_s3a_1p35>;
vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
vreg_s2a_1p125: smps2 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
vreg_s3a_1p35: smps3 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_s5a_2p04: smps5 {
regulator-min-microvolt = <1904000>;
regulator-max-microvolt = <2040000>;
};
vreg_s7a_1p025: smps7 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1028000>;
};
vdd_qusb_hs0:
vdda_hp_pcie_core:
vdda_mipi_csi0_0p9:
vdda_mipi_csi1_0p9:
vdda_mipi_csi2_0p9:
vdda_mipi_dsi0_pll:
vdda_mipi_dsi1_pll:
vdda_qlink_lv:
vdda_qlink_lv_ck:
vdda_qrefs_0p875:
vdda_pcie_core:
vdda_pll_cc_ebi01:
vdda_pll_cc_ebi23:
vdda_sp_sensor:
vdda_ufs1_core:
vdda_ufs2_core:
vdda_usb1_ss_core:
vdda_usb2_ss_core:
vreg_l1a_0p875: ldo1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_10:
vreg_l2a_1p2: ldo2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l3a_1p0: ldo3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_wcss_cx:
vdd_wcss_mx:
vdda_wcss_pll:
vreg_l5a_0p8: ldo5 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_13:
vreg_l6a_1p8: ldo6 {
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <1856000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a_1p8: ldo7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a_1p2: ldo8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1248000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a_1p8: ldo9 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10a_1p8: ldo10 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11a_1p0: ldo11 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1048000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_qfprom:
vdd_qfprom_sp:
vdda_apc1_cs_1p8:
vdda_gfx_cs_1p8:
vdda_qrefs_1p8:
vdda_qusb_hs0_1p8:
vddpx_11:
vreg_l12a_1p8: ldo12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_2:
vreg_l13a_2p95: ldo13 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14a_1p88: ldo14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15a_1p8: ldo15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16a_2p7: ldo16 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17a_1p3: ldo17 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18a_2p7: ldo18 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l19a_3p0: ldo19 {
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <3104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l20a_2p95: ldo20 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l21a_2p95: ldo21 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l22a_2p85: ldo22 {
regulator-min-microvolt = <2864000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l23a_3p3: ldo23 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_qusb_hs0_3p1:
vreg_l24a_3p075: ldo24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l25a_3p3: ldo25 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_hp_pcie_1p2:
vdda_hv_ebi0:
vdda_hv_ebi1:
vdda_hv_ebi2:
vdda_hv_ebi3:
vdda_mipi_csi_1p25:
vdda_mipi_dsi0_1p2:
vdda_mipi_dsi1_1p2:
vdda_pcie_1p2:
vdda_ufs1_1p2:
vdda_ufs2_1p2:
vdda_usb1_ss_1p2:
vdda_usb2_ss_1p2:
vreg_l26a_1p2: ldo26 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l28a_3p0: ldo28 {
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_lvs1a_1p8: lvs1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs2a_1p8: lvs2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
pmi8998-rpmh-regulators {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
vdd-bob-supply = <&vph_pwr>;
vreg_bob: bob {
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3600000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
regulator-allow-bypass;
};
};
pm8005-rpmh-regulators {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vreg_s3c_0p6: smps3 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
};
};
};
&i2c10 {
@@ -35,6 +356,67 @@
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
/* Until we have Type C hooked up we'll force this as host. */
dr_mode = "host";
};
&usb_1_hsphy {
status = "okay";
vdd-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
qcom,imp-res-offset-value = <8>;
qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
};
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb1_ss_1p2>;
vdda-pll-supply = <&vdda_usb1_ss_core>;
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
/*
* Though the USB block on SDM845 can support host, there's no vbus
* signal for this port on MTP. Thus (unless you have a non-compliant
* hub that works without vbus) the only sensible thing is to force
* peripheral mode.
*/
dr_mode = "peripheral";
};
&usb_2_hsphy {
status = "okay";
vdd-supply = <&vdda_usb2_ss_core>;
vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
qcom,imp-res-offset-value = <8>;
qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
};
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
};
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
&qup_i2c10_default {

300
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@@ -5,9 +5,12 @@
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -230,6 +233,94 @@
hwlocks = <&tcsr_mutex 3>;
};
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 6>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-lpass {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-mpss {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 26>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
slpi_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
slpi_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -249,6 +340,23 @@
#power-domain-cells = <1>;
};
qfprom@784000 {
compatible = "qcom,qfprom";
reg = <0x784000 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
qusb2p_hstx_trim: hstx-trim-primary@1eb {
reg = <0x1eb 0x1>;
bits = <1 4>;
};
qusb2s_hstx_trim: hstx-trim-secondary@1eb {
reg = <0x1eb 0x2>;
bits = <6 4>;
};
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x6000>;
@@ -962,6 +1070,192 @@
};
};
usb_1_hsphy: phy@88e2000 {
compatible = "qcom,sdm845-qusb2-phy";
reg = <0x88e2000 0x400>;
status = "disabled";
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2p_hstx_trim>;
};
usb_2_hsphy: phy@88e3000 {
compatible = "qcom,sdm845-qusb2-phy";
reg = <0x88e3000 0x400>;
status = "disabled";
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
nvmem-cells = <&qusb2s_hstx_trim>;
};
usb_1_qmpphy: phy@88e9000 {
compatible = "qcom,sdm845-qmp-usb3-phy";
reg = <0x88e9000 0x18c>,
<0x88e8000 0x10>;
reg-names = "reg-base", "dp_com";
status = "disabled";
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: lane@88e9200 {
reg = <0x88e9200 0x128>,
<0x88e9400 0x200>,
<0x88e9c00 0x218>,
<0x88e9a00 0x100>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
};
usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
reg = <0x88eb000 0x18c>;
status = "disabled";
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
usb_2_ssphy: lane@88eb200 {
reg = <0x88eb200 0x128>,
<0x88eb400 0x1fc>,
<0x88eb800 0x218>,
<0x88e9600 0x70>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_uni_phy_pipe_clk_src";
};
};
usb_1: usb@a6f8800 {
compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
reg = <0xa6f8800 0x400>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
usb_1_dwc3: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usb_2: usb@a8f8800 {
compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
reg = <0xa8f8800 0x400>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep";
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
resets = <&gcc GCC_USB30_SEC_BCR>;
usb_2_dwc3: dwc3@a800000 {
compatible = "snps,dwc3";
reg = <0xa800000 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
reg = <0xaf00000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
reg = <0xc263000 0x1ff>, /* TM */
@@ -978,6 +1272,12 @@
#thermal-sensor-cells = <1>;
};
aoss_reset: reset-controller@c2a0000 {
compatible = "qcom,sdm845-aoss-cc";
reg = <0xc2a0000 0x31000>;
#reset-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,

2
arch/arm64/boot/dts/renesas/Makefile
View File

@@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb

1663
arch/arm64/boot/dts/renesas/r8a774a1.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

3
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
View File

@@ -40,12 +40,11 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};

18
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the r8a7795 ES1.x SoC
* Device Tree Source for the R-Car H3 (R8A77950) ES1.x SoC
*
* Copyright (C) 2015 Renesas Electronics Corp.
*/
@@ -232,7 +232,7 @@
port@1 {
vin0csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin0>;
remote-endpoint = <&csi21vin0>;
};
};
};
@@ -243,7 +243,7 @@
port@1 {
vin1csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin1>;
remote-endpoint = <&csi21vin1>;
};
};
};
@@ -254,7 +254,7 @@
port@1 {
vin2csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin2>;
remote-endpoint = <&csi21vin2>;
};
};
};
@@ -265,7 +265,7 @@
port@1 {
vin3csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin3>;
remote-endpoint = <&csi21vin3>;
};
};
};
@@ -276,7 +276,7 @@
port@1 {
vin4csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin4>;
remote-endpoint = <&csi21vin4>;
};
};
};
@@ -287,7 +287,7 @@
port@1 {
vin5csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin5>;
remote-endpoint = <&csi21vin5>;
};
};
};
@@ -298,7 +298,7 @@
port@1 {
vin6csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin6>;
remote-endpoint = <&csi21vin6>;
};
};
};
@@ -309,7 +309,7 @@
port@1 {
vin7csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin7>;
remote-endpoint = <&csi21vin7>;
};
};
};

3
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
View File

@@ -41,11 +41,10 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&versaclock5 3>,
<&versaclock5 4>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};

3
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
View File

@@ -40,12 +40,11 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock5 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};

17
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
View File

@@ -40,12 +40,11 @@
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>,
<&versaclock6 1>,
<&x21_clk>,
<&x22_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
clock-names = "du.0", "du.1", "du.2", "du.3",
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
};
@@ -152,6 +151,15 @@
};
};
&pca9654 {
pcie_sata_switch {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-low; /* enable SATA by default */
line-name = "PCIE/SATA switch";
};
};
&pfc {
usb2_pins: usb2 {
groups = "usb2";
@@ -176,6 +184,11 @@
};
};
/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
&sata {
status = "okay";
};
&usb2_phy2 {
pinctrl-0 = <&usb2_pins>;
pinctrl-names = "default";

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