[MIPS] MIPS32/MIPS64 secondary cache management
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle

parent
f7a849153b
commit
9318c51acd
@@ -597,8 +597,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
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break;
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case PRID_IMP_25KF:
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c->cputype = CPU_25KF;
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/* Probe for L2 cache */
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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break;
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case PRID_IMP_34K:
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c->cputype = CPU_34K;
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