Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM updates from Paolo Bonzini:
"Small release, the most interesting stuff is x86 nested virt
improvements.
x86:
- userspace can now hide nested VMX features from guests
- nested VMX can now run Hyper-V in a guest
- support for AVX512_4VNNIW and AVX512_FMAPS in KVM
- infrastructure support for virtual Intel GPUs.
PPC:
- support for KVM guests on POWER9
- improved support for interrupt polling
- optimizations and cleanups.
s390:
- two small optimizations, more stuff is in flight and will be in
4.11.
ARM:
- support for the GICv3 ITS on 32bit platforms"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (94 commits)
arm64: KVM: pmu: Reset PMSELR_EL0.SEL to a sane value before entering the guest
KVM: arm/arm64: timer: Check for properly initialized timer on init
KVM: arm/arm64: vgic-v2: Limit ITARGETSR bits to number of VCPUs
KVM: x86: Handle the kthread worker using the new API
KVM: nVMX: invvpid handling improvements
KVM: nVMX: check host CR3 on vmentry and vmexit
KVM: nVMX: introduce nested_vmx_load_cr3 and call it on vmentry
KVM: nVMX: propagate errors from prepare_vmcs02
KVM: nVMX: fix CR3 load if L2 uses PAE paging and EPT
KVM: nVMX: load GUEST_EFER after GUEST_CR0 during emulated VM-entry
KVM: nVMX: generate MSR_IA32_CR{0,4}_FIXED1 from guest CPUID
KVM: nVMX: fix checks on CR{0,4} during virtual VMX operation
KVM: nVMX: support restore of VMX capability MSRs
KVM: nVMX: generate non-true VMX MSRs based on true versions
KVM: x86: Do not clear RFLAGS.TF when a singlestep trap occurs.
KVM: x86: Add kvm_skip_emulated_instruction and use it.
KVM: VMX: Move skip_emulated_instruction out of nested_vmx_check_vmcs12
KVM: VMX: Reorder some skip_emulated_instruction calls
KVM: x86: Add a return value to kvm_emulate_cpuid
KVM: PPC: Book3S: Move prototypes for KVM functions into kvm_ppc.h
...
Этот коммит содержится в:
Linus Torvalds
@@ -191,6 +191,8 @@ enum {
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#define PFERR_RSVD_BIT 3
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#define PFERR_FETCH_BIT 4
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#define PFERR_PK_BIT 5
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#define PFERR_GUEST_FINAL_BIT 32
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#define PFERR_GUEST_PAGE_BIT 33
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#define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT)
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#define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT)
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@@ -198,6 +200,13 @@ enum {
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#define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT)
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#define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT)
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#define PFERR_PK_MASK (1U << PFERR_PK_BIT)
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#define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT)
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#define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT)
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#define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \
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PFERR_USER_MASK | \
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PFERR_WRITE_MASK | \
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PFERR_PRESENT_MASK)
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/* apic attention bits */
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#define KVM_APIC_CHECK_VAPIC 0
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@@ -1062,6 +1071,7 @@ unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
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void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
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int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
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bool pdptrs_changed(struct kvm_vcpu *vcpu);
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int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
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const void *val, int bytes);
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@@ -1124,7 +1134,8 @@ int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr);
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struct x86_emulate_ctxt;
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int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port);
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void kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
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int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port);
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int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
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int kvm_emulate_halt(struct kvm_vcpu *vcpu);
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int kvm_vcpu_halt(struct kvm_vcpu *vcpu);
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int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
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@@ -1203,7 +1214,7 @@ void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu);
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int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
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int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code,
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int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u64 error_code,
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void *insn, int insn_len);
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void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
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void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu);
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@@ -1358,7 +1369,8 @@ void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
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bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu);
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extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
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void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
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int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu);
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int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
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int kvm_is_in_guest(void);
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@@ -25,6 +25,7 @@
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#define VMX_H
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#include <linux/bitops.h>
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#include <linux/types.h>
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#include <uapi/asm/vmx.h>
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@@ -60,6 +61,7 @@
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*/
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#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
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#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
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#define SECONDARY_EXEC_DESC 0x00000004
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#define SECONDARY_EXEC_RDTSCP 0x00000008
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#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
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#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
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@@ -110,6 +112,36 @@
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#define VMX_MISC_SAVE_EFER_LMA 0x00000020
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#define VMX_MISC_ACTIVITY_HLT 0x00000040
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static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
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{
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return vmx_basic & GENMASK_ULL(30, 0);
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}
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static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
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{
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return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
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}
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static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
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{
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return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
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}
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static inline int vmx_misc_cr3_count(u64 vmx_misc)
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{
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return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
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}
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static inline int vmx_misc_max_msr(u64 vmx_misc)
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{
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return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
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}
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static inline int vmx_misc_mseg_revid(u64 vmx_misc)
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{
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return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
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}
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/* VMCS Encodings */
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enum vmcs_field {
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VIRTUAL_PROCESSOR_ID = 0x00000000,
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@@ -399,10 +431,11 @@ enum vmcs_field {
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#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
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#define VMX_NR_VPIDS (1 << 16)
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#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
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#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
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#define VMX_VPID_EXTENT_ALL_CONTEXT 2
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#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3
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#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0
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#define VMX_EPT_EXTENT_CONTEXT 1
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#define VMX_EPT_EXTENT_GLOBAL 2
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#define VMX_EPT_EXTENT_SHIFT 24
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@@ -419,8 +452,10 @@ enum vmcs_field {
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#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
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#define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */
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#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8) /* (40 - 32) */
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#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
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#define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
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#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11) /* (43 - 32) */
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#define VMX_EPT_DEFAULT_GAW 3
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#define VMX_EPT_MAX_GAW 0x4
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@@ -65,6 +65,8 @@
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#define EXIT_REASON_TPR_BELOW_THRESHOLD 43
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#define EXIT_REASON_APIC_ACCESS 44
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#define EXIT_REASON_EOI_INDUCED 45
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#define EXIT_REASON_GDTR_IDTR 46
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#define EXIT_REASON_LDTR_TR 47
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#define EXIT_REASON_EPT_VIOLATION 48
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#define EXIT_REASON_EPT_MISCONFIG 49
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#define EXIT_REASON_INVEPT 50
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@@ -113,6 +115,8 @@
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{ EXIT_REASON_MCE_DURING_VMENTRY, "MCE_DURING_VMENTRY" }, \
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{ EXIT_REASON_TPR_BELOW_THRESHOLD, "TPR_BELOW_THRESHOLD" }, \
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{ EXIT_REASON_APIC_ACCESS, "APIC_ACCESS" }, \
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{ EXIT_REASON_GDTR_IDTR, "GDTR_IDTR" }, \
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{ EXIT_REASON_LDTR_TR, "LDTR_TR" }, \
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{ EXIT_REASON_EPT_VIOLATION, "EPT_VIOLATION" }, \
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{ EXIT_REASON_EPT_MISCONFIG, "EPT_MISCONFIG" }, \
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{ EXIT_REASON_INVEPT, "INVEPT" }, \
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@@ -129,6 +133,7 @@
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{ EXIT_REASON_XRSTORS, "XRSTORS" }
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#define VMX_ABORT_SAVE_GUEST_MSR_FAIL 1
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#define VMX_ABORT_LOAD_HOST_PDPTE_FAIL 2
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#define VMX_ABORT_LOAD_HOST_MSR_FAIL 4
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#endif /* _UAPIVMX_H */
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Ссылка в новой задаче
Block a user